Abstract: A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided.

Abstract: Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter structure capable of reducing the current crowding effect and preventing thermal instabilities is disclosed, wherein a negative differential resistance. (NDR) element is added to the layer structure of the conventional emitter. In accordance with the invention, the NDR element can be implemented, for example, by a Resonant Tunnel Diode (RTD) or an Esaki Diode structure. The NDR element is designed to limit the tunneling current to the maximal emitter current density required for safe transistor operation, thereby also reducing the current crowding effect.

Abstract: A semiconductor device including a bipolar transistor formed by epitaxial growth or ion implantation is provided has an epitaxial silicon collector layer, a base region directly under an emitter defined as an intrinsic base and a peripheral region thereof defined as an outer base region is formed by the step of implanting ions into the collector layer to form a high concentration collector region at a location close to a buried region using a photoresist to form an aperture, and the step of implanting ions into the collector layer to form a high concentration collector region directly beneath the base region after forming the base region.

Abstract: A process used in the fabrication of a self-aligned non-selective thin-epi-base silicon germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS. The process involves using TEOS or Spin-On-Glass (SOG) silicon dioxide etchback in the fabrication of the SiGe BiCMOS device.

Abstract: A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer surrounding the ledge; a base layer formed on the ledge of the collector layer; an ohmic cap layer on the emitter layer; an emitter layer formed in the center of the base layer; an emitter electrode formed on the ohmic cap layer; a base electrode formed on the base layer surrounding the emitter electrode; an insulating layer formed to cover the base electrode and to overlay on the insulating layer; a metal wire formed to cover the emitter electrode; and an air bridge brought in contact with the metal wire and electrically connected to an external pad lying on an ion-implanted isolation region.

Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.

Abstract: A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.

Abstract: A method for fabricating a bipolar transistor comprising the steps of implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the farther step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material.

Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.

Abstract: A process used in the fabrication of a self-aligned non-selective thin-epi-base silicon germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS. The process involves using TEOS or Spin-On-Glass (SOG) silicon dioxide etchback in the fabrication of the SiGe BiCMOS device.

Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

Abstract: A partial oxide film on a base region is removed to form an opening, a polycrystalline silicon film is deposited directly thereon, and by dry etching, the polycrystalline silicon film is divided into a region including an impurity of same conductive type as the base, and a region including an impurity of reverse conductive type of the base. By heat treatment, the impurity is diffused from the polycrystalline silicon film into the base region, and an external base diffusion layer and an emitter diffusion layer are formed. In succession, the surface of the polycrystalline silicon film is formed into polyside film to lower the resistance, and by using the polycrystalline silicon film as emitter electrode and base electrode, a fine base and emitter area is realized.

Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.

Abstract: A heterojunction bipolar transistor based on the InP/InGaAs materials family and its method of making. An n-type collector layer, principally composed of InP is epitaxially grown on an insulating InP substrate by vapor phase epitaxy. The collector layer is then laterally defined into a stack, and semi-insulating InP is regrown around the sides of the stack to the extent that it planarizes with the stack top. The semi-insulating InP electrically isolates the collector stack. A thin base layer of p-type InGaAs, preferably lattice matched to InP, is grown over the collector stack, and an n-type emitter layer is grown over the base layer. A series of photolithographic steps then defines a small emitter stack and a base that extends outside of the area of the emitter and collector stacks. The reduced size of the interface between the base and the collector produces a lower base-collector capacitance and hence higher speed of operation for the transistor.

Abstract: A manufacturing method of the present invention comprises the first step of forming an epitaxial base layer in an opening of an element-isolating oxide film on a semiconductor substrate in a non-selection condition, the second step of growing a silicon oxide film on the epitaxial base layer and a base polysilicon layer, and the third step of etching the silicon oxide film to expose the polysilicon layer by the etch-back or the CMP. According to this method, the silicon oxide film is left only on the epitaxial base layer, and the planarization of the device can be attained. The present invention also reduces the resistance of the base electrode by providing silicide to the device.

Abstract: A semiconductor device including a bipolar transistor is provided, which can reduce the base resistance of the transistor. This device includes a semiconductor base region having a first semiconductor active region of a first conductivity type in its inside. A first insulating layer is formed on the main surface of the substructure to cover the first active region. The first insulating layer has a first penetrating window exposing the first active region. A semiconductor contact region of a second conductivity type is formed on the first insulating layer. The contact region has an overhanging part which overhangs the first window. The second window is defined by the inner end of the overhanging part to be entirely overlapped with the first window. The contact region is made of a polycrystalline semiconductor. A second semiconductor active region of the second conductivity type is formed on the first active region in the first window.

Abstract: A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.

Abstract: A method of fabricating an HBT using differential epitaxy. By using an emitter mask and an exside-inside spacer structure, a self-aligned fabrication of an emitter contact and a base contact is carried out. The emitter contact layer is made from amorphous silicon. Since the entire process sequence is very temperature-stable and can be carried out at lower implantation energies than conventional methods, HBT's having a high layer quality can be fabricated by the method of the invention which is suitable for mass production and with which high oscillation frequencies can be accomplished.

Abstract: A method for producing a bipolar semiconductor device having a first layer doped according to a first doping type, the first layer being adapted to have minority charge carriers injected thereinto from a second layer of the device of a doping type opposite to that of the first layer in a forward conducting state of the device, comprises the steps of a) epitaxially growing the first layer and b) providing at least one region of the first layer with the minority charge carriers having a lifetime lower than in other parts of the first layer, the lower lifetime region of the first layer being formed directly during the epitaxial growth of this region by changing composition of substances fed to the first layer for the growth thereof when the region is grown.

Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

Abstract: In a BiMOS semiconductor device, emitter and base electrodes formed by polycrystalline Si of a bipolar transistor are isolated from each other by way of a sidewall and an insulator layer. As this insulator layer acts as an offset during the formation of the sidewall, its layer thickness can be made larger. Further, as this insulator layer is not provided in a MOS region, its step can be made smaller. Consequently, parasitic capacitance can be reduced while the insulator layer can be made thicker. Thus, there can be achieved both fast operation and high reliability of the bipolar transistor and, moreover, reduction in the reliability of a MOS transistor can also be prevented.

Abstract: A semiconductor device is manufactured by a process comprising the steps of forming a cover film on a surface of a semiconductor substrate such that the cover film exposes a portion of the surface, covers a remaining portion thereof and has an edge along a boundary between the exposed portion and the covered portion, forming a first conductor film in a range from the cover film formed in the cover film forming step through the edge to the exposed surface portion of the semiconductor substrate, removing the first conductor film formed in the first conductor film forming step other than a portion formed along the edge such that the first conductor film is left along the edge, forming an insulating film on the opposite sides of the first conductor film left along the edge in the removing step such that a top edge of the left first conductor film is exposed, and forming a second conductor film on the surface of the insulating film formed in the insulating film forming step along the exposed top edge of the first

Abstract: A method of fabricating a bipolar transistor includes successively growing a collector layer, a base layer, and a crystalline mask layer on a semiconductor substrate; forming an opening in the crystalline mask layer to expose a portion of the base layer; growing an emitter layer on the crystalline mask layer and on the base layer exposed in the opening of the mask layer; forming an emitter electrode on the emitter layer; removing part of the emitter layer using the emitter electrode as a mask; removing the crystalline mask layer; forming a first resist pattern for formation of base electrodes; forming base electrodes using the first resist pattern and the emitter electrode as masks; removing the first resist pattern; forming a second resist pattern for formation of collector electrodes covering base electrodes and the emitter electrode; using the second resist pattern as a mask, removing portions of the base layer and the collector layer; and forming collector electrodes in contact with the collector layer.

Abstract: A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Abstract: A submicron emitter heterojunction bipolar transistor and a method for fabricating the same is disclosed. The fabrication process includes lattice matched growth of subcollector, collector, base, emitter, and emitter cap layers in sequential order on a semi-insulating semiconductor substrate. An emitter cap mesa, an emitter/base/collector mesa and a subcollector mesa are formed. Dielectric platforms are formed extending the base/collector layers laterally. Sidewalls are formed on the sides of emitter cap mesa and the sides of the extended base/collector layers and undercuts are etched into the emitter layer and the upper portion of the subcollector layer. This forms an overhang on the emitter cap mesa with respect to the emitter layer and an overhang on the base/collector layers with respect to the upper portion of the subcollector layer.

Abstract: A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

Abstract: The lateral base resistance of a DHBT device is reduced and its high-speed operating characteristics thereby improved by forming a structure that initially includes a relatively thick extrinsic base layer overlying a relatively thin intrinsic base layer. The extrinsic base layer is then etched to form a window in which an emitter layer is deposited. In that way, the growth time for formation of the base-emitter junction is minimized. High-performance devices are thereby realized in a relatively simple process that has advantageous self-alignment features.

Abstract: A heterojunction bipolar transistor. An active region is defined on a silicon collector layer. A silicon-germanium base layer characterized by an integral polycrystalline and epitaxial structure is deposited over the collector such that the epitaxial portion of the base covers substantially the entire active region of the collector. In one version, a field oxide region separates the polycrystalline part of the base layer from the remainder of the collector layer. Alternatively, the collector layer is also characterized by an integral polycrystalline and epitaxial structure; in this version the epitaxial part of the base overlies the epitaxial part of the collector.

Abstract: A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.

Abstract: Regulation of eucaryotic gene expression is controlled by procaryotic peptides. The peptides recognize specific DNA sequences present in the gene, which may be derived from procaryotic genes, and either activate or repress gene transcription. Hybrid procaryotic peptides may be used containing both repressor and activator peptides.