Having Lateral Bipolar Transistor Patents (Class 438/327)
  • Patent number: 9099385
    Abstract: Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: August 4, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 8921194
    Abstract: Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: David L. Harame, Qizhi Liu
  • Patent number: 8796100
    Abstract: The present invention discloses a method of manufacturing an N-type LDMOS device. The method comprises forming a gate above the semiconductor substrate; forming a body, comprising forming a Pwell apart from the gate and forming a Pbase partly in the Pwell, wherein the Pbase is wider and shallower than the Pwell; and forming an N-type source and a drain contact region. Wherein the body curvature of the LDMOS device is controlled by adjusting the layout width of the Pwell.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 5, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Jeesung Jung
  • Patent number: 8772141
    Abstract: A method for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski
  • Patent number: 8772910
    Abstract: A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bhupesh Chandra, George Stojan Tulevski
  • Patent number: 8431450
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Patent number: 8415764
    Abstract: An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Wen Chung, Po-Yao Ke, Wei-Yang Lin, Shine Chung
  • Patent number: 8378392
    Abstract: A trench Metal Oxide Semiconductor Field Effect Transistor with improved body region structures is disclosed. By forming the inventive body region structures with concave-arc shape with respect to epitaxial layer, a wider interfaced area between the body region and the epitaxial layer is achieved, thus increasing capacitance between drain and source Cds. Moreover, the invention further comprises a Cds enhancement doped region interfaced with said body region having higher doping concentration than the epitaxial layer to further enhancing Cds without significantly impact breakdown voltage.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8043962
    Abstract: A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong Ha Jung, Baek Mann Kim, Soo Hyun Kim, Young Jin Lee, Sun Woo Hwang, Jeong Tae Kim
  • Patent number: 8030167
    Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, Bradley A. Orner, Jay S. Rascoe, David C. Sheridan, Stephen A. St. Onge
  • Patent number: 7868378
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: January 11, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Patent number: 7727847
    Abstract: A light-absorbing layer is selectively formed over an insulating surface, an insulating layer is formed over the insulating surface and the light-absorbing layer, the insulating surface, the light-absorbing layer, and the insulating layer are irradiated with laser light to selectively remove only the insulating layer above the light-absorbing layer in an irradiated region of the insulating layer so that an opening reaching the light-absorbing layer is formed in the insulating layer, and a conductive film is formed in the opening so as to be in contact with the light-absorbing layer. By forming the conductive film in the opening so as to be in contact with the exposed light-absorbing layer, the conductive film can be electrically connected to the light-absorbing layer with the insulating layer interposed therebetween.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: June 1, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yasuyuki Arai
  • Patent number: 7666749
    Abstract: Provided are a SiGe semiconductor device and a method of manufacturing the same.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: February 23, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Hun Kim, Hyun Cheol Bae, Sang Heung Lee
  • Publication number: 20090305477
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Application
    Filed: July 30, 2009
    Publication date: December 10, 2009
    Inventors: Thomas Bottner, Stefan Draxl, Thomas Huttner, Martin Seck
  • Patent number: 7541250
    Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 2, 2009
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • Patent number: 7442617
    Abstract: A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the third well region to form a base electrode pattern; forming a spacer on a sidewalls of the base electrode pattern; implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and performing a diffusion process to form a base region adjacent to the emitter region.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: October 28, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Woong Je Sung
  • Patent number: 7422952
    Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: September 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
  • Patent number: 7348250
    Abstract: Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has lower ramp rate.
    Type: Grant
    Filed: January 22, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventor: Gregory G. Freeman
  • Patent number: 7329584
    Abstract: A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the semiconductor substrate; forming an emitter electrode pattern on the third well region, and forming a collector electrode pattern on the second well region; forming spacers at sidewalls of the emitter and collector electrode patterns; performing a diffusion process to form an emitter region of a first conductivity on the third well region and to form a collector region of a first conductivity on the second well region; implanting ions of a second conductivity in the third well region to form a base region; and removing the emitter electrode and collector region patterns.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: February 12, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Woong Je Sung
  • Patent number: 7217609
    Abstract: A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n+-type contact from the upper surface of the substrate to the buried n+-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: May 15, 2007
    Assignee: Infineon Technologies AG
    Inventors: Hans Norström, Ted Johansson
  • Patent number: 6987039
    Abstract: A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The method includes the steps of forming emitter and collector contacts by implants used in source/drain regions; forming an emitter that includes implants done in core pMOS during core pMOS LDD extender and pocket implant steps and while the collector omits the core pMOS LDD extender and pocket implants; forming a base region below the emitter and collector contacts by the n-well region with said base region going laterally from emitter to collector being the n-well and including pocket implants; and forming base contact by said n-well region and by implants used in nMOS source/drain regions.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: January 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Amitava Chatterjee
  • Patent number: 6972237
    Abstract: A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: December 6, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Purakh Raj Verma, Shao-fu Sanford Chu, Lap Chan, Jia Zhen Zheng, Jian Xun Li
  • Patent number: 6864540
    Abstract: The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corp.
    Inventors: Rama Divakaruni, Louis C. Hsu, Rajiv V. Joshi, Carl J. Radens
  • Patent number: 6861325
    Abstract: A method for fabricating a lateral bipolar junction transistor in an active area of a substrate includes forming a base structure directly on a central portion of the active area without a gate oxide layer being formed on the substrate. The method also includes implanting a first type of dopant into the active area for forming an emitter region and a collector region, and forming contacts and interconnects for the base structure and emitter and collector regions.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: March 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James N. Pan, Matthew Buynoski
  • Patent number: 6800531
    Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: October 5, 2004
    Assignee: Rockwell Scientific Licensing, LLC
    Inventors: Richard L. Pierson, Jr., James Chingwei Li, Berinder P. S. Brar, John A. Higgins
  • Patent number: 6784065
    Abstract: A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow through the transistor, while the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: August 31, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Abdalla Aly Naem
  • Patent number: 6610578
    Abstract: A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer. A base region in the active region is defined by a well-defined opening, which is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: August 26, 2003
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Hans Norström, Stefan Nygren, Ola Tylstedt
  • Patent number: 6573149
    Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: June 3, 2003
    Assignee: Agere Systems Inc.
    Inventors: Isik C. Kizilyalli, Ranbir Singh, Lori Stirling
  • Patent number: 6518139
    Abstract: A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: February 11, 2003
    Assignee: CO.RI.M.ME Consorzio per la Sulla Microelectronica nel Mezzogiorno
    Inventors: Natale Aiello, Davide Patti, Salvatore Scaccianoce, Salvatore Leonardi
  • Patent number: 6492238
    Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: David C. Ahlgren, Gregory G. Freeman, Feng-Yi Huang, Adam D. Ticknor
  • Patent number: 6489211
    Abstract: A method of manufacturing a semiconductor component includes providing a composite substrate (300) with a dielectric portion and a semiconductor portion and growing an epitaxial layer (400) over the composite substrate. The epitaxial layer has a polycrystalline portion (402) over the dielectric portion of the composite substrate and also has a monocrystalline portion (401) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: December 3, 2002
    Assignee: Motorola, Inc.
    Inventors: John L. Freeman, Jr., Raymond J. Balda, Robert A. Pryor, James D. Paulsen, Robert J. Johnsen
  • Patent number: 6384433
    Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: May 7, 2002
    Assignee: RF Micro Devices, Inc.
    Inventors: Curtis A. Barratt, Arthur E. Geissberger, Larry W. Kapitan, Michael T. Fresina, Ramond Jeffrey Vass
  • Patent number: 6358786
    Abstract: A lateral bipolar field effect transistor having a drift region of a first conductivity formed on a silicon-on insulation substrate with a buried insulation layer, a gate region of a second conductivity formed over and from the buried insulation layer separated by a channel depth, in the drift region, a source region of the first conductivity contacting with the gate region and formed on the buried insulation layer, and a drain region of the first conductivity opposite to the source region, the drain region separated from the gate region by a selected distance. The gate region comprises a plurality of cells arranged parallel to an extension of the source region, each cell separated from adjacent cell by a channel width.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: March 19, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong Dong Kim
  • Patent number: 6352887
    Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: March 5, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Louis N. Hutter, Peter Ying, Marco Corsi, Imran Khan
  • Patent number: 6337220
    Abstract: An ion implanter vacuum integrity check process and apparatus that enables a vacuum integrity check at a pressure substantially below the ion implantation process pressure, while storing an ion implantation process pressure set point for a subsequent ion implantation process. An ion implanter includes an end station chamber, a high vacuum system, a disk, a gas supply system and a controller for storing at least a vacuum integrity check pressure set point and an ion implantation process pressure set point. A disk inserted into the end station is accelerated to a predetermined rotational speed, while the high vacuum system is used to pump down the end station chamber. The end station chamber is, then, purged with an inert gas for a first predetermined time period, while maintaining the disk rotational speed and continuing to pump down the end station chamber. The pressure of the end station chamber is monitored, while the disk rotational speed and pumping of the chamber are maintained.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: January 8, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Donald L. Wilcox, Randy M. Underwood
  • Patent number: 6326664
    Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: December 4, 2001
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Paul A. Packan, Leopoldo D. Yau
  • Patent number: 6291303
    Abstract: A method of forming an improved bipolar junction device structure. By forming a well region around the emitter terminal, the area of distribution of ions within the emitter terminal of a vertical bipolar junction transistor is enlarged. Furthermore, by forming a separate well region around the emitter terminal and the collector terminal, the area of distribution of ions within the emitter terminal and the collector terminal of a lateral bipolar junction transistor is also enlarged.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: September 18, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Ming-Tsung Tung
  • Patent number: 6265277
    Abstract: In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the disclosed method are advantageously used to protect MOS type integrated circuits against electrical discharges.
    Type: Grant
    Filed: December 24, 1998
    Date of Patent: July 24, 2001
    Assignee: SGS-Thomson Microelectronics S.A
    Inventor: François Tailliet
  • Patent number: 6216099
    Abstract: A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: April 10, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peng Fang, Sunil Shabde
  • Patent number: 6174779
    Abstract: In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: January 16, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Shino, Takashi Yamada, Makoto Yoshimi, Shigeru Kawanaka, Hideaki Nii, Kazumi Inoh, Tsuneaki Fuse, Sadayuki Yoshitomi, Mamoru Terauchi
  • Patent number: 6165860
    Abstract: There is provided a method of fabricating a semiconductor device, including the steps of, in sequence, (a) partially forming a buried layer in a semiconductor substrate and also forming an epitaxial layer on the buried layer, (b) forming a collector region in the epitaxial layer by selectively introducing impurities into the epitaxial layer so that the collector region reaches the buried layer, (c) forming an insulating film on the epitaxial layer, (d) forming a polysilicon film on the insulating film, (e) patterning the polysilicon film to form a base electrode, (f) forming an interlayer insulating film over the base electrode and the insulating film, (g) patterning both the interlayer insulating film and the base electrode to form a base opening at a region at which a base region is to be formed and a collector opening above the collector region, (h) side-etching portions of the insulating film located below the base electrode to form undercut hollow portions in the insulating film, (i) filling the undercut
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: December 26, 2000
    Assignee: NEC Corporation
    Inventor: Takeshi Watanabe
  • Patent number: 6033964
    Abstract: Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source voltage and channel length. The present invention increases the speed of a circuit by decreasing the channel length of subset of transistors in the circuit. The subset is chosen by identifying instances where more than one transistor in series is used to discharge a capacitance. Those transistors are subject to lower drain to source voltages; therefore, the channel length can be reduced without suffering from the effects of HCI.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: March 7, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Donald A. Draper
  • Patent number: 6001770
    Abstract: A dye-donor element for thermal dye transfer comprising a support having on one side thereof a dye layer and on the other side a slipping layer comprising a binder containing polyalkylsilsesquioxane particles wherein less than about 8% of the particles have a diameter of >0.8 .mu.m.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: December 14, 1999
    Inventors: William H. Simpson, Jacob J. Hastreiter, Jr., Ronald M. Wexler, Daniel F. Hurley, George B. Bodem
  • Patent number: 5885880
    Abstract: A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is formed by high-energy ion implantation after formation of the n.sup.+ type buried collector region of the vertical NPN transistor, and a p.sup.+ type buried collector region of the vertical PNP transistor is formed subsequently to formation of an n-type epitaxial layer and a device separating region whereby the thickness of the n-type epitaxial layer is optimized to a required minimum value. A method for producing a semiconductor device is also provided in which a first vertical bipolar transistor of a first conductivity type and a second vertical bipolar transistor of a second conductivity type, electrically isolated from each other, are formed on a semiconductor substrate having a pre-set conductivity type.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: March 23, 1999
    Assignee: Sony Corporation
    Inventor: Takayuki Gomi