Complementary Bipolar Transistors Patents (Class 438/322)
  • Patent number: 9525029
    Abstract: An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure. Further, the insulated gate bipolar transistor device includes a first nanowire structure and a first gate structure. The first nanowire structure of the insulated gate bipolar transistor structure is connected to the drift region, and the first gate structure of the insulated gate bipolar transistor structure extends along at least a part of the first nanowire structure.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Franz Josef Niedernostheide, Vera van Treek
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8946040
    Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning
  • Patent number: 8872276
    Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Publication number: 20140235026
    Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 21, 2014
    Inventors: ROUYING ZHAN, AMAURY GENDRON, CHAI EAN GILL
  • Patent number: 8697523
    Abstract: A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chun-Chen Yeh
  • Patent number: 8664054
    Abstract: The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
  • Patent number: 8648427
    Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 11, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Patent number: 8609509
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Baars
  • Patent number: 8598678
    Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 3, 2013
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Wensheng Qian, Jun Hu, Donghua Liu
  • Patent number: 8564116
    Abstract: A semiconductor device includes a reinforcement plate having an accommodating hole and a through hole extending from a first surface to a second surface, a semiconductor chip including a chip core and a pad formed on a pad surface of the chip core, the semiconductor chip disposed in the accommodating hole with the pad surface flush with the first surface, the chip core having substantially the same thickness as the reinforcement plate and including a semiconductor substrate, a through-hole electrode disposed in the through hole, resin sealing the semiconductor chip and the reinforcement plate, a interconnection pattern disposed on the first-surface side of the reinforcement plate to connect between the through-hole electrode and the pad, and a interconnection pattern disposed on the second-surface side of the reinforcement plate to be connected to the through-hole electrode, wherein the reinforcement plate is made of the same material as the semiconductor substrate.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: October 22, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 8530979
    Abstract: Provided is a semiconductor package which includes: a semiconductor substrate; a functional element that is disposed on one surface of the semiconductor substrate; a protection substrate that is disposed in an opposite side of that surface of the semiconductor substrate with a predetermined gap from a surface of the semiconductor substrate; and a junction member that is disposed to surround the functional element and bonds the semiconductor substrate and the protection substrate together, wherein the functional element has a shape different from a shape of a plane surrounded by the junction member in that surface of the semiconductor substrate, or is disposed in a region deviated from a central region of the plane surrounded by the junction member in that surface of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujikura Ltd.
    Inventors: Shingo Ogura, Yuki Suto
  • Patent number: 8502347
    Abstract: Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0?x?1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: August 6, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20120248574
    Abstract: A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 4, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 8263469
    Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: September 11, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
  • Patent number: 8247300
    Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Scott G. Balster, Gregory E. Howard, Alfred Hausler
  • Patent number: 8158451
    Abstract: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 17, 2012
    Assignee: IMEC
    Inventors: Ngoc Duy Nguyen, Roger Loo, Matty Caymax
  • Patent number: 8030151
    Abstract: A bipolar transistor (101) has a base (243) formed with an intrinsic base portion (2431), a base contact portion (245C), and a base link portion (243L) that extends between the intrinsic base portion and the base contact portion. An isolating dielectric layer (267-1 or 267-2) is provided above the base link portion. The length of the base link portion is determined, and thereby controlled, with a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, provided on the dielectric layer above the base link portion. The lateral spacing portion is typically provided as part of a layer of non-monocrystalline semiconductor material used in the gate electrode of an insulated-gate field-effect transistor.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: October 4, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jeng-Jiun Yang, Constantin Bulucea
  • Patent number: 8030167
    Abstract: Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Louis D. Lanzerotti, Bradley A. Orner, Jay S. Rascoe, David C. Sheridan, Stephen A. St. Onge
  • Patent number: 7972919
    Abstract: The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Peter B. Gray, Benjamin T. Voegeli
  • Patent number: 7968418
    Abstract: An isolation trench structure includes both a deep trench isolation (DTI) trench and a shallow trench isolation (STI) trench. The DTI trench can be formed by etching a deeper, narrower trench in a substrate and filling the deeper trench with one or more materials (such as an oxide). The STI trench can be formed by etching a shallower, wider trench in the substrate and filling the shallower trench with one or more materials (such as an oxide). The STI trench surrounds a portion of the DTI trench, such as by completely encircling an upper portion of the DTI trench. The DTI and STI trenches are filled during different operations, and the DTI and STI trenches can be filled with the same material(s) or with different material(s).
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Andre P. Labonte, Todd P. Thibeault
  • Publication number: 20110140233
    Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 16, 2011
    Inventors: Wensheng QIAN, Jun Hu, Donghua Liu
  • Patent number: 7863148
    Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: January 4, 2011
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Kenneth M. Ring, Chun Hu, Amol M Kalburge
  • Patent number: 7807579
    Abstract: An oxygen-free hydrogen plasma ashing process particularly useful for low-k dielectric materials based on hydrogenated silicon oxycarbide materials. The main ashing step includes exposing a previously etched dielectric layer to a plasma of hydrogen and optional nitrogen, a larger amount of water vapor, and a yet larger amount of argon or helium. Especially for porous low-k dielectrics, the main ashing plasma additionally contains a hydrocarbon gas such as methane. The main ashing may be preceded by a short surface treatment by a plasma of a hydrogen-containing reducing gas such as hydrogen and optional nitrogen.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: October 5, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Chan-Syun Yang, Changhun Lee
  • Publication number: 20100244143
    Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 30, 2010
    Inventors: Jeng-Jiun Yang, Constantin Bulucea
  • Patent number: 7763518
    Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
  • Publication number: 20100167446
    Abstract: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.
    Type: Application
    Filed: December 28, 2009
    Publication date: July 1, 2010
    Applicant: IMEC
    Inventors: Ngoc Duy Nguyen, Roger Loo, Matty Caymax
  • Patent number: 7719081
    Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: May 18, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
  • Patent number: 7659157
    Abstract: A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Mahender Kumar
  • Publication number: 20100009507
    Abstract: The present invention provides a method of fabricating an integrated circuit comprising at least one bipolar transistor and at least one field effect transistor. The method includes implanting a dopant species of a first type in a semiconductor layer that is doped with a dopant of a second type opposite the first type to form at least one sinker that contacts at least one collector of said at least one bipolar transistor. The method also includes applying heat to cause the dopant species to diffuse outwards to form at least one doped extension of said at least one sinker and forming said at least one field effect transistor in the doped extension.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 14, 2010
    Inventor: Thomas J. Krutsick
  • Publication number: 20090305477
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Application
    Filed: July 30, 2009
    Publication date: December 10, 2009
    Inventors: Thomas Bottner, Stefan Draxl, Thomas Huttner, Martin Seck
  • Patent number: 7601990
    Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: October 13, 2009
    Assignee: Delphi Technologies, Inc.
    Inventor: Jack L. Glenn
  • Publication number: 20090206335
    Abstract: The invention relates to a BiCMOS device comprising a substrate having a first type of conductivity and a number of active regions that are provided therein and are delimited in a lateral direction by flat field-insulating regions. Vertical npn bipolar epitaxial base transistors are disposed in a first partial number of the active regions while vertical pnp bipolar epitaxial base transistors are arranged in a second partial number of the active regions of the BiCMOS device. One transistor type or both transistor types are provided with both a collector region and a collector contact region in one and the same respective active region. In order to improve the high frequency characteristics, an insulation doping region that is configured so as to electrically insulate the collector and the substrate is provided between the collector region and the substrate exclusively in a first transistor type in which the type of conductivity of the substrate corresponds to that of the collector region.
    Type: Application
    Filed: December 1, 2004
    Publication date: August 20, 2009
    Inventors: Bernd Heinemann, Jürgen Drews, Steffen Marschmayer, Holger Rücker
  • Publication number: 20090203183
    Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
    Type: Application
    Filed: April 10, 2009
    Publication date: August 13, 2009
    Inventors: Paul D. Hurwitz, Kenneth M. Ring, Chun Hu, Amol M. Kalburge
  • Publication number: 20090146258
    Abstract: A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 11, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Shaoqiang ZHANG, Purakh Raj VERMA, Sanford CHU
  • Patent number: 7541250
    Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 2, 2009
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • Patent number: 7462547
    Abstract: A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: December 9, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Rama Divakaruni, Marwan Khater, Christopher M. Schnabel, William Tonti
  • Patent number: 7459367
    Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a semiconductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Benjamin T. Voegeli, Steven H. Voldman
  • Patent number: 7442617
    Abstract: A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the third well region to form a base electrode pattern; forming a spacer on a sidewalls of the base electrode pattern; implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and performing a diffusion process to form a base region adjacent to the emitter region.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: October 28, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Woong Je Sung
  • Patent number: 7419611
    Abstract: A method of forming an image. The method includes: a transfer layer on a substrate; forming on the transfer layer, an etch barrier layer; pressing a template having a relief pattern into the etch barrier layer; exposing the etch barrier layer to actinic radiation forming a cured etch barrier layer having thick and thin regions corresponding to the relief pattern; removing the template; removing the thin regions of the cured etch barrier layer; removing regions of the transfer layer not protected by the etch barrier layer; removing regions of the substrate not protected by the transfer layer and any remaining etch barrier layer; and removing remaining transfer layer. The transfer layer may be removed using a solvent, the etch barrier layer may include a release agent and an adhesion layer may be formed between the transfer layer and the etch barrier layer. A reverse tone process is also described.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: September 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Richard Anthony DiPietro, Mark Whitney Hart, Frances Anne Houle, Hiroshi Ito
  • Patent number: 7396732
    Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: July 8, 2008
    Assignee: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventor: Eddy Kunnen
  • Patent number: 7393731
    Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
  • Patent number: 7348250
    Abstract: Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has lower ramp rate.
    Type: Grant
    Filed: January 22, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventor: Gregory G. Freeman
  • Patent number: 7329584
    Abstract: A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the semiconductor substrate; forming an emitter electrode pattern on the third well region, and forming a collector electrode pattern on the second well region; forming spacers at sidewalls of the emitter and collector electrode patterns; performing a diffusion process to form an emitter region of a first conductivity on the third well region and to form a collector region of a first conductivity on the second well region; implanting ions of a second conductivity in the third well region to form a base region; and removing the emitter electrode and collector region patterns.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: February 12, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Woong Je Sung
  • Patent number: 7329583
    Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 12, 2008
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Publication number: 20070298578
    Abstract: An improved bipolar transistor with dual shallow trench isolation for reducing the parasitic component of the base to collector capacitance Ccb and base resistance Rb is provided. The structure includes a semiconductor substrate having at least a pair of neighboring first shallow trench isolation (STI) regions disposed therein. The pair of neighboring first STI regions defines an active area in the substrate. The structure also includes a collector disposed in the in the active area of the semiconductor substrate, a base layer disposed atop a surface of the semiconductor substrate in the active area, and a raised extrinsic base disposed on the base layer. In accordance with the present, the raised extrinsic base has an opening to a portion of the base layer. An emitter is located in the opening and extending on a portion of the patterned raised extrinsic base; the emitter is spaced apart and isolated from the raised extrinsic base.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 27, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marwan H. Khater, Andreas D. Stricker, Bradley A. Orner, Mattias E. Dahlstrom
  • Patent number: 7285469
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: October 23, 2007
    Assignee: Intersil Americas
    Inventor: James Douglas Beasom
  • Patent number: 7282401
    Abstract: A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 7279793
    Abstract: An anti-reflective coating layer for the manufacturing of semiconductor devices is disclosed. In one example, a partial semiconductor device includes a substrate; a bottom anti-reflective coating (BARC) layer over the substrate, and the BARC layer is transformed from being hydrophobic to being hydrophilic during a lithography process; and a photoresist layer over the BARC layer.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: October 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bang-Ching Ho, Jen-Chieh Shih
  • Patent number: RE44140
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: April 9, 2013
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom