Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.

Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.

Abstract: Methods and apparatus according to various aspects of the present invention may operate in conjunction with a resistor formed of a lightly-doped P-type region formed in a portion of a lightly-doped N-type semiconductor well extending on a lightly-doped P-type semiconductor substrate, the well being laterally delimited by a P-type wall extending down to the substrate, the portion of the well being delimited, vertically, by a heavily-doped N-type area at the limit between the well and the substrate and, horizontally, by a heavily-doped N-type wall. A diode may be placed between a terminal of the resistor and the heavily-doped N-type wall, the cathode of the diode being connected to said terminal.

Abstract: A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.

Abstract: A copper conducting wire structure is for use in the thin-film-transistor liquid crystal display (LCD) device. The copper conducting wire structure includes at least a buffer layer and a copper layer. A fabricating method of the copper conducting wire structure includes the following steps. At first, a glass substrate is provided. Next, the buffer layer is formed on the glass substrate. The buffer layer is comprised of a copper nitride. At last, the copper layer is formed on the buffer layer.

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.

Abstract: Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.

Abstract: A method for fabricating a semiconductor device includes forming a device isolation structure in a substrate to define active regions, forming a hard mask pattern to open a region defining an active region pattern and to cover the device isolation structure, forming the active region pattern by selectively recessing the device isolation structure formed in the opened region using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulation layer over the substrate to cover at least the active region pattern, and forming a gate electrode over the gate insulation layer to cover at least the active region pattern.

Abstract: Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.

Abstract: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: The present invention relates to a method for forming an inductor in a semiconductor device. The method comprises the steps of forming a first metal layer on a semiconductor substrate in which a predetermined structure is formed, and then patterning the first metal layer so that a predetermined region of the semiconductor substrate is exposed; forming a first copper layer on the entire resulting surface and then polishing the first copper layer; forming a second metal layer on the resulting surface including the polished first copper layer and then patterning the second metal layer so that predetermined regions of the first metal layer and the first copper layer are exposed; forming a second copper layer on the formed resulting surface; and polishing the resulting surface and stripping the first and second metal layers.

Abstract: A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particular, a dielectric layer is deposited on a semiconductor wafer and has two openings defined by a single masking step, one opening above an emitter region and a second opening above a base-collector junction region. Polysilicon is deposited on the dielectric layer and selectively doped in the areas of the openings. Thus for an NPN transistor for example, the area above the emitter opening is doped N type and the area above the base/field plate opening is doped P type. The doped polysilicon is patterned and etched to leave a polysilicon emitter contact and an integrated polysilicon base contact and field plate within the respective openings.

Abstract: The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.

Abstract: A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

Abstract: A bipolar transistor structure that includes a semiconductor material substrate that has a bottom substrate and base region of a first conductivity type and a buried layer, collector region and sink region of a second conductivity type. The substrate has an extrinsic base region of the first conductivity type and an emitter region of the second conductivity type, both of which extend from the substrate's upper surface into the base region. The bipolar transistor structure also includes a single patterned polysilicon layer with a first polysilicon portion of the first conductivity type in contact with the extrinsic base region and a second polysilicon portion of the second conductivity type in contact with the emitter region. The bipolar transistor structure is compact since contact to the extrinsic base region is made by the first polysilicon portion, which can be formed to a minimum dimension and self-aligned to the extrinsic base region.

Abstract: An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: A method of fabricating a small bipolar transistor emitter in an integrated circuit structure is provided. The integrated circuit structure includes a trench isolation structure formed in a semiconductor substrate to define a substrate active device region. A collector region having a first conductivity type is formed in the substrate active device region beneath a surface thereof. A base region having a second conductivity type opposite the first conductivity type is formed in the substrate active device region above the collector region and extending to the surface of the substrate active device region such that the surface of the active device region forms a surface of the base region. A layer of dielectric material is formed to extend at least partially over the surface-of the base region to define an edge of the layer of dielectric material that is formed over the surface of the base region.

Abstract: A method of fabricating a thin-film transistor on an insulation substrate. A first conductive layer, a gate dielectric layer, a silicon layer and a doped silicon layer are formed on the insulation substrate. These four layers are patterned to form a gate and a gate line. A second conductive layer is formed over the insulation substrate. The second conductive layer and the doped silicon layer are patterned to form a source/drain region, a source/drain conductive layer and a source/drain line on both sides of the gate line. A protection layer is formed over the insulation layer, followed by a patterning step to form openings on the source/drain conductive layer and the source/drain line. A transparent conductive layer is formed on the protection layer and in the openings. After being patterned, a pixel electrode is formed, and a portion of the transparent conductive layer remains to electrically connect the source/drain line and the source/drain conductive layer.

Abstract: The invention discloses a micro-structure capacitor formed by joining the metal layer of a multi-porous micro-structure. A substrate is used as an etching stop layer when producing the capacitor. Therefore, pores with low aspect ratio and uniform size are formed on the surface of the substrate. The efficiency of the subsequent thin film coating process is increased. The porous three-dimensional structure increases the capacitance. Micro-structures are stacked up so the capacitor produced features small size and high capacitance.

Abstract: A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped with emitter metal forming the resistor contacts. The emitter mesas are layered on top of the current channel that is layered atop of a base layer. The voltage variable resistor's control contact is provided by a base contact located on the base layer and separated from the current channel.

Abstract: A method of manufacturing a bipolar transistor having a self-registered base-emitter structure is provided.

Abstract: The present invention relates to a semiconductor apparatus adapted to a ultrahigh density integration process.A semiconductor apparatus of the present invention is characterized by including a high concentration impurity layer with the same type of conductivity as that of a semiconductor wafer provided on the back of the semiconductor wafer, and at least one layer of a low resistance electrode provided on said high concentration impurity layer.

Abstract: Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertically stacked region is fully depleted and thus reduces the parasitic capacitance between the semiconductor device and the well region.

Abstract: A board of calcium silicate crystals, characterized in that the board is composed of a plurality of layers of laminated thin sheets, each of the thin sheets having a thickness of 2 mm or less, each layer comprising secondary particles of calcium silicate crystals, a fibrous material, a coagulant and preferably additionally a polymer adsorbed on the surface of the secondary particles of calcium silicate; wherein each layer contains secondary calcium silicate particles interconnected with one another, and wherein the superposed thin sheets are firmly united with one another into an integral body by the interlayer interconnection of secondary particles of calcium silicate crystals present on the surface of the sheets.