Resistor Patents (Class 438/330)
  • Patent number: 10373837
    Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 6, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Huang Yu, Shih-Yin Hsiao
  • Patent number: 9029180
    Abstract: A method of producing a temperature sensing device is provided. The method includes forming at least one silicon layer and at least one electrode or contact to define a thermistor structure. At least the silicon layer is formed by printing, and at least one of the silicon layer and the electrode or contact is supported by a substrate during printing thereof. Preferably, the electrodes or contacts are formed by printing, using an ink comprising silicon particles having a size in the range 10 nanometers to 100 micrometers, and a liquid vehicle composed of a binder and a suitable solvent. In some embodiments the substrate is an object the temperature of which is to be measured. Instead, the substrate may be a template, may be sacrificial, or may be a flexible or rigid material. Various device geometries are disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 12, 2015
    Assignee: PST Sensors (Proprietary) Limited
    Inventors: David Thomas Britton, Margit Harting
  • Publication number: 20150108422
    Abstract: A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, F, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Fabio Pellizzer, Marcello Mariani, Giorgio Servalli
  • Patent number: 9012289
    Abstract: A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jinhua Liu
  • Patent number: 8872273
    Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: October 28, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • Patent number: 8860139
    Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Sawahata
  • Patent number: 8847320
    Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Hui Chen
  • Publication number: 20140273390
    Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Federica Ottogalli, Luca Laurin
  • Patent number: 8824187
    Abstract: A phase change memory device includes a plurality of word lines, a plurality of lower electrodes, and a plurality of phase change material patterns. The plurality of word lines extend in a first direction and the plurality of word lines are arranged along a second direction perpendicular to the first direction. The lower electrodes are on the word lines and the lower electrodes are arranged in a direction diagonal to the first direction by a first angle. Each of the plurality of phase change material patterns are on a corresponding one of the plurality of lower electrodes.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Park, Ki-Hoon Do, Myung-Jin Kang
  • Patent number: 8815687
    Abstract: Provided are methods of manufacturing semiconductor devices. The method of manufacturing the semiconductor device may include forming a transistor on a substrate, the transistor having first and second doped regions, forming an interlayer dielectric on the substrate, forming a contact hole exposing the first doped region of the transistor, forming a spacer disposed on an inner sidewall of the contact hole, and filling the contact hole provided with the spacer with a conductive layer to form a contact plug.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Sangsup Jeong, Byung-Jin Kang
  • Patent number: 8796102
    Abstract: A method of forming a resistive device includes forming a first wiring layer overlying a first dielectric on top of a substrate, forming a junction material, patterning the first wiring layer and junction material to expose a portion of the first dielectric, forming a second dielectric over the patterned first wiring layer, forming an opening in the second dielectric to expose a portion of the junction material, forming a resistive switching material over the portion of the junction material in the opening, the resistive switching material having an intrinsic semiconductor characteristic, forming a conductive material over the resistive switching material, etching the conductive material and the resistive switching material to expose respective sidewalls of the resistive switching material and the conductive material, and the second dielectric, and forming a second wiring layer over the conductive material in contact with the respective sidewalls and the second dielectric.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 5, 2014
    Assignee: Crossbar, Inc.
    Inventor: Mark Harold Clark
  • Patent number: 8792265
    Abstract: A phase change material for use in a phase change memory device comprises germanium-antimony-tellurium-indium, wherein the phase change material comprises in total more than 30 at % antimony, preferably 5-16 at % germanium, 30-60 at % antimony, 25-51 at % tellurium, and 2-33% at % indium.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Michael Antoine Armand In 'T Zandt, Robertus Andrianus Maria Wolters, Hendrikus Jan Wondergem
  • Patent number: 8785288
    Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Sumeet C. Pandey
  • Patent number: 8772121
    Abstract: A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Man Hwang, Jun-Soo Bae, Sung-Un Kwon, Kwang-Ho Park
  • Patent number: 8748988
    Abstract: A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yuichiro Kitajima
  • Patent number: 8742507
    Abstract: A variable resistive element configured to reduce a forming voltage while reducing a variation in forming voltage among elements, a method for producing it, and a highly integrated nonvolatile semiconductor memory device provided with the variable resistive element are provided. The variable resistive element includes a resistance change layer (first metal oxide film) and a control layer (second metal oxide film) having contact with a first electrode sandwiched between the first electrode and a second electrode. The control layer includes a metal oxide film having a low work function (4.5 eV or less) and capable of extracting oxygen from the resistance change layer. The first electrode includes a metal having a low work function similar to the above metal, and a material having oxide formation free energy higher than that of an element included in the control layer, to prevent oxygen from being thermally diffused from the control layer.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: June 3, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yukio Tamai
  • Publication number: 20140106532
    Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 8696918
    Abstract: Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass transition temperature (Tg,O) and a degradation temperature (Td). A temperature window may be defined to correspond to temperatures (T) within the range of Tg,O?T?Td. While the block copolymer is in the upper half of the temperature window, solvent may be dispersed into the block copolymer to a process volume fraction that induces self-assembly of the block copolymer into a pattern. A defect specification may be defined, and the process volume fraction of solvent may be at level that achieves self-assembly within the defect specification. In some embodiments, the solvent may be removed from within the block copolymer while maintaining the defect specification.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dan Millward, Scott Sills
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8652927
    Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 18, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sandra Malhotra, Hanhong Chen, Wim Y. Deweerd, Edward L. Haywood, Hiroyuki Ode, Gerald Richardson
  • Patent number: 8642428
    Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: February 4, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 8643090
    Abstract: In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
  • Patent number: 8637912
    Abstract: A semiconductor device includes a substrate having a primary side. A first pillar extends vertically with respect to the primary side of the substrate, the first pillar defining first and second conductive regions and a channel region that is provided between the first and second conductive regions. A first gate is provided over the channel region of the first pillar. A buried word line extends along a first direction below the first pillar, the buried word line configured to provide a first control signal to the first gate. A first interposer is coupled with the buried word line and the first gate to enable the first control signal to be applied to the first gate via the buried word line.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jinchul Park
  • Patent number: 8598009
    Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 3, 2013
    Assignees: International Business Machines Corporation, Globalfoundries, Inc.
    Inventors: Brian J. Greene, William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal, Johan W. Weijtmans
  • Patent number: 8587224
    Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 19, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun-Tak Kim, Bongjun Kim
  • Patent number: 8563336
    Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, John C. Malinowski, Anthony K. Stamper
  • Publication number: 20130242649
    Abstract: Embodiments disclosed herein may relate to forming an interface between a selector transistor and a phase change material storage cell in a memory device.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Agostino Pirovano
  • Patent number: 8502478
    Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: August 6, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Tak Kim, Bong Jun Kim
  • Patent number: 8486796
    Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: David L. Harmon, Joseph M. Lukaitis, Stewart E. Rauch, III, Robert R. Robison, Dustin K. Slisher, Jeffrey H. Sloan, Timothy D. Sullivan, Kimball M. Watson
  • Publication number: 20130157433
    Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe.
    Type: Application
    Filed: February 19, 2013
    Publication date: June 20, 2013
    Inventors: Rouying Zhan, Amaury Gendron, Chai Ean Gill
  • Patent number: 8461010
    Abstract: In conventional processes, a recombination rate of minority carrier accumulated between a diffusion layer of an anode and a diffusion layer of a cathode cannot be enhanced. An interlayer insulating film 20 is formed on a semiconductor substrate 10. An opening 22 (first opening), an opening 24 (second opening) and an opening 26 are formed in the interlayer insulating film 20. The opening 22 and the opening 26 are formed above respective the p-type diffusion layer 16 and the n-type diffusion layer 18. The opening 24 is formed above the gap region that is a region between the p-type diffusion layer 16 and the n-type diffusion layer 18. A contact plug 32, a contact plug 34 and a contact plug 36 are embedded in the opening 22, the opening 24 and the opening 26 respectively. Both regions of the semiconductor substrate 10 located under the opening 22 among and located under the opening 24 are doped with an impurity.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masaharu Sato
  • Patent number: 8299579
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 30, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Publication number: 20120145984
    Abstract: A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: Peter Rabkin, Andrei Mihnea
  • Patent number: 8178948
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: May 15, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jae-Young Park, Jong-Kyu Song, San-Hong Kim
  • Patent number: 8163637
    Abstract: First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 24, 2012
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Masaki Konishi, Hirokazu Fujiwara, Takeshi Endo, Takeo Yamamoto, Takashi Katsuno, Yukihiko Watanabe
  • Publication number: 20120070949
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
    Type: Application
    Filed: July 12, 2011
    Publication date: March 22, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tea-Kwang Yu, Byung-Sup Shim, Yong-Kyu Lee, Bo-Young Seo, Yong-Tae Kim
  • Patent number: 8120122
    Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 21, 2012
    Inventor: Scott Jong Ho Limb
  • Patent number: 8110472
    Abstract: A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: February 7, 2012
    Assignee: Alpha and Omega Semiconductor Ltd
    Inventors: François Hébert, Anup Bhalla
  • Publication number: 20110181323
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 28, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 7985616
    Abstract: Embodiments of the present invention provide a method that includes providing a wafer including multiple cells, each cell including at least one emitter, and performing a lithographic operation on the wafer. The lithographic operation comprises forming heater trenches adjacent the emitters, each heater trench having a width that extends over at least respective portions of two cells. Other embodiments are also described.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: July 26, 2011
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Chien-Chuan Wei, Runzi Chang, Winston Lee, Peter Lee
  • Patent number: 7952131
    Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 31, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Manju Sarkar
  • Patent number: 7911032
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: March 22, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Publication number: 20110043141
    Abstract: Provided are a MIT device self-heating preventive-circuit that can solve a self-heating problem of a MIT device and a method of manufacturing a MIT device self-heating preventive-circuit integrated device. The MIT device self-heating preventive-circuit includes a MIT device that generates an abrupt MIT at a temperature equal to or greater than a critical temperature and is connected to a current driving device to control the flow of current in the current driving device, a transistor that is connected to the MIT device to control the self-heating of the MIT device after generating the MIT in the MIT device, and a resistor connected to the MIT device and the transistor.
    Type: Application
    Filed: February 23, 2009
    Publication date: February 24, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Tak Kim, Bong-Jun Kim, Sun-Jin Yun, Dae-Yong Kim
  • Patent number: 7870664
    Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: January 18, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Vova R. Markovich
  • Publication number: 20100321990
    Abstract: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 23, 2010
    Applicant: QIMONDA NORTH AMERICA CORP.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7741187
    Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: June 22, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Manju Sarkar
  • Patent number: 7678992
    Abstract: A thin film photoelectric converter, especially an integrated thin film photoelectric converter having improved photoelectric conversion efficiency is provided by controlling an open-circuit voltage and a fill factor so as not be small in a thin film photoelectric converter including a crystalline silicon photoelectric conversion unit. The thin film photoelectric converter by the present invention has at least a transparent electrode film, a crystalline silicon photoelectric conversion unit, and a back electrode film formed sequentially on one principal surface of a transparent substrate, and the converter has a whitish discoloring area on a part of a surface of the converter after formation of the crystalline silicon photoelectric conversion unit. A percentage of dimensions of the whitish discoloring area preferably is not more than 5% of a dimension of the photoelectric conversion area.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: March 16, 2010
    Assignee: Kaneka Corporation
    Inventors: Takashi Suezaki, Masashi Yoshimi, Toshiaki Sasaki, Yuko Tawada, Kenji Yamamoto
  • Patent number: 7675114
    Abstract: In order to obtain an increased avalanche strength, a trench transistor is proposed in which the breakdown location is defined in a trench bottom region below body contact zones. This is done by means of a modulation of the dopant concentration in a drift zone and an insulation layer thickness modulation in the bottom region of the trenches.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 9, 2010
    Assignee: Infineon Technologies AG
    Inventor: Markus Zundel
  • Publication number: 20100044834
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 25, 2010
    Inventors: Jae-Young Park, Jong-Kyu Song, San-Hong Kim
  • Publication number: 20090253239
    Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 8, 2009
    Applicant: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Kimball M. Watson