Making Plural Bipolar Transistors Of Differing Electrical Characteristics Patents (Class 438/340)
  • Patent number: 9252293
    Abstract: Diodes and methods of manufacturing diodes are disclosed. The diodes may include a cathode assembly and an anode assembly having an anode electrode, a gate electrode layer under the anode electrode, a gate oxide layer under the gate electrode layer, at least one P? body region under the gate oxide layer, and at least one trench that extends through the gate electrode layer, the gate oxide layer, and the at least one P? body region to the cathode assembly. The at least one trench may include a lower portion having (1) a bottom and a plurality of sidewalls defining a bottom volume and having an insulating layer and (2) a conductive material that is disposed within the bottom volume and that is in electrical communication with the anode electrode. The anode electrode may contact extend through the at least one trench to the conductive material.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: February 2, 2016
    Inventor: Alexei Ankoudinov
  • Patent number: 8932931
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • Patent number: 8921190
    Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Alvin J. Joseph, Stephen E. Luce, John J. Pekarik, Yun Shi
  • Publication number: 20140231963
    Abstract: A unidirectional transient voltage suppressor (TVS) device includes first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Applicant: Alpha & Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8748936
    Abstract: A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: June 10, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Yu Wang, Chia-Ling Lu, Yan-Yu Chen, Yu-Lien Liu, Tao-Cheng Lu
  • Patent number: 8710627
    Abstract: An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 29, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 8680621
    Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: March 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrice Besse, Jean Philippe Laine
  • Patent number: 8603885
    Abstract: Bipolar transistors with tailored response curves, as well as fabrication methods for bipolar transistors and design structures for BiCMOS integrated circuits. The bipolar transistor includes a first section of a collector region implanted with a first dopant concentration and a second section of the collector region implanted with a second dopant concentration that is higher than the first dopant concentration. A first emitter is formed in vertical alignment with the first section of the collector region. A second emitter is formed in vertical alignment with the second section of the collector region.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ramana M. Malladi, Kim M. Newton
  • Patent number: 8330219
    Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: December 11, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Tomoyuki Furuhata, Hideyuki Akanuma, Hiroaki Nitta
  • Patent number: 8263470
    Abstract: There is provided a method of fabricating a semiconductor including: forming a first and a second bipolar transistors on a semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region for establishing an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, a contact hole for establishing contact with each of those regions; and embedding a conductive member in the contact holes.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 11, 2012
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Katsuhiro Yamaide
  • Patent number: 8247300
    Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Scott G. Balster, Gregory E. Howard, Alfred Hausler
  • Patent number: 8124468
    Abstract: An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 28, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna
  • Publication number: 20120028432
    Abstract: A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicant: Analog Devices, Inc.
    Inventors: Bernard Patrick Stenson, Andrew David Bain, Derek Frederick Bowers, Paul Malachy Daly, Anne Maria Deignan, Michael Thomas Dunbar, Patrick Martin McGuiness, William Allan Lane
  • Patent number: 8076211
    Abstract: A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Augusto Benvenuti, Fabio Pellizzer, Giorgio Servalli
  • Patent number: 8026146
    Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 27, 2011
    Assignee: NXP B.V.
    Inventors: Johannes J. T. M. Donkers, Sebastien Nuttinck, Guillaume L. R. Boccardi, Francois Neuilly
  • Patent number: 7998779
    Abstract: A solid-state imaging device includes: a solid-state imaging element having a light-receiving area; a transparent member disposed so as to oppose the light-receiving area; a supporting member configured to support the transparent member; a first mark disposed at either an upper surface of the transparent member or an upper surface of the supporting member; and a second mark disposed at an outer side of the light-receiving area, at an upper surface of the solid-state imaging element.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyuki Watanabe, Takao Ohno, Susumu Moriya, Izumi Kobayashi
  • Patent number: 7989921
    Abstract: An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 2, 2011
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Publication number: 20110176243
    Abstract: A stacked electrostatic discharge (ESD) protection clamp (99, 100-104) for protecting associated devices or circuits (24) comprises two or more series coupled (stacked) bipolar transistors (70, 700) whose individual trigger voltages Vt1 depend on their base-collector spacing D. A first (70-1, 700-1) of the transistors (70, 700) has a spacing DZ1 chosen within a D range Z1 whose slope (?Vt1/?D) has a first value (?Vt1/?D)Z1, and a second (70-2, 700-2) of the transistors (70, 700) has a spacing value D(Z2 or Z3) chosen within a D range Z2 or Z3 whose slope (?Vt1/?D) has a second value (?Vt1/?D)(Z2 or Z3) less than the first value (?Vt1/?D)Z1. The sensitivity of the ESD stack trigger voltage Vt1STACK to base-collector spacing variations ?D during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vt1STACK values can be obtained that are less sensitive to unavoidable manufacturing spacing variations ?D.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 21, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rouying Zhan, Amaury Gendron, Chai Ean Gill
  • Patent number: 7968417
    Abstract: According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 28, 2011
    Assignee: Newport Fab, LLC
    Inventor: Edward Preisler
  • Publication number: 20110151638
    Abstract: There is provided a method of fabricating a semiconductor including: forming a first and a second bipolar transistors on a semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region for establishing an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, a contact hole for establishing contact with each of those regions; and embedding a conductive member in the contact holes.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 23, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Katsuhiro Yamaide
  • Patent number: 7811894
    Abstract: An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: October 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Nam Joo Kim
  • Patent number: 7800143
    Abstract: A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has a collector, a base and an emitter. The emitter of the bipolar transistor is formed to serve as the source region for the MOS transistor and the base of the bipolar transistor is formed to serve as a capacitive charge storage region for the memory cell.
    Type: Grant
    Filed: December 24, 2006
    Date of Patent: September 21, 2010
    Assignee: GlobalFoundries Inc.
    Inventor: Hyun-Jin Cho
  • Patent number: 7777255
    Abstract: A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: August 17, 2010
    Assignee: IHP GmbH—Innovations for High Performance Microelectronics / Leibniz-Instut für innovative Mikroelektronik
    Inventors: Holger Rücker, Bernd Heinemann
  • Patent number: 7767469
    Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Hiroaki Yoda
  • Patent number: 7741223
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first recess having a micro trench, etching the substrate disposed under the first recess to form a second recess having a profile substantially vertical and a width greater than a portion of the first recess where no micro trench is formed, etching the substrate disposed under the second recess to form a third recess having a profile substantially spherical, and forming a gate pattern over a resultant recess including the first to third recesses.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 22, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Sik Park, Ky-Hyun Han
  • Patent number: 7495312
    Abstract: A method for producing vertical bipolar transistors having different voltage breakdown and high-frequency performance characteristics on a single die comprises forming, for each of the vertical bipolar transistors, a buried collector region, and base and emitter regions above the buried collector region. The lateral extensions and locations of the base and emitter regions and of the buried collector region are, for each of the vertical bipolar transistors, selected to create an overlap between the base and emitter regions, and the buried collector region, as seen from above, wherein at least some of the overlaps are selected to be different.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: February 24, 2009
    Assignee: Infineon Technologies AG
    Inventors: Patrick Algotsson, Hans Norström, Karin Andersson
  • Patent number: 7459368
    Abstract: Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconductor material, which is formed as a single crystal at least in the collector semiconductor region above the opening, is applied over the etch stop layer and over the opening. Before etching of the semiconductor material, a masking layer is applied above the collector semiconductor region to the semiconductor material, which protects the collector semiconductor region from the etching. Afterwards the semiconductor material is etched to the depth of the etch stop layer, the etch stop layer acting as an etch stop such that reaching an interface between the semiconductor material and the etch stop layer is detected during the etching and the etching is stopped depending on the detection.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: December 2, 2008
    Assignee: Atmel Germany GmbH
    Inventor: Peter Brandl
  • Patent number: 7456070
    Abstract: A method of fabricating a transistor that includes a doped buried region within a semiconductor body. The doped buried region includes a portion having a first thickness and a second thickness, the first thickness being less than the second thickness. In one embodiment, the first thickness is about half the second thickness. The transistor also includes a collector region over the buried region, a base region within the collector region and an emitter region within the base region.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: November 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Frank S. Johnson
  • Patent number: 7449389
    Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: November 11, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Meister, Herbert Schäfer, Josef Böck, Rudolf Lachner
  • Publication number: 20080102593
    Abstract: A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 1, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Meister, Herbert Schafer, Josef Bock, Rudolf Lachner
  • Patent number: 7327012
    Abstract: A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a region of a substrate of a second conductivity type through a first aperture in a first mask to form a collector region. Impurities of the second conductivity type are introduced in the collector through the first aperture in the first mask to form the base region. Impurities of the first conductivity type are then introduced into the base region through a second aperture in a second mask to form the emitter region. The minimum dimension of the first aperture of the first mask is selected for a desired collector to base breakdown voltage. This allows tuning of the breakdown voltage.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: February 5, 2008
    Inventor: James Douglas Beasom
  • Patent number: 7285469
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: October 23, 2007
    Assignee: Intersil Americas
    Inventor: James Douglas Beasom
  • Patent number: 7271046
    Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: September 18, 2007
    Assignee: Sony Corporation
    Inventor: Chihiro Arai
  • Patent number: 7217628
    Abstract: A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.
    Type: Grant
    Filed: January 17, 2005
    Date of Patent: May 15, 2007
    Assignee: International Business Machines Corporation
    Inventors: David C. Sheridan, Peter B. Gray, Jeffrey B. Johnson, Qizhi Liu
  • Patent number: 7192838
    Abstract: Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: March 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Philipp Steinmann, Scott Balster, Badih El-Kareh, Thomas Scharnagl
  • Patent number: 7144789
    Abstract: In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: December 5, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Badih El-Kareh, Scott Balster, Philipp Steinmann, Thomas Scharnagl, Manfred Schiekofer, Carl Willis
  • Patent number: 7109567
    Abstract: The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: September 19, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond Josephus Engelbart Hueting, Jan Willem Slotboom, Leon Cornelis Maria Van Den Oever
  • Patent number: 7071536
    Abstract: A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: July 4, 2006
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Saichirou Kaneko, Masakatsu Hoshi, Yoshinori Murakami, Tetsuya Hayashi, Hideaki Tanaka
  • Patent number: 7060583
    Abstract: In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an insulating material will now be applied, wherein the at least one layer is patterned such that at least one section of the basis region is exposed. Next, a layer of a polycrystalline semiconductor material of the first conductivity type, which is heavily doped with doping atoms, will be generated such that the exposed section is essentially covered. Now, a second layer of a highly conductive material on the layer of the polycrystalline semiconductor material will be generated in order to form an emitter double layer with the same.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: June 13, 2006
    Assignee: Infineon Technologies AG
    Inventors: Jakob Kriz, Martin Seck, Armin Tilke
  • Patent number: 7015085
    Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green
  • Patent number: 7001806
    Abstract: A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor area of a second doping type on the second semiconductor layer, so that a pn junction is formed between the semiconductor area and the second semiconductor layer, and a recess present below the semiconductor area in the buried first semiconductor layer, which comprises a semiconductor material of the first doping type, which can be less doped than the buried first semiconductor layer and has a larger distance to the semiconductor area of the second doping type on the second semiconductor layer, such that the breakdown voltage across the pn junction is higher than if the recess were not provided.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: February 21, 2006
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Wolfgang Klein
  • Patent number: 6992338
    Abstract: According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate and the transistor gate. The conformal layer may, for example, be silicon nitride. An opening is then etched in the conformal layer. Next, a base layer is deposited on the conformal layer and in the opening. The base layer may, for example, be silicon-germanium. According to this exemplary embodiment, an emitter may be formed on the base layer in the opening. Next, the base layer is removed from the conformal layer. The conformal layer is then etched back to form a spacer adjacent to the transistor gate. In one embodiment, a structure is fabricated according to the above described exemplary method.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: January 31, 2006
    Assignee: Newport Fab, LLC
    Inventors: Kevin Q. Yin, Amol Kalburge, Klaus F. Schuegraf
  • Patent number: 6984567
    Abstract: A nonvolatile semiconductor memory device having a memory cell comprising source/drain diffusion layer in p-well formed to a silicon substrate, a floating gate as a first gate, a control gate (word line) as a second gate, and a third gate, in which the floating gate and the p-well are isolated by a tunnel insulator film, the third gate and the p-well are isolated by a gate insulator film, the floating gate and the third gate are isolated by an insulator film, the floating gate and the word line (control gate) are isolated by a insulator film (ONO film), and the second gate film and the word line (control gate) are isolated by a silicon oxide film, respectively, wherein the thickness of the tunnel insulator film is made larger than the thickness of the gate insulator film. Accordingly, the reliability and access time of the device is improved.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: January 10, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Takashi Kobayashi
  • Patent number: 6977426
    Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N+-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 20, 2005
    Assignee: Sony Corporation
    Inventors: Takayuki Gomi, Hiroaki Ammo
  • Patent number: 6940149
    Abstract: Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Rama Divakaruni, Gregory Freeman, Marwan Khater, William Tonti
  • Patent number: 6930008
    Abstract: A method of fabricating a complementary bipolar junction transistor includes forming a polycrystalline silicon layer on an NPN bipolar junction transistor region and a PNP bipolar junction transistor region, respectively implanting an N-type impurity and a P-type impurity into the polycrystalline silicon layer, and then diffusing to respectively form an N-type emitter region and a P-type emitter region within a P-type base region and an N-type base region. By patterning the polycrystalline silicon layer, an N-type emitter electrode and a P-type emitter electrode are simultaneously formed. The polycrystalline silicon layer is used for simultaneously forming the N-type emitter electrode of the NPN bipolar junction transistor and the P-type emitter electrode of the PNP bipolar junction transistor by a single depositing and etching process.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyun Nam, Sung-ryoul Bae
  • Patent number: 6888221
    Abstract: A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Alvin J. Joseph, Qizhi Liu, Devendra K. Sadana
  • Patent number: 6838348
    Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: January 4, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Gregory E. Howard, Angelo Pinto, Phillipp Steinmann, Scott G. Balster
  • Patent number: RE44140
    Abstract: In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×1012 cm?2.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: April 9, 2013
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom