Abstract: The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant.

Abstract: A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semiconductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with a gate insulating layer interposed therebetween; a first impurity region formed of the first conductivity type in the semiconductor substrate below the gate electrode and having a higher concentration of first conductivity type ions than the semiconductor substrate; and a second impurity region formed of a second conductivity type in the photodiode region of the semiconductor substrate.

Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.

Abstract: A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an N-Pocket mask, forming P-LDD regions on the semiconductor chip using a P-LDD mask, and forming P-Pocket regions on the semiconductor chip using a P-Pocket mask.

Abstract: A method of performing salicide processes on a MOS transistor, wherein the MOS transistor comprises a gate structure and a source/drain region, the method comprising: performing a selective growth process to form a silicon layer on the top of the gate and the source/drain region; performing an ion implantation process to form a retarded interface layer between the silicon layer and the gate and source/drain region; forming a metal layer on the silicon layer; and reacting the metal layer with the silicon layer for forming a silicide layer.

Abstract: A method for fabricating a photodiode of a CMOS image sensor is disclosed, to improve a charge accumulation capacity in the photodiode, which includes the steps of defining a semiconductor substrate as an active area and a field area by forming an STI layer; firstly implanting impurity ions for formation of the photodiode to the semiconductor substrate of the active area; secondarily implanting impurity ions for formation of the photodiode to the semiconductor substrate being adjacent to the STI layer; and forming a photodiode ion-implantation diffusion layer by diffusing the implanted impurity ions with a thermal process.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.

Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: A process uses pressure changes and a pressure compensation factor to estimate the rate at which neutral atoms are implanted. While implanting a first wafer using a first pressure compensation factor, the rate at which ions are implanted is determined. The first wafer is moved radially with respect to an ion beam while implanting ions into the first wafer so as to achieve a uniform total dose based on the rate at which ions are implanted and the estimated rate at which neutral atoms are implanted. The pressure is determined while implanting the first wafer, determining the pressure. A second pressure compensation factor is selected, that would have achieved a uniform rate of implanted ions plus implanted neutral atoms across a surface of the first wafer. The second pressure compensation factor is different from the first pressure compensation factor. The second pressure compensation factor is used to implant a second wafer. The second wafer is tested by forming a sheet resistance contour map.

Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

Abstract: According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semiconductor substrate, etching a portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and after forming the emitter polysilicon layer, annealing the semiconductor substrate.

Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.

Abstract: A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced width is achieved without the need of using advanced lithographic tools and/or advanced photomasks.

Abstract: Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.

Abstract: Methods and apparatus are provided for plasma doping and ion implantation in an integrated processing system. The apparatus includes a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a plasma doping module including a plasma doping chamber that is accessible from the process chamber, and a wafer positioner. The positioner positions a semiconductor wafer in the path of the ion beam in a beamline implant mode and positions the semiconductor wafer in the plasma doping chamber in a plasma doping mode.

Abstract: During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first region of the two adjacent regions includes a doping with a lower target concentration than a second region. The predetermined area of a semiconductor blank is doped with a dopant until a concentration of the dopant is obtained that is at least as high as the target concentration of the second region. A protective layer is applied to the second region, and the dopant is out-diffused from the first region until a concentration of dopant is obtained that corresponds to the target concentration of the first region.

Abstract: A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price of high beta and high base resistance, separate boron and indium doping profiles are combined in the base. Thus, a transistor, which preserves most of the properties of pure boron-base transistor, is obtained, but with some parameters improved due to the added indium profile. This “double-profile” or “indium-enhanced” transistor exhibits improved beta-Early voltage product, reduced collector-base capacitance swing and lower temperature dependence of beta, but preserves the advantageous properties of a pure boron-base transistor.

Abstract: An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.

Abstract: A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 130) with the first region (11) and separates the first region (11) from the first major surface (10a) while the third region (14) separates the first region (11) from the second major surface (10b). A plurality of semi-insulating or resistive paths (21) are dispersed within the first region (1′) such that each path extends through the first region from the second to the third region. In use of the device when a reverse biasing voltage is applied across the rectifying junction (13 or 130) an electrical potential distribution is generated along the resistive paths (21) which causes a depletion region in the first region (11) to extend through the first region (11) to the third region (14) to increase the reverse breakdown voltage of the device.

Abstract: According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semiconductor substrate, etching a portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and after forming the emitter polysilicon layer, annealing the semiconductor substrate.

Abstract: According to one embodiment of the invention, a method for manufacturing a bipolar junction transistor includes implanting a first base dopant in a semiconductor substrate, forming an epitaxial layer outwardly from the semiconductor substrate, and forming a dielectric layer outwardly from the epitaxial layer. The method also includes etching a first portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and implanting an emitter dopant in the emitter polysilicon layer. The method further includes etching a portion of the emitter polysilicon layer and a second portion of the dielectric layer to form an emitter polysilicon region having sidewalls, forming nitride regions on the sidewalls, and implanting a second base dopant in the semiconductor substrate. After implanting the second base dopant, an annealing process is performed for the semiconductor substrate to form an emitter and a base.

Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: The collector of a vertical bipolar transistor is selectively doped by a first implantation of dopants before the epitaxy of the base, and is selectivly doped by a second implantation of dopants through the epitaxial base. Two implanted zones with different widths are obtained. The base of the vertical bipolar transistor is thinned and the collector resistance is optimized.

Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (34) formed in the epitaxial layer (14). A doped region (13) is formed in the semiconductor substrate (11) to reduce the drift resistance of the semiconductor device (10). The drain region (34) is formed from a plurality of doped regions (30-33) that can be formed with high energy implants.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functioning as spacers (11,12) at the sidewalls of this gate electrode. Dopants for a collector region (4) and an emitter region (6) are introduced using lacquer masks (13,14). After the removal of the TEOS layer (10), the base implantation ensues in the region of the spacer (11) along an edge of the gate electrode.