Multiple Ion Implantation Steps Patents (Class 438/373)
  • Patent number: 10283627
    Abstract: An object is to provide a highly reliable semiconductor device including a thin film transistor having stable electric characteristics. In addition, another object is to manufacture a highly reliable semiconductor device at low cost with high productivity. In a method for manufacturing a semiconductor device including a thin film transistor including an oxide semiconductor layer as a channel formation region, the oxide semiconductor layer is heated under a nitrogen atmosphere to lower its resistance, thereby forming a low-resistance oxide semiconductor layer. Further, resistance of a region of the low-resistance oxide semiconductor layer, which is overlapped with a gate electrode layer, is selectively increased, thereby forming a high-resistance oxide semiconductor layer. Resistance of the oxide semiconductor layer is increased by forming a silicon oxide film in contact with the oxide semiconductor layer by a sputtering method.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 7, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hiroki Ohara, Junichiro Sakata
  • Patent number: 10115720
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: October 30, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 9362278
    Abstract: A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Huang, Da-Wen Lin
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Patent number: 8921197
    Abstract: Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells including a read pull down transistor and a read pass gate transistor. First conductivity-determining impurity ions are implanted to establish a first threshold voltage in each of the read pull down transistors; and second conductivity-determining impurity ions are implanted to establish a second threshold voltage different than the first threshold voltage in each of the read pass gate transistors.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Ralf van Bentum, Torsten Klick
  • Patent number: 8900954
    Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8900962
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Yamashita, Etsuo Hamada, Hideki Nozaki, Hironobu Shibata
  • Patent number: 8853026
    Abstract: Semiconductor devices and methods of fabricating the same are provided. An insulating film can be disposed on a semiconductor substrate, and insulating film patterns can be formed opening a plurality of areas with predetermined widths by patterning the insulating film. A plurality of ion implantation areas having a first conductivity type can be formed by implanting impurities into the plurality of open areas, and an oxide film pattern can be formed on each of the ion implantation areas. The insulating film patterns can be removed, and ion implantation areas having a second conductivity type can be formed by implanting impurities using the oxide film pattern as a mask. The semiconductor substrate can be annealed at a high temperature to form deep wells.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Kyung Wook Kwon
  • Patent number: 8796123
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda
  • Patent number: 8765583
    Abstract: An improved method of tilting a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. The mask and substrate are tilted at a first angle relative to the incoming ion beam. After the substrate is exposed to the ion beam, the mask and substrate are tilted at a second angle relative to the ion beam and a subsequent implant step is performed. Through the selection of the aperture size and shape, the cross-section of the mask, the distance between the mask and the substrate and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: July 1, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Benjamin Riordon, Nicholas Bateman, Atul Gupta
  • Patent number: 8759188
    Abstract: A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 24, 2014
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Alfonso Patti, Antonino Schillaci, Bartolome Marrone, Gianleonardo Grasso, Rajesh Kumar
  • Patent number: 8753948
    Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: June 17, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiaowei Ren, Robert P. Davidson, Mark A. Detar
  • Patent number: 8673753
    Abstract: In a multi-energy ion implantation process, an ion implanting system having an ion source, an extraction assembly, and an electrode assembly is used to implant ions into a target. An ion beam having a first energy may be generated using the ion source and the extraction assembly. A first voltage may be applied across the electrode assembly. The ion beam may enter the electrode assembly at the first energy, exit the electrode assembly at a second energy, and implant ions into the target at the second energy. A second voltage may be applied across the electrode assembly. The ion beam may enter the electrode assembly at the first energy, exit the electrode assembly at a third energy, and implants ions into the target at the third energy. The third energy may be different from the second energy.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 18, 2014
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventor: Zhimin Wan
  • Patent number: 8598007
    Abstract: One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: December 3, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8580646
    Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack A. Mandelman, William R. Tonti
  • Patent number: 8513083
    Abstract: Disclosed herein are various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. In one example, the method includes performing a first angled ion implantation process to form a first doped region in a bulk layer of an SOI substrate for one of the anode or the diode and, after performing the first angled ion implantation process, performing a second angled ion implantation process to form a second doped region in the bulk layer of the SOI substrate for the other of the anode and the diode, wherein said first and second angled ion implantation process are performed through the same masking layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 20, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Thilo Scheiper
  • Patent number: 8487280
    Abstract: A first species is implanted into an entire surface of a workpiece and helium is implanted into this entire surface with a non-uniform dose. The first species may be, for example, hydrogen, helium, or nitrogen. The helium has a higher dose at a portion of a periphery of the workpiece. When the workpiece is split, this split is initiated at the periphery with the higher dose. The non-uniform dose may be formed by altering a scan speed of the workpiece or an ion beam current of the helium. In one instance, the non-uniform dose of the helium is larger than a uniform dose of the hydrogen.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Gary E. Dickerson, Julian G. Blake
  • Patent number: 8409975
    Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 2, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Liujiang Yu
  • Patent number: 8298889
    Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
  • Patent number: 8198659
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device may include forming a gate electrode over a semiconductor substrate, a second conductive type ion implantation region at opposite sides of a gate electrode, a second conductive type ion implantation region as a first conductive type second ion implantation region by implanting a first conductive type impurity over opposite sides of said gate electrode, and/or forming a first conductive type first ion implantation region that substantially surrounds a first conductive type second ion implantation region. A method of manufacturing a semiconductor device may form an N type MOSFET and/or a P type MOSFET using a single photolithography process for each N+ source/drain photolithography process and/or P+ source/drain photolithography process.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: June 12, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kyung-Wook Kwon
  • Patent number: 8174074
    Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chung-Hsun Lin, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8114751
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: February 14, 2012
    Assignee: Icemos Technology Ltd.
    Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
  • Patent number: 8067301
    Abstract: A reliable image sensor and a method for forming the same are provided. The image sensor includes a photo-detective device. At least one transistor is electrically connected to the photo-detective device for outputting charges stored in the photo-detective device. A transistor directly connected to the photo-detective device includes a gate electrode pattern and an ion-implantation interrupting pattern arranged on the gate electrode pattern. Since the ion-implantation interrupting pattern is located on an upper portion of the gate electrode pattern of the transistor in the vicinity of the photo-detective device, a threshold voltage of the gate electrode pattern of the transistor in the vicinity of the photo-detective device is adjusted to a desired value.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duk-Min Yi, Sung-Keun Won, Jun-Yeoul You
  • Patent number: 8035196
    Abstract: The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 11, 2011
    Assignee: Zarlink Semiconductor (US) Inc.
    Inventors: Thomas J. Krutsick, Christopher J. Speyer
  • Patent number: 8012843
    Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: September 6, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
  • Patent number: 7888226
    Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: February 15, 2011
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Tae-hun Kwon, Cheol-joong Kim, Young-sub Jeong
  • Patent number: 7825457
    Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 2, 2010
    Assignee: Spansion LLC
    Inventor: Masatomi Okanishi
  • Patent number: 7732292
    Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Marwan H. Khater, Francois Pagette
  • Patent number: 7674658
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 9, 2010
    Assignee: Au Optronics Corporation
    Inventors: Chen-Yueh Li, Yi-Wei Chen, Ming-Yan Chen
  • Patent number: 7655526
    Abstract: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of forming a gate electrode on a semiconductor substrate, forming a drift area in the semiconductor substrate by implanting a dopant using the gate electrode as a mask, forming a sidewall spacer at sides of the gate electrode, and forming a source/drain area in the semiconductor substrate by implanting a dopant using the gate electrode and the sidewall spacer as a mask.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: February 2, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Choul Joo Ko
  • Patent number: 7645652
    Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semiconductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with a gate insulating layer interposed therebetween; a first impurity region formed of the first conductivity type in the semiconductor substrate below the gate electrode and having a higher concentration of first conductivity type ions than the semiconductor substrate; and a second impurity region formed of a second conductivity type in the photodiode region of the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: January 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Lim Keun Hyuk
  • Patent number: 7611975
    Abstract: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 3, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Adrian Murrell, Peter Michael Banks, Matthew Peter Dobson, Peter Kindersley, Takao Sakase, Marvin Farley, Shu Satoh, Geoffrey Ryding
  • Patent number: 7582546
    Abstract: A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: September 1, 2009
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Thomas Nirschl
  • Patent number: 7569457
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: August 4, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7550355
    Abstract: A boron ion stream may be used to implant ions, such as boron ions, into the sidewalls of an active area, such as an NFET active area. The boron ion stream has both vertical tilt and horizontal rotation components relative to the sidewalls and/or the silicon device, to provide a better line of sight onto the sidewalls. This may allow components of the silicon device to be moved closer together without unduly reducing the effectiveness of boron doping of NFET active area sidewalls, and provides an improved line of sight of a boron ion stream onto the sidewalls of an NFET active area prior to filling the surrounding trench with STI material.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama
  • Patent number: 7541250
    Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 2, 2009
    Assignee: Atmel Corporation
    Inventors: Gayle W. Miller, Jr., Bryan D. Sendelweck
  • Patent number: 7476914
    Abstract: Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Gregory G. Freeman, Marwan H. Khater, Rajendran Krishnasamy, Kathryn T. Schonenberg
  • Patent number: 7468305
    Abstract: A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an N-Pocket mask, forming P-LDD regions on the semiconductor chip using a P-LDD mask, and forming P-Pocket regions on the semiconductor chip using a P-Pocket mask.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: December 23, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Michael Yu, Chih-Ping Chao, Chih-Sheng Chang, Chun-Hong Chen
  • Patent number: 7439092
    Abstract: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate with ions of a non-gaseous heavy species in order to implant those ions in a concentration sufficient to create in the substrate a layer of microcavities containing a gaseous phase formed by the element of the substrate; (2) bringing this face of the substrate into intimate contact with a stiffener; and (3) obtaining cleavage at the level of the microcavity layer by the application of heat treatment and/or a splitting stress.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: October 21, 2008
    Assignee: Commissariat A l'Energie Atomique
    Inventor: Aurélie Tauzin
  • Patent number: 7314805
    Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: January 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki
  • Patent number: 7300851
    Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: November 27, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masao Okihara
  • Patent number: 7276421
    Abstract: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: October 2, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hyuk Kim, Soon-Moon Jung, Won-Seok Cho, Jae-Hoon Jang, Kun-Ho Kwak, Sung-Jin Kim, Jae-Joo Shim
  • Patent number: 7271443
    Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: September 18, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masafumi Hamaguchi
  • Patent number: 7253072
    Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James D. Bernstein, Lance S. Robertson, Said Ghneim, Nandu Mahalingam, Benjamin Moser
  • Patent number: 7253067
    Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting fist ions onto the surface of the semiconductor substrate in a region other than a stress region in the active region, which is located at the interface with the element isolation region, in the stress region, a potential stress is generated by forming the element isolation region and/or the difference between a material of the element isolation region and a material of the semiconductor substrate, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed; and second ion implanting second ions each of which mass is smaller than that of each of the first ions so that a second ion impurity region is formed in the stress r
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 7, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Kanshi Abe
  • Patent number: 7220649
    Abstract: The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate insulation film is removed to form an opening that exposes an outside area of the active area, which is outside of the central area where a gate electrode will be formed. A shallow grade layer is formed by implanting impurities into an opening with an energy that does not permit penetration of impurity ions through the gate insulation film.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 22, 2007
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Ryo Nakamura
  • Patent number: 7195986
    Abstract: A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the microchannel or well to increase conductivity of the region.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 27, 2007
    Assignee: Caliper Life Sciences, Inc.
    Inventors: Luc J. Bousse, Seth R. Stern, Richard J. McReynolds
  • Patent number: 7169674
    Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Kevin Kok Chan, Christopher Peter D'Emic, Evgeni Gousev, Supratik Guha, Paul C. Jamison, Lars-Ake Ragnarsson
  • Patent number: 7157346
    Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: January 2, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Ting Chen, Wen-Bin Lu, Chao-Hu Liang
  • Patent number: 7144787
    Abstract: Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Omer H. Dokumaci, Gregory G. Freeman, Marwan H. Khater, Rajendran Krishnasamy, Kathryn T. Schonenberg