Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (?m).

Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.

Abstract: An assembly (20) includes a MEMS die (22) having a pressure transducer device (40) formed on a substrate (44) and a cap layer (38). A packaging process (74) entails forming the device (40) on the substrate, creating an aperture (70) through a back side (58) of the substrate underlying a diaphragm (46) of the device (40), and coupling a cap layer (38) to the front side of the substrate overlying the device. A trench (54) is produced extending through both the cap layer and the substrate, and the trench surrounds a cantilevered platform (48) at which the diaphragm resides. The MEMS die is suspended above a substrate (26) so that a clearance space (60) is formed between the cantilevered platform and the substrate. The diaphragm is exposed to an external environment (68) via the aperture, the clearance space, and an external port.

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract: A method for producing a sealed cavity, including: a) producing a sacrificial layer on a substrate; b) producing a cover layer covering at least the sacrificial layer and a portion of the face of the substrate not covered by the sacrificial layer, the cover layer including lateral flanks forming, with the substrate, an angle of less than 90°; c) producing a hole through one of the lateral flanks of the cover layer such that a maximum distance between the substrate and an edge of the hole is less than approximately 3 ?m, the hole crossing a portion of the cover layer deposited on a portion of the substrate not covered by the sacrificial layer; d) eliminating the sacrificial layer through the hole, forming the cavity; and e) depositing at least one material plugging the hole in a sealed fashion.

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.

Abstract: According to the invention, there is provided a novel soybean variety designated XB22N06. This invention thus relates to the seeds of soybean variety XB22N06, to the plants of soybean XB22N06 to plant parts of soybean variety XB22N06 and to methods for producing a soybean plant produced by crossing plants of the soybean variety XB22N06 with another soybean plant, using XB22N06 as either the male or the female parent.

Abstract: A method and structure for a semiconductor structure that includes a substrate having at least one integrated circuit heat generating structure is disclosed. The invention has at least one integrated circuit cooling device on the substrate adjacent the heat generating structure. The cooling device is adapted to remove heat from the heat generating structure. The cooling device includes a cold region and a hot region. The cold region is positioned adjacent the heat generating structure. The cooling device has one of a silicon germanium super lattice structure. The cooling device also has a plurality of cooling devices that surround the heat generating structure. The cooling device includes a thermoelectric cooler.

Abstract: Semiconductor devices are known comprising a multiple p-n junction RESURF semiconductor material (10) that provides a voltage-sustaining space-charge zone when depleted from a blocking junction (40). Charge balance is important in the alternating p-type (11) and n-type (12) regions which together provide the voltage-sustaining space-charge zone. The invention provides a low-cost yet reliable way of manufacturing such a material (10), and also devices with such a material (10). A p-type silicon body (100) having an acceptor doping concentration (Na) for the p-type regions (11) of the material is subjected to irradiation with collimated beams (152) of thermal neutrons (150) at window areas (52) in a mask (50) so as to form the n-type regions (12) by transmutation of silicon atoms into phosphorus. A well-defined and controllable phosphorus doping concentration to balance the low acceptor concentration of the p-type regions (11) is achievable in this manner, even when the acceptor concentration is of boron.

Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.

Abstract: A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of free charge carriers the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area. The method starts with a semiconductor body having adjacent a first major surface (10b) a first semiconductor region (2) of one conductivity type. A mask (3, 4, 5) is provided on the first major surface, having at least one mask area masking a part (2a) of the first region. At least a part of the unmasked first region (2) is then removed to provide at least one opening (7) in the first region.

Abstract: A method of converting ball grid array (BGA) modules to column grid array (CGA) modules comprises steps of heating a BGA module, brushing the BGA module to remove the balls, and attaching columns to the module to create a CGA module. A method of converting a first CGA module to a second CGA module comprises steps of heating the first CGA module, brushing the first CGA module to remove the columns, and attaching columns to the module to create the second CGA module.

Abstract: A process for fabricating a MEMS device is disclosed. The device has at least one hinged element. The MEMS device including the hinged element is delineated and defined on a semiconductor substrate. The substrate is placed device side down in a chamber. The MEMS device is then exposed to a release expedient for sufficient amount of time for the release expedient to dissolve a sacrificial material connecting the element to the substrate. Upon the dissolution of the sacrificial material, the element is released from the substrate and pivots away from the surface.

Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.

Abstract: A process is disclosed for producing spatially patterned components from a body. On the backside of the body, a retardation layer with openings is provided for retarding a removal of the material of the body, and areas of migration-capable material are deposited. The body is subjected to a thermal migration process to form migration regions. Then, in a single material removal step, the components are separated from the body and the migration regions are exposed.