Formation Of Electrically Isolated Lateral Semiconductive Structure Patents (Class 438/400)
  • Patent number: 10978556
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 10896875
    Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 10832960
    Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming an interfacial dielectric around alternate semiconductor layers of the plurality of FET devices, depositing a first sacrificial capping layer over the plurality of FET devices, selectively removing the first sacrificial capping layer from a first set of the plurality of FET devices, depositing a second sacrificial capping layer and an oxygen blocking layer, selectively removing the oxygen blocking layer from a second set of the plurality of FET devices, and performing an anneal to create the different gate dielectric thicknesses for each of the plurality of FET devices.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee
  • Patent number: 10763115
    Abstract: A method of removing an oxide layer is provided. A metal layer is deposited over an oxide layer formed at a top surface of a germanium substrate. A metal oxide layer is deposited over the metal layer. The metal oxide layer includes a same metal material as the metal layer. The metal layer and the oxide layer are reacted and combined with the metal oxide layer to form a dielectric layer during an anneal process. During the anneal process, the oxide layer is reacted with the metal layer and removed.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: September 1, 2020
    Assignee: NXP USA, Inc.
    Inventor: Rama I. Hegde
  • Patent number: 10756214
    Abstract: A semiconductor device includes a substrate, and a semiconductor fin structure formed on the substrate. The semiconductor device also includes a dielectric liner disposed on and in direct contact with a top surface of the substrate and a sidewall of the semiconductor fin structure. The semiconductor device includes a first isolation layer disposed on and in direct contact with a top surface and a sidewall of the dielectric liner. The semiconductor device also includes a second isolation layer disposed on and in direct contact with a top surface of the first isolation layer and a sidewall of the semiconductor fin structure. The semiconductor device also includes an oxide isolation region formed beneath the semiconductor fin structure by oxidation through the second isolation layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 25, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventor: Qing Liu
  • Patent number: 10714487
    Abstract: A semiconductor device includes a transistor, an isolation structure, and a fin sidewall structure. The transistor includes a fin extending from a substrate and an epitaxy structure grown on the fin. The isolation structure is above the substrate. The fin sidewall structure is above the isolation structure and is on a sidewall of the epitaxy structure. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Tsz-Mei Kwok, Ming-Hua Yu, Kun-Mu Li
  • Patent number: 10600684
    Abstract: In one embodiment, a method of forming a barrier layer is provided. The method includes positioning a substrate in a processing chamber, forming a barrier layer over the substrate and in contact with the underlayer, and annealing the substrate. The substrate comprises at least one underlayer having cobalt, tungsten, or copper. The barrier layer has a thickness of less than 70 angstroms.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Yihong Chen, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10562261
    Abstract: A display substrate and a display device are provided. The display substrate includes a display area located inside the display substrate and a barrier layer, located between the display area and a substrate edge of the display substrate, wherein the barrier layer includes at least two rows of first hole sections arranged alternately on a direction from the display area to the substrate edge, each row of the first hole sections includes at least two first hole sections arranged alternately on an extending direction of the substrate edge, wherein a projection of the first hole sections of the adjacent rows on the extending direction of the substrate edge overlaps each other. By practice of the disclosure, the extending of the crack could be effectively avoided, so the product yield could be improved.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 18, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiaoxia Zhang
  • Patent number: 10535695
    Abstract: Described herein is an electronic device that includes a first integrated circuit die having formed therein at least one photodiode and readout circuitry to convert charge generated by the at least one photodiode to a read voltage and to selectively output the read voltage. A second integrated circuit die is in a stacked arrangement with the first integrated circuit die and has formed therein storage circuitry to selectively transfer the read voltage to at least one storage capacitor for storage as a stored voltage and to selectively transfer the stored voltage to an output. The at least one storage capacitor is formed from a capacitive deep trench isolation. There is an interconnect between the first and second integrated circuit dies for coupling the readout circuitry to the storage circuitry.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Jeffrey M. Raynor
  • Patent number: 10503068
    Abstract: A method for forming a resist pattern including forming a first contact hole pattern including a hole portion and a hole-unformed portion, which includes alkali developing the exposed positive-type resist film; preparing a structure including the first contact hole pattern and a first layer which covers the first contact hole pattern, which includes forming a first layer by applying a solution including an acid or a thermal acid generator onto a support on which the first contact hole pattern is formed; forming organic solvent-soluble and organic solvent-insoluble regions on the hole-unformed portion, which includes heating the structure; and forming a second contact hole pattern on the hole-unformed portion, which includes developing the heated structure with an organic solvent.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: December 10, 2019
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Takayoshi Mori, Ryoji Watanabe, Yoichi Hori
  • Patent number: 10483118
    Abstract: A selectivity can be improved in a desirable manner when etching a processing target object containing silicon carbide. An etching method of processing the processing target object, having a first region containing silicon carbide and a second region containing silicon nitride and in contact with the first region, includes etching the first region to remove the first region atomic layer by atomic layer by repeating a sequence comprising: generating plasma from a first gas containing nitrogen to form a mixed layer containing ions contained in the plasma generated from the first gas in an atomic layer of an exposed surface of the first region; and generating plasma from a second gas containing fluorine to remove the mixed layer by radicals contained in the plasma generated from the second gas.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 19, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sho Kumakura, Masahiro Tabata
  • Patent number: 10475925
    Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Hsin-Che Huang, Shyan-Liang Chou, Hung-Lin Shih
  • Patent number: 10438888
    Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 10325776
    Abstract: An n-type layer (3) is formed by implanting an n-type impurity in a back surface of a Si substrate (1). A recess (4) is formed in the back surface of the Si substrate (1). After forming the n-type layer (3), an oxide film (5) is formed on the back surface and in the recess (4). The oxide film (5) on the back surface is removed while the oxide film (5) in the recess (4) is left. After removing the oxide film (5), an Al—Si film (6) is formed on the back surface. A metal electrode (7) is formed on the Al—Si film (6). The oxide film (5) in the recess (4) prevents Al from diffusing from the Al—Si film (6) into the Si substrate (1) through the recess (4).
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 18, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Misato Hisano
  • Patent number: 10319427
    Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Hoon Jeon, Yong Seok Kim, Jun Hee Lim
  • Patent number: 10269736
    Abstract: A device includes a metal pad, and a passivation layer comprising portions overlapping edge portions of the metal pad. The metal pad and the passivation layer are in a chip. A solder region is over the passivation layer. A metallic feature electrically inter-couples the metal pad and the solder region, and the metallic feature includes a continuous metal region. A polymer layer includes an upper portion over the metallic feature, and a lower portion penetrating through the continuous metal region.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Yu-Ting Huang
  • Patent number: 10269649
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10157914
    Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Yi-Tang Lin
  • Patent number: 10121865
    Abstract: The silicon carbide layer has a second main surface. The second main surface has a peripheral region within 5 mm from an outer edge thereof, and a central region surrounded by the peripheral region. The silicon carbide layer has a central surface layer. An average value of a carrier concentration in the central surface layer is not less than 1×1014 cm?3 and not more than 5×1016 cm?3. Circumferential uniformity of the carrier concentration is not more than 2%, and in-plane uniformity of the carrier concentration is not more than 10%. An average value of a thickness of a portion of the silicon carbide layer sandwiched between the central region and the silicon carbide single-crystal substrate is not less than 5 ?m. Circumferential uniformity of the thickness is not more than 1%, and in-plane uniformity of the thickness is not more than 4%.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: November 6, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tsutomu Hori, Hironori Itoh
  • Patent number: 10109741
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10068963
    Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 4, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
  • Patent number: 9853031
    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
  • Patent number: 9825125
    Abstract: In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: November 21, 2017
    Assignee: DENSO CORPORATION
    Inventor: Yuichi Takeuchi
  • Patent number: 9812367
    Abstract: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Ji-Hwan An, Kwang-Yul Lee, Tae-Won Ha, Jeong-Nam Han
  • Patent number: 9773695
    Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: September 26, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Vinod R. Purayath, Randhir Thakur, Shankar Venkataraman, Nitin K. Ingle
  • Patent number: 9773870
    Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 9721839
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: August 1, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Brad Eaton, Ajay Kumar
  • Patent number: 9640259
    Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 2, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
  • Patent number: 9589958
    Abstract: A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical dimension to meet the target fin critical dimension.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sivananda K. Kanakasabapathy, Fee Li Lie, Eric Miller, Stuart A. Sieg
  • Patent number: 9548354
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A polysilicon layer having the first conductivity type fills the trench, and a first doping region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and on sidewalls of the trench. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 17, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao Lee, Po-Heng Lin, Chih-Cherng Liao, Jun-Wei Chen
  • Patent number: 9515160
    Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: December 6, 2016
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Kazumi Chida, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9508771
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor is provided. The CMOS image sensor may include an epitaxial layer having a first conductivity type and having first and second surfaces, a first device isolation layer extending from the first surface to the second surface to define first and second pixel regions, a well impurity layer of a second conductivity type formed adjacent to the first surface and formed in the epitaxial layer of each of the first and second pixel regions, and a second device isolation layer formed in the well impurity layer in each of the first and second pixel regions to define first and second active portions spaced apart from each other in each of the first and second pixel regions.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungwook Lee, Jungchak Ahn, Youngwoo Jung
  • Patent number: 9466675
    Abstract: A recess is formed by partially etching a silicon carbide substrate. A mask layer is formed on the silicon carbide substrate by means of photolithography using the recess as an alignment mark. An impurity is implanted into the silicon carbide substrate using the mask layer. The silicon carbide substrate is annealed. After the annealing, a first electrode layer is deposited on the silicon carbide substrate. The first electrode layer is patterned by means of photolithography using the recess in the silicon carbide substrate as an alignment mark.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 11, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Chikayuki Okamoto
  • Patent number: 9455327
    Abstract: A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (?) and 40 ?. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO2) that is used as an insulating gate layer with silicon-based power transistors. The Schottky gated transistor further includes at least one metal layer disposed over the interfacial layer. A source contact and a drain contact are disposed on the surface of the plurality of epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 27, 2016
    Assignee: Qorvo US, Inc.
    Inventor: Andrew P. Ritenour
  • Patent number: 9412743
    Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Chien-Chung Huang, Yu-Ting Tseng, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 9391198
    Abstract: A method of forming a strained trampoline including: forming a strain inducing layer on a semiconductor-on-insulator (SOI), the SOI having a semiconductor layer on an insulator layer and the insulator layer is on a handle substrate; forming a opening through the semiconductor layer and the insulator layer using a patterned hardmask; forming a trampoline support in the opening; forming a trench through the strain inducing layer and through the semiconductor layer exposing a portion of the insulator layer, a strained trampoline is a portion of the semiconductor layer with a boundary defined by the trampoline support and the trench; and removing the insulator layer through the trench, where the strained trampoline is supported by the trampoline support.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9356035
    Abstract: A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 31, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
  • Patent number: 9287387
    Abstract: The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: March 15, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Mieno Fumitake
  • Patent number: 9209279
    Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: December 8, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ying Zhang, Hua Chung
  • Patent number: 9178068
    Abstract: A method for inducing stress within the channel of a semiconductor fin structure includes forming a semiconductor fin on a substrate; forming a fin hard mask layer, multiple isolation regions, and multiple spacers, on the semiconductor fin; forming a gate structure on the semiconductor fin; and oxidizing multiple outer regions of the semiconductor fin to create oxidized stressors that induce compressive stress within the channel of the semiconductor fin. A method for inducing tensile stress within the channel of a semiconductor fin by oxidizing a central region of the semiconductor fin is also provided. Structures corresponding to the methods are also provided.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Kern Rim
  • Patent number: 9129858
    Abstract: A semiconductor device includes a memory cell transistor that is formed via a first gate insulating film on an active region of a memory cell region and has a gate electrode including a first charge storage layer, a first interelectrode insulating film, and a first control gate electrode film. A transistor, which includes a second gate insulating film on the active region or a peripheral circuit region and a gate electrode including a second charge storage layer, a second interelectrode insulating film, and a second control gate electrode film, is also provided. A groove with a funnel shape is formed in a trap film of the second charge storage layer, and the second control gate electrode film and the polysilicon film of the second charge storage layer are interconnected via the groove.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Nagashima
  • Patent number: 9059394
    Abstract: A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventor: Matthew J. Breitwisch
  • Patent number: 9040382
    Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu
  • Publication number: 20150137306
    Abstract: An N type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a P type epitaxial layer covering a surface of a P type semiconductor substrate to reach the surface of the semiconductor substrate. An N type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region. High breakdown voltage isolation region includes a corner portion located along a corner pattern of rectangular high-side circuit region, and a linear portion located along a linear pattern thereof. The concentration of an impurity in an N type diffusion layer of corner portion is set to be higher than the concentration of an impurity in an N type diffusion layer of linear portion.
    Type: Application
    Filed: September 8, 2014
    Publication date: May 21, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Manabu YOSHINO
  • Publication number: 20150137305
    Abstract: Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode.
    Type: Application
    Filed: December 11, 2014
    Publication date: May 21, 2015
    Inventors: Andre Schmenn, Damian Sojka, Carsten Ahrens
  • Patent number: 9029954
    Abstract: A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a semiconductor substrate, a first gate insulating film having a first high-dielectric-constant insulating film containing a first metal for adjustment, and a first electrode formed on the first gate insulating film. A protrusion amount of one end of the first high-dielectric-constant insulating film on the first device isolation part is smaller than a protrusion amount of an end of the first gate electrode above the first device isolation part.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 12, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Tomohiro Fujita
  • Publication number: 20150123138
    Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: AVOGY, INC.
    Inventors: Isik C. Kizilyalli, David P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 9023704
    Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Young Yoon, Chang-Sun Hwang, Bo-Kyeong Kang, Jae-Seok Kim, Ho-Young Kim, Bo-Un Yoon
  • Patent number: 9023712
    Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: May 5, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Roman Boschke, Markus Forsberg
  • Patent number: 9023713
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) substrate. A PFET temporary gate structure and an NFET temporary gate structure are formed on the substrate. The method implants ions to form lightly doped active areas around the gate structures. A diffusionless annealing process is performed on the active areas. Further, a compressive strain region is formed around the PFET gate structure and a tensile strain region is formed around the NFET gate structure.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Ralf Illgen, Stefan Flachowsky