Abstract: An embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: A backside illuminated image sensor includes a sensor layer comprising photosensitive elements of the pixel array, an epitaxial layer formed on a frontside surface of the sensor layer, and a color filter array formed on a backside surface of the sensor layer. The epitaxial layer comprises polysilicon color filter array alignment marks formed in locations corresponding to respective color filter array alignment mark openings in the frontside surface of the sensor layer. The color filter array is aligned to the color filter array alignment marks of the epitaxial layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.

Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.

Abstract: Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of a non-selective epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source such as silane and a higher order silane, followed by heating the substrate to promote solid phase epitaxial growth.

Abstract: A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain regions of the first conductivity type impurity formed in the semiconductor substrate and extended from edge portions of the gate electrode, and second source/drain regions having a first conductivity type impurity concentration lower than that in the first source/drain regions and formed adjoining the gate insulation film and the first source/drain regions in the semiconductor substrate so as to overlap portions of the conductive portion of the gate electrode.

Abstract: Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-crystallized while growing crystal grains laterally. Further a second rapid thermal treatment is performed all over the panel so as to reduce defects in the crystal grains in a region PSI poly-crystallized by the aforementioned energy beam. Thus, a high-quality polycrystalline semiconductor thin film serving as TFTs for a high-performance circuit and having a high on-current, a low threshold value, a low variation and a sharp leading edge characteristic is obtained.

Abstract: A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; performing a thermal treatment of the substrate to getter oxygen and forming a barrier layer; and filling copper into the via hole and the trench.

Abstract: The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.

Abstract: A coplanar mounting member for a MEM sensor includes a first surface coplanar with a connection pad on the surface of a MEM sensor board containing the MEM sensor control circuit; a second surface inclined to the surface of the board for mounting a MEM sensor and an electrical conductor array for interconnecting the MEM sensor with the connection pad on the board.

Abstract: An active matrix substrate includes a load circuit including a first active element performing a switching operation of a load, the first active element including a semiconductor film of a substantially polycrystalline state; a drive circuit including a second active element controlling driving the load, the second active element including a semiconductor film of a substantially single crystalline state, a hole being provided to one of a part and a peripheral part of the semiconductor film, the hole functioning a starting point for crystallizing the semiconductor film; and a substrate on a same plane of which the load circuit and the drive circuit are formed.

Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality of semiconductor chips of different kinds (processor chip and memory chip) are formed on a semiconductor wafer, and a go/no-go test is conducted on all the chips. The semiconductor wafer is cut and divided into pieces that each consist of a good processor chip and a good memory chip, and they are mounted on a substrate to form a semiconductor module.

Abstract: A wafer cassette comprises a holding member having a depression corresponding to the shape of the substrate, and a cover having an opening smaller than the surface size of the substrate. The substrate is to be held in the depression by means of the holding member and the cover, and the substrate is to be covered at its one-side surface, side and all peripheral region of the other-side surface, with the holding member at its depression and with the cover at the edge of its opening. Also disclosed are a liquid-phase growth system and a liquid-phase growth process which make use of the wafer cassette.

Abstract: A semiconductor device which is mounted with a plurality of semiconductor chips. The fraction defective is low when the device is manufactured, and the efficiency of inspection is high. A method for manufacturing such a semiconductor device is also disclosed. A plurality of kinds of semiconductor chips 1 are COB-mounted on a substrate 2 and the surface of the substrate 2 mounted with the chips 1 is encapsulated with a resin 3. Then all the chips 1 mounted on the substrate 2 are inspected at once. Semiconductor devices 10 are produced by cutting the substrate 2 into pairs of adjacently arranged two different kinds of semiconductor chips 1 together which are judged to be nondefective chips.

Abstract: An identification document and a method of placing personalized data (variable text and color image) directly on the identification document having a data receiving page. The method comprises the steps of: printing personalized data directly onto a silicone release coat of a release sheet; positioning the release sheet with the side containing fused toner adjacent to the adhesive of an adhesive side of a security laminate; passing the release sheet and the security laminate through a laminator to transfer the personalized data to the adhesive of the security laminate; removing the release sheet leaving the personalized data on the security laminate; and passing the security laminate and the data receiving page through a laminator to seal personalized data between the security laminate and the data receiving page.

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.