Abstract: There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a break down voltage between wells is reduced and an insulating characteristic between the wells is lowered due to degraded barrier characteristic between the wells, in a flash memory device employing a triple well structure, the present invention forms an anti-diffusion region for preventing diffusion of dopants between a P-well region and a N-well region by nitrogen ion implantation, thus improving the electrical characteristic of the device.

Abstract: A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region and the first doped region are doped with a first type dopant and the first well region is electrically connected to the first doped region. An isolation region is formed between the first well region and the first doped region. The isolation region is electrically connected to a second well region. The isolation region and the second well region are doped with a second dopant type The second dopant type is opposite the first dopant type. In one embodiment, the first type dopant includes a p-type dopant, and the second type dopant includes an n-type dopant. The method may further include, forming a second doped region within the first well region and below the isolation region.

Abstract: A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. Thus a triple N well is formed. A fourth ion implantation step is performed to form a cell well surrounded by the annular longitudinal deep N well. The cell well lies above the transversal deep N well. The second mask layer is removed.

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract: A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate electrodes are formed via a gate oxide film and then sidewall oxide films are formed, on the semiconductor substrate. Thereafter, an ion implantation of a P-type impurity is performed with a dose two orders of magnitude smaller than that of the N-type impurity for element isolation, with the gate electrodes and the sidewall oxide films being employed as a mask, thereby forming P-type impurity regions. The P-type impurity regions are caused to diffuse due to thermal processing in the following step. However, the element isolating P-type impurity regions resulted from the diffusion diffuse only into immediately under the sidewall oxide films at most, thus preventing the channel width from being narrowed.

Abstract: A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants. After filling the deep trenches with insulating material, a diffusion process is done. This diffusion process performs in such a way that the formerly predeposited dopant is distributed rather uniformly in between the parallel deep trenches, e.g. is counterdoping the whole region with respect to the monocrystalline silicon substrate. The said lateral trench doped region, which preferably is more deep than wide, serves either as drain or collector region of high voltage transistors or other high voltage devices. Also other devices like hall sensors, which gain advantages from the more deep than wide counterdoped regions, are possible.

Abstract: In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capability. The current block is created by implanting P+ into a region in an N+ drain, and through the drain into an N-well laying below the drain. A high resistance of the block forces drain current flowing from the channel to the drain contact into the semiconductor bulk. The block is the full width of the drain spreading out the current from an ESD and forcing current from the channel down into the N-well, under the block, and back up to the drain contact area. The increased path and the spreading of the drain current through the semiconductor bulk enhances heat dissipation, and allows smaller devices and layout area with ESD protection.

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention, only one conductivity type of impurities are implanted in each well. Therefore, it is possible to prevent the decrease of the carrier mobility and increase of the leakage current.

Abstract: A twin well forming method for a semiconductor device includes the steps of forming a first insulation layer on a semiconductor substrate, selectively etching the first insulation layer to obtain a first insulation layer pattern and a first buffer insulation, ion-implanting first impurities through the first buffer insulation layer into the semiconductor substrate, forming a second insulation layer on the first insulation layer pattern and the first buffer insulation layer, spreading a planarizing material on the second insulation layer and applying the planarizing material to an annealing treatment to obtain a planarizing material layer, etching back the planarizing material layer and the second insulation layer to expose an upper surface of the first insulation layer pattern, forming a second buffer insulation layer by partially etching the first insulation layer pattern, ion-implanting second impurities through the second buffer insulation layer into the semiconductor substrate, removing the second insulat

Abstract: A semiconductor device having an electrostatic discharge protection device and at least one accompanying device selected from the group comprising of a N or P channel MOS transistor, CMOS, bipolar transistor and BiCMOS, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including; a semiconductor substrate; an epitaxial layer laminated on the semiconductor substrate; a buried collector of a first conductivity type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer; a base of a second conductivity type which is a lightly doped well and formed on the epitaxial layer; and an emitter of the first conductivity type and formed on the surface layer of the base of the second conductivity type; and in which the base is adapted to have impurity concentration and depth so that a punch-through is generated between the emitter and the collector of the electrostatic discharge protection dev

Abstract: A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A mask pattern is formed on the semiconductor substrate of a predetermined conductivity type to expose a region where the MOS transistor, having a same conductivity type as that of the substrate, is to be formed wherein the mask pattern has a vertical boundary face having a gradual slope. A buried layer is then formed in the form of island by ion-implanting the impurity ions into the substrate to pass through the mask pattern, the buried layer having a same conductivity type as that of the substrate, and being formed to be continuous under the vertical boundary face of the mask pattern.

Abstract: A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.

Abstract: A method of forming a triple-well in a semiconductor device, includes the steps of forming a second conductivity type impurity region in a first conductivity type semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, forming a second conductivity type first well in a first portion of the epitaxial layer, and a second conductivity type second well in a second portion of the epitaxial layer, and forming a first conductivity type first well in the first portion of the epitaxial layer, and a first conductivity type second well in a portion of the epitaxial layer between the second conductivity type first and second wells.

Abstract: A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power suppl

Abstract: A method for fabricating a semiconductor device is provided, which includes the steps of: (i-a) forming at least one impurity region of a first conductivity type in a semiconductor substrate; (ii-a) forming a gate insulation film and a gate electrode on the impurity region of the first conductivity type followed by the formation of impurity diffusion layers of a second conductivity type in self-alignment with the gate electrode to yield plurality of transistors; (iii-a) forming low-concentration impurity layers of the second conductivity type in peripheral portions of the impurity diffusion layers of the second conductivity type; and (iv-a) implanting impurity ions of the first conductivity type into desired regions between the plurality of transistors to form device isolation regions, whereby converting at least a part of the low-concentration impurity layers of the second conductivity type to a low-concentration impurity layers of the first conductivity type.

Abstract: An improved twin well formation method for a semiconductor device capable of improving the latch-up characteristic in DRAM device which requires a high integration density and of improving a recess problem which occurs due to the capacitor, which includes the steps of a first step which forms an insulation film on a semiconductor substrate having a first region and a second region; a second step which forms a first temporary film on an insulation film of the first region; a third step which forms a first side wall spacer at the first temporary side wall; a fourth step which implants a first conductive ion to a substrate of a second region; a fifth step which forms a second temporary film on a substrate of the second region; a sixth step which removes the first temporary film; a seventh step which implants a second conductive ion to a substrate of the first region; and an eighth step which anneals and removes the second temporary film and the first insulation spacer.

Abstract: A process for fabricating double well regions for a semiconductor device having a first well region of a first type and a second well region of a second type on the substrate is disclosed. The process comprises the steps of first implanting impurities of the first type into the substrate. Then a shielding layer covering the location designated for the first well region of the first type on the substrate is formed. Impurities of the second type are then implanted into the substrate at locations not covered by the shielding layer and designated for the formation of the second well region of the second type. Finally, the impurities of both the first and the second type are driven into a designated depth of the substrate by a heating process to form the first well region of the first type and the second well region of the second type.