To Alter Conductivity Of Fuse Or Antifuse Element Patents (Class 438/467)
  • Patent number: 9419393
    Abstract: A male RJ45 connector includes a printed circuit (8) having electrical tracks, at least one grounding plate sandwiched between faces (23, 24) of the circuit and a slot extending longitudinally and opening on a side (38) of the circuit and being configured to pass through both the faces and the at least one grounding plate; and a spreader system (9) mounted on the circuit and including a separator body (25), an extension body (26) provided with a hollow (27) configured to receive the printed circuit and a central wall (28) dividing the hollow (27) into two parts and being configured to be inserted into the slot; the central wall and the at least one grounding plate being configured to be electrically interconnected and form an electrically and/or magnetically shielding barrier between pairs of conducting wires (11-14) mounted on the spreader and connected to the circuit.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 16, 2016
    Assignees: LEGRAND FRANCE, LEGRAND SNC
    Inventors: Julien Guitard, Vincent Grigis
  • Patent number: 9263484
    Abstract: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: February 16, 2016
    Assignee: Intellectual Ventures II, LLC
    Inventors: Woon-Il Choi, Hyung-Sik Kim, Ui-Sik Kim
  • Patent number: 9142767
    Abstract: Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 22, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, D. V. Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 9064794
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: June 23, 2015
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd, Qimonda AG
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Patent number: 9040370
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Publication number: 20150123702
    Abstract: The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied during semiconductor processing to provide a semiconductor die having devices of varied values. In other aspects, different areas of semiconductor dies are exposed during semiconductor processing to provide semiconductor dies with devices that vary in value from one die to the next. For each semiconductor die, a value generated based on the values of the die's respective devices can be associated with that die thereby enabling subsequent authentication of the semiconductor die.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 7, 2015
    Inventors: Patrick A. McKinley, Walter Lee McNall, Robert W. Shreeve, Thomas Page Bruch, Neal C. Jaarsma
  • Publication number: 20150076655
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Application
    Filed: April 25, 2014
    Publication date: March 19, 2015
    Inventors: Hyun-Min Choi, Shigenobu MAEDA
  • Patent number: 8969141
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventor: Laurentiu Vasiliu
  • Patent number: 8937357
    Abstract: According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: January 20, 2015
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen
  • Patent number: 8921167
    Abstract: A method of forming an electronic fuse including providing an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, forming an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the second Mx metal to the Mx+1 metal in a vertical orientation, and forming a nano-pillar from the Mx cap dielectric at a bottom of the via and above the second Mx metal, the nano-pillar having a height less than a height of the via.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20140370671
    Abstract: An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.
    Type: Application
    Filed: August 7, 2014
    Publication date: December 18, 2014
    Inventors: Yan Zun Li, Zhengwen Li, Chengwen Pei, Jian Yu
  • Publication number: 20140346655
    Abstract: A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion.
    Type: Application
    Filed: June 11, 2014
    Publication date: November 27, 2014
    Inventors: Jyun-Ying LIN, Chun-Yao KO, Ting-Chen HSU
  • Patent number: 8889490
    Abstract: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Publication number: 20140332923
    Abstract: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.
    Type: Application
    Filed: September 12, 2013
    Publication date: November 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Andrew T. Kim, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8884398
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • Publication number: 20140319650
    Abstract: An method and structure of forming an electronic fuse. The method including forming a first metal line and a second metal line in a first interconnect level, wherein the first metal line is electrically insulated form the second metal line, and forming a via in a second interconnect level above the first interconnect level, the via electrically and physically connecting the first metal line with the second metal line. The via may create a sub-lithographic contact with the underlying metal line, thus increasing current density and probability of failure at a specific location.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Jason Coyner, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8866257
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Ll, Ping-Chaun Wang
  • Patent number: 8865568
    Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: October 21, 2014
    Assignee: Hamamatsu Photonics K.K
    Inventors: Takeshi Sakamoto, Aiko Nakagawa
  • Patent number: 8860176
    Abstract: The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gregory M. Fritz, Bahman Hekmatshoartabari, Ali Khakifirooz, Dirk Pfeiffer, Kenneth P. Rodbell, Davood Shahrjerdi
  • Patent number: 8829645
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S Ozcan, Haining S Yang
  • Patent number: 8828800
    Abstract: An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Matthew R. Wordeman, Albert M. Young
  • Patent number: 8822968
    Abstract: According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideki Inokuma
  • Patent number: 8809142
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S. Ozcan, Haining S. Yang
  • Patent number: 8803281
    Abstract: A semiconductor device has a field insulating film provided on a semiconductor substrate, and a fuse provided on the field insulating film and having a fuse trimming laser irradiation portion and fuse terminals. The semiconductor device further includes an intermediate insulating film covering the fuse, a first TEOS layer on the intermediate insulating film, an SOG layer for planarizing the first TEOS layer, a second TEOS layer on the SOG layer and on the first TEOS layer, a protective film on the second TEOS layer, and an opening portion above the fuse trimming laser irradiation portion in a region from the protective film to the first TEOS layer. A seal ring is provided on the intermediate insulating film so as to surround the opening portion. The seal ring is disposed over the fuse so as to overlap each of the fuse terminals in plan view.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 12, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Hisashi Hasegawa
  • Patent number: 8785300
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Andreas Kurz, Jens Poppe
  • Patent number: 8766706
    Abstract: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 1, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Markus Lutz, Aaron Patridge, Brian H. Stark
  • Publication number: 20140179070
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsiao-Lan Yang
  • Publication number: 20140175601
    Abstract: An anti-fuse structure includes a substrate having at least a shallow trench isolation formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch.
    Type: Application
    Filed: December 24, 2012
    Publication date: June 26, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Chih-Yuan Ho
  • Patent number: 8728876
    Abstract: The invention prevents a conductive fuse blown out by laser trimming from reconnecting by a plating electrode in a plating process and prevents a plating solution etc from entering a fuse blowout portion. On a semiconductor substrate of a multilayered wiring structure including a fuse blowout groove formed by blowing out a conductive fuse by laser trimming in a trimming element forming region, a second protection layer is formed so as to cover the trimming element forming region and then a plating electrode is formed on an draw-out pad electrode made of a topmost metal wiring. A third protection layer is then formed so as to cover the semiconductor substrate including the second protection layer and have an opening on the plating electrode.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Eiji Kurose
  • Patent number: 8722518
    Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 13, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
  • Patent number: 8716071
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Patent number: 8686536
    Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Wei-Chan Kung
  • Patent number: 8674475
    Abstract: Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-kee Kim, Jung-hun Sung, Sang-moo Choi, Soo-jung Hwang
  • Patent number: 8674476
    Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
  • Patent number: 8610245
    Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinsuke Tani, Toshiyuki Nakaiso
  • Patent number: 8592941
    Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Tom C. Lee, Kevin G. Petrunich, David C. Thomas
  • Patent number: 8592288
    Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 26, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20130299940
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Application
    Filed: July 16, 2013
    Publication date: November 14, 2013
    Inventors: Andreas KURZ, Jens POPPE
  • Patent number: 8575718
    Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, William Tonti
  • Patent number: 8569755
    Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Patent number: 8569116
    Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: October 29, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Randy W. Mann, Kingsuk Maitra, Anurag Mittal
  • Publication number: 20130249046
    Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 26, 2013
    Inventors: Hsiang-Ming Chou, Kuo-Liang Pan, Chien-Feng Tseng, Yi-Chiu Tsai, Chien-Shao Tang, Hsin-Han Chen
  • Publication number: 20130224933
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 29, 2013
    Applicant: Broadcom Corporation
    Inventor: Broadcom Corporation
  • Patent number: 8507326
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 13, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Andreas Kurz, Jens Poppe
  • Patent number: 8501591
    Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 6, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih Chieh Yeh, Han Chao Lai, Wen Jer Tsai, Tao Cheng Lu, Chih Yuan Lu
  • Patent number: 8471356
    Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Patent number: 8445362
    Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
  • Patent number: 8426257
    Abstract: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Sik Park, Hae-Jung Lee, Jae-Kyun Lee
  • Patent number: 8409933
    Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu, H. Montgomery Manning
  • Publication number: 20130071998
    Abstract: An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baozhen Li, Yan Zun Li, Keith Kwong Hon Wong, Chih-Chao Yang