Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.

Abstract: A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an absence of high stress areas in the surrounding substrate thereby resulting in higher fabrication yields due to lower occurrence of substrate fracturing or other damage occasioned by the opening of the fuse.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover. the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: An antifuse includes a grid having at least one n-well active stripe and at least one polysilicon stripe; a first oxide layer having a first oxide thickness, the first oxide layer adapted to electrically short the n-well active stripe with the polysilicon stripe; and a second oxide layer surrounding the first oxide and thicker than the first oxide layer.

Abstract: A method for forming a metal-to-metal antifuse disposed above and insulated from a semiconductor substrate is disclosed. The method comprises forming a first metal layer disposed above and insulated from the semiconductor substrate; forming a layer of antifuse material over and in electrical contact with the first metal layer; forming a second metal layer over and in electrical contact with the layer of antifuse material; and forming at least one barrier layer comprising a layer of TaN between the layer of antifuse material and one of the first and second metal layers.

Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

Abstract: A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed.

Abstract: The present invention relates to a fuse and a method for forming a fuse over a semiconductor substrate. The fuse comprises forming a first contact member and a second contact member over a respective first region and a second region of a patterned, electrically-conductive silicide layer, wherein the first contact member and the second contact member electrically contact the silicide layer, thereby defining a first interface and a second interface, respectively. A first contact area and a second contact area are associated with the respective first contact member and second contact member, wherein the first contact area is larger than the second contact area, thereby defining a fusible link at the second interface. According to one example, the silicide resides over a patterned polysilicon layer, wherein the patterned polysilicon layer generally tapered, and wherein the first region is wider than the second region.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an “on” signal to the gate (38) of control transistor (36) only when a_“select_” signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.

Abstract: The present invention includes forming a first conductive layer in a first dielectric layer, followed by forming a second dielectric layer on the first dielectric layer. The second dielectric layer is patterned to form openings on the second dielectric layer, a patterned photoresist is used as a mask to etch holes on the bottom of openings through the second dielectric layer to expose the surface of the first conductive layer 4, and an anti-fuse layer is formed on the second dielectric layer and on a surface of the holes. A photoresist is formed on the anti-fuse layer to expose un-programmable area, followed by plasma etching the anti-fuse layer on the un-programmable area using the photoresist as mask to expose the first conductive layer on the un-programmable area. The photoresist is removed. A second conductive layer is formed on the anti-fuse layer and refilling into the holes.

Abstract: A fabrication method for forming a semiconductor device having a fuse is provided. A substrate includes a cell array area, a peripheral circuit area and a global step difference between the cell array area and the peripheral circuit area. The substrate comprises a fuse formed in the peripheral circuit of the substrate. An interlayer insulating layer is formed on the global step difference. The global step difference is reduced by a cell open process. A multilevel metal interconnection including an intermetal insulating layer is formed on the resultant structure. During the cell open process and/or the process for forming the multilevel metal interconnection, the interlayer insulating layer and/or the intermetal insulating layer is partially removed to form a recess. A passivation layer is formed on the multilevel metal interconnection. A fuse opening is formed through the recess to expose the fuse.

Abstract: The invention provides a method for activating fuse units (101a-101n) in an electronic circuit device (100) in order to modify a circuit design for the electronic circuit device (100), where an electronic circuit device (100) in which fuse units (101a-101n) can be activated is selected, those fuse units (101a-101n) in the selected electronic circuit device (100) which can be activated in order to modify the circuit design for the electronic circuit device (100) are determined, the fuse units (101a-101n) which can be activated in order to mosdify the circuit design for the electronic circuit device (100) are addressed using fuse addressing units (102a-102n), and an activation state of the fuse units (101a-101n) which can be activated in order to modify the circuit design for the electronic circuit device (100) is stipulated, the fuse units (101a-101n) addressed using the fuse addressing units (102a-102n) being activated using fuse activation units (103a-103n) in line with the stipulated activation state.

Abstract: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected.

Abstract: Within both an anti-fuse structure and a method for operating the anti-fuse structure there is employed a semiconductor substrate having a first region adjoining a second region, where there is formed a metal oxide semiconductor field effect transistor within and upon the first region of the semiconductor substrate and a metal oxide semiconductor capacitor within the upon the second region of the semiconductor substrate. Further, within the anti-fuse structure: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor is thicker than a capacitive dielectric layer within the metal oxide semiconductor capacitor; and (2) the metal oxide semiconductor capacitor is formed employing as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: A semiconductor device of the present invention is provided with a first metal wire formed above a semiconductor substrate with an interlayer insulating film intervened, a fuse formed on interlayer insulating film so as to be spaced at a distance away from first metal wire, an insulating film which covers first metal wire and which has an opening above fuse, a second metal wire formed on insulating film, a first passivation film which covers second metal wire and fuse, and a second passivation film formed on first passivation film, made of a material different from that of first passivation film and having an opening above fuse.

Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Abstract: An antifuse structure of the present invention comprises an antifase layer and a bottom electrode which are immune to the damages caused by harmful processing environment. The three major components of the antifuse—the bottom electrode, the antifuse layer and the top buffer layer are formed consecutively in a friendly manufacturing environment. This antifuse structure can substantially improve the antifuse manufacturability.

Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.

Abstract: A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.

Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

Abstract: A programmable anti-fuse is formed simultaneously with transistors and other devices on a semiconductor substrate. Embodiments include an anti-fuse comprising a doped active region in the substrate, such as an n+ region, a gate oxide layer, and a gate, such as polysilicon, of a minimum size according to design rules. The anti-fuse is programmed by passing a current through it sufficient to cause its gate oxide layer to fail. The inventive anti-fuse is formed by simply altering the patterning of layers that need to be formed for other devices on the substrate. Therefore, it is formed without added manufacturing costs.

Abstract: A semiconductor antifuse device that utilizes a resistive heating element as both a heating source or fuse blowing and as part of the fuse link. The antifuse device may also be utilized as a fuse and the antifuse or fuse embodiment can be programmed and read with the same two electrodes. The antifuse or fuse is well suited for use and efficient fabrication in a printhead apparatus or other circuit arrangements.

Abstract: A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology.

Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: An apparatus and methods for testing a semiconductor integrated circuit are disclosed. One embodiment includes a method for making a pass/fail determination in a semiconductor integrated circuit device. The method includes executing a test on the device after assembly and determining a pass/fail state of the device in response to the test. The method further includes programming a test history fuse on the semiconductor integrated circuit device to store a pass/fail state of the device. Another embodiment further includes performing a final test on the device, wherein if the stored pass/fail state indicates a pass state, a reduced final test is executed. A semiconductor integrated circuit device including internal circuitry, self test circuitry, and test history fuse circuitry is also disclosed.

Abstract: A programmable interconnect structure and method of operating the same provides a programmable interconnection between electrical contacts. The interconnect includes material that has a reversibly programmable resistance. The material includes a molecular matrix with ionic complexes distributed through the molecular matrix. Application of an electrical field or electric current causes the molecular composite material to assume a desired resistivity (or conductivity) state. This state is retained by the molecular composite material to thus form a conductive or a non-conductive path between the electrical contacts.

Abstract: A method of forming metal fuses. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Abstract: The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connecti

Abstract: A copper fuse structure for integrated circuit employs two copper pads formed over a semiconductor substrate. The two copper pads are electrically insulated by dielectrics. An aluminum line is utilized to cover and electrically connect the two copper pads.

Abstract: A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.

Abstract: An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

Abstract: Within both an anti-fuse structure and a method for operating the anti-fuse structure there is employed a semiconductor substrate having a first region adjoining a second region, where there is formed a metal oxide semiconductor field effect transistor within and upon the first region of the semiconductor substrate and a metal oxide semiconductor capacitor within the upon the second region of the semiconductor substrate. Further, within the anti-fuse structure: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor is thicker than a capacitive dielectric layer within the metal oxide semiconductor capacitor; and (2) the metal oxide semiconductor capacitor is formed employing as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: A fuse circuit includes electrical fuse elements which are commonly connected at one-side ends, a voltage generating section and a readout section. The voltage generating section is configured to selectively apply program voltage for destroying the electrical fuse element and read voltage for reading out the destructive/nondestructive states of the electrical fuse elements to a common connection node of the one-side ends of the electrical fuse elements. The readout section is configured to read out the destructive/nondestructive states of the electrical fuse elements from the other ends of the electrical fuse elements when the read voltage is applied to the common connection node from the voltage generating section.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing.