Electromigration Patents (Class 438/468)
  • Patent number: 9484412
    Abstract: A structure includes a substrate; a plurality of pFET fins disposed over the substrate; and a plurality of nFET fins disposed over the substrate. In the structure each of the plurality of pFET fins is composed of s-Si1-xGex, where x has a value in a range of about 0.4-0.6; each of the plurality of nFET fins is composed of one of s-Si or a Group III-V material; and each of the plurality of pFET fins and the plurality of nFET fins includes a thin (e.g., <1 nm) multilayer structure containing a plurality s-Ge monolayers disposed on a surface thereof, a gate dielectric disposed over the multilayer structure, and a gate conductor disposed over the gate dielectric. The presence of the multilayer structure containing the plurality s-Ge monolayers enhances Tinv scaling by effectively increasing a Ge percentage of the s-Si1-xGex pFETs. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Pranita Kerber, Alexander Reznicek
  • Patent number: 9406803
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar, Steven Bentley
  • Patent number: 8999819
    Abstract: The present invention relates generally to dendritic metal structures and devices including them. The present invention also relates particularly to methods for making dendritic metal structures without the use of solid electrolyte materials. In one aspect, a method for constructing a dendritic metal structure includes providing a substrate having a surface and a cathode disposed on the surface; providing an anode comprising a metal; and disposing a liquid on the surface of the substrate, such that the liquid is in electrical contact with the anode and the cathode; and then applying a bias voltage across the cathode and the anode sufficient to grow the dendritic metal structure extending from the cathode. The methods described herein can be used to grow dendritic metal electrodes, which can be useful in devices such as LEDs, touchscreens, solar cells and photodetectors.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: April 7, 2015
    Assignee: Arizona Board of Regents, A Body Corporate of the State of Arizona Acting For on Behalf of Arizona State University
    Inventors: Michael N. Kozicki, Minghan Ren
  • Patent number: 8901738
    Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, David L. Harame, Baozhen Li, Timothy D. Sullivan, Bjorn K. A. Zetterlund
  • Patent number: 8900973
    Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: December 2, 2014
    Assignees: International Business Machines Corporation, Globalfoundries Inc., Renesas Electronics America Inc., STMicroelectronics, Inc.
    Inventors: Nathaniel C. Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C. Mehta, Paul A. Ronsheim, Toyoji Yamamoto, Zhengmao Zhu
  • Publication number: 20140227861
    Abstract: The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to from a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Jung Wu, Su-Horng Lin, Chi-Ming Yang
  • Publication number: 20140159030
    Abstract: The present invention relates to a process for preparing an electronic device comprising at least one layer selected from the group consisting of a upper electrode layer, a lower electrode layer, an organic layer and an inorganic layer, which comprises a step of introducing a nanoparticle layer or a nano/micro structure layer by adhering charged nanoparticles, before, after or during forming the layer.
    Type: Application
    Filed: March 4, 2013
    Publication date: June 12, 2014
    Inventors: Changsoon Kim, Hyungchae Kim, Jongcheon Lee, Kyuhee Han, Hyangki Sung, Kinam Jung, Hoseop Choi, Kyungyeon Ha, Man Soo Choi
  • Patent number: 8742531
    Abstract: The present invention relates generally to electrical devices. The present invention relates more particularly to electrical devices including dendritic metal electrodes. One aspect of the present invention is an electrical device comprising a first electrode comprising at least one dendritic metal structure; a second electrode; and an electrically active structure disposed between the dendritic metal structure and the second electrode.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: June 3, 2014
    Assignee: Arizona Board of Regents, Acting for and on Behalf of Arizona State University
    Inventor: Michael Kozicki
  • Patent number: 8709858
    Abstract: The present invention relates to a method for decreasing or increasing the band gap shift in the production of photovoltaic devices by means of coating a substrate with a formulation containing a silicon compound, e.g., in the production of a solar cell comprising a step in which a substrate is coated with a liquid-silane formulation, the invention being characterized in that the formulation also contains at least one germanium compound. The invention further relates to the method for producing such a photovoltaic device.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 29, 2014
    Assignee: Evonik Degussa GmbH
    Inventors: Bernhard Stuetzel, Wolfgang Fahrner
  • Patent number: 8704210
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 22, 2014
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Patent number: 8704041
    Abstract: A variety of methods and compostions are provided, including methods and compositions for targeted modification of a specific target site in a cell or organism, methods for integrating polynucleotides of interest, methods to assess promoter activity, directly select transformed organisms, minimize or eliminate expression resulting from random integration into the genome of an organism, such as a plant, remove polynucleotides of interest, combine multiple transfer cassettes, invert or excise a polynucleotide, silence a gene, and identify and/or characterize transcriptional regulating regions. The methods involve the introduction of a cell proliferation factor and a double-strand break-inducing enzyme into an organism.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 22, 2014
    Assignee: Pioneer Hi Bred International Inc
    Inventors: William J. Gordon-Kamm, Keith S. Lowe, David J. Peterson, Christopher J. Scelonge, Grace M. St. Clair, Bing-Bing Wang
  • Patent number: 8642376
    Abstract: Methods for depositing a material atop a substrate are provided herein. In some embodiments, a method of depositing a material atop a substrate may include exposing a substrate to a silicon containing gas and a reducing gas; increasing a flow rate of the silicon containing gas while decreasing a flow rate of the reducing gas to form a first layer; and depositing a second layer atop the first layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sukti Chatterjee, Annamalai Lakshmanan, Joe Griffith Cruz, Pravin K. Narwankar
  • Patent number: 8633092
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 8575007
    Abstract: The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Timothy Harrison Daubenspeck, Jeffrey P. Gambino, Christopher David Muzzy, Wolfgang Sauter, Thomas Anthony Wassick
  • Patent number: 8575727
    Abstract: A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
  • Patent number: 8569755
    Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Patent number: 8569116
    Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: October 29, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Randy W. Mann, Kingsuk Maitra, Anurag Mittal
  • Publication number: 20130168841
    Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K.V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Publication number: 20130137242
    Abstract: Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 30, 2013
    Inventors: Zhian HE, David W. PORTER, Jonathan D. REID, Frederick D. WILMOT
  • Publication number: 20130130474
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer, The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Application
    Filed: December 12, 2012
    Publication date: May 23, 2013
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 8445362
    Abstract: An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dan Moy, Stephen Wu, Peter Wang, Brian W. Messenger, Edwin Soler, Gabriel Chiulli
  • Patent number: 8436330
    Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two dopants are present in a spatially varying region of the active region prior to device actuation. The at least two dopants have opposite conductivity types and different mobilities.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: May 7, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I Kamins, R Stanley Williams
  • Patent number: 8410560
    Abstract: A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: April 2, 2013
    Assignee: Cambridge CMOS Sensors Ltd.
    Inventors: Syed Zeeshan Ali, Florin Udrea, Julian William Gardner
  • Publication number: 20130052801
    Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS AMERICA, INC., GLOBALFOUNDRIES, STMICROELECTRONICS, INC.
    Inventors: Nathaniel C. Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C. Mehta, Paul A. Ronsheim, Toyoji Yamamoto, Zhengmao Zhu
  • Patent number: 8350264
    Abstract: An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: January 8, 2013
    Assignee: International Businesss Machines Corporation
    Inventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Publication number: 20120315740
    Abstract: A method of selective deposition on silicon substrates having regions of bare silicon and regions of oxide formed thereon. The method includes placing the substrate on a wafer support inside a processing chamber, introducing a carbon-containing gas into the reactor, applying a bias to the substrate, generating a plasma from the hydrocarbon gas, implanting carbon ions into the regions of oxide on the substrate by a plasma doping process, and depositing a carbon-containing film on the bare silicon regions.
    Type: Application
    Filed: April 26, 2012
    Publication date: December 13, 2012
    Applicant: Applied Materials, Inc.
    Inventor: Daping Yao
  • Publication number: 20120306048
    Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baozhen Li, Chunyan E. Tian, Chih-Chao Yang
  • Patent number: 8323990
    Abstract: Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Wen Shi, Wei Wei Ruan
  • Patent number: 8278173
    Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
  • Publication number: 20120238074
    Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or more dopant elements into the dopant region of the substrate using a plasma doping process; forming a cap layer atop the dopant region; annealing the dopant region after forming the cap layer; and removing the cap layer after annealing the dopant region.
    Type: Application
    Filed: July 22, 2011
    Publication date: September 20, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: KARTIK SANTHANAM, MARTIN A. HILKENE, MANOJ VELLAIKAL, MARK R. LEE, MATTHEW D. SCOTNEY-CASTLE, PETER I. PORSHNEV
  • Publication number: 20120037990
    Abstract: According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 16, 2012
    Applicant: STMicroelectronics, Inc.
    Inventors: Craig J. Rotay, John C. Pritiskutch
  • Publication number: 20120037985
    Abstract: Transistors are described, along with methods and systems that include them. In one such transistor, a field plate is capacitively coupled between a first terminal and a second terminal. A potential in the field plate modulates dopant in a diffusion region in a semiconductor material of the transistor. Additional embodiments are also described.
    Type: Application
    Filed: August 16, 2010
    Publication date: February 16, 2012
    Inventor: Michael Smith
  • Publication number: 20120001253
    Abstract: Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material is formed on the semiconductor between the pair of source/drain regions. A control gate is formed on the dielectric material. A charged species is introduced into the dielectric material. The charged species, e.g., mobile ions, has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device.
    Type: Application
    Filed: July 2, 2010
    Publication date: January 5, 2012
    Inventor: Roy Meade
  • Publication number: 20120003818
    Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.
    Type: Application
    Filed: August 12, 2011
    Publication date: January 5, 2012
    Inventors: Akram A. Salman, Stephen G. Beebe, Shuqing Cao
  • Patent number: 8089060
    Abstract: A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 3, 2012
    Assignee: Nanya Technology Corp.
    Inventors: Chun-I Hsieh, Shih-Shu Tsai, Chang-Rong Wu
  • Publication number: 20110254117
    Abstract: The present invention relates generally to electrical devices. The present invention relates more particularly to electrical devices including dendritic metal electrodes. One aspect of the present invention is an electrical device comprising a first electrode comprising at least one dendritic metal structure; a second electrode; and an electrically active structure disposed between the dendritic metal structure and the second electrode.
    Type: Application
    Filed: December 8, 2009
    Publication date: October 20, 2011
    Inventor: Michael Kozicki
  • Patent number: 8040604
    Abstract: An imaging system is presented for imaging objects within a field of view of the system. The imaging system comprises an imaging lens arrangement, a light detector unit at a certain distance from the imaging lens arrangement, and a control unit connectable to the output of the detection unit. The imaging lens arrangement comprises an imaging lens and an optical element located in the vicinity of the lens aperture, said optical element introducing aperture coding by an array of regions differently affecting a phase of light incident thereon which are randomly distributed within the lens aperture, thereby generating an axially-dependent randomized phase distribution in the Optical Transfer Function (OTF) of the imaging system resulting in an extended depth of focus of the imaging system. The control unit is configured to decode the sampled output of the detection unit by using the random aperture coding to thereby extract 3D information of the objects in the field of view of the light detector unit.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: October 18, 2011
    Assignee: Xceed Imaging Ltd.
    Inventors: Zeev Zalevsky, Alex Zlotnik
  • Publication number: 20110193062
    Abstract: Methods by which the growth of a nanostructure may be precisely controlled by an electrical current are described here. In one embodiment, an interior nanostructure is grown to a predetermined geometry inside another nanostructure, which serves as a reaction chamber. The growth is effected by a catalytic agent loaded with feedstock for the interior nanostructure. Another embodiment allows a preexisting marginal quality nanostructure to be zone refined into a higher-quality nanostructure by driving a catalytic agent down a controlled length of the nanostructure with an electric current. In both embodiments, the speed of nanostructure formation is adjustable, and the growth may be stopped and restarted at will. The catalytic agent may be doped or undoped to produce semiconductor effects, and the bead may be removed via acid etching.
    Type: Application
    Filed: November 23, 2010
    Publication date: August 11, 2011
    Applicant: The Regents of the University of California
    Inventors: Kenneth J. Jensen, William E. Mickelson, Alex K. Zettl
  • Publication number: 20110186806
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 4, 2011
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20110186807
    Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 4, 2011
    Inventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
  • Publication number: 20110181352
    Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two dopants are present in a spatially varying region of the active region prior to device actuation. The at least two dopants have opposite conductivity types and different mobilities.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 28, 2011
    Applicant: Hewlett-Packard Development Company, LP
    Inventors: Theodore I. Kamins, R. Stanley Williams
  • Publication number: 20110180783
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 28, 2011
    Inventor: Pu-Xian Gao
  • Patent number: 7981771
    Abstract: The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in interconnects. A method includes forming an interconnect, forming a cap on the interconnect, and forming a plurality of holes in the cap to improve electromigration performance of the interconnect.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventor: Baozhen Li
  • Patent number: 7935630
    Abstract: A designing method of a semiconductor device having a first wire and a second wire with a plurality of vias includes determining a first life time change rate of the semiconductor device in response to a change in a number of via column, a second life time change rate of the semiconductor device in response to a change in a number of via row, reducing the number of via column according to a ratio based on the first life time change and the second life time change; and increasing the number of via row at least one.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Motonobu Sato
  • Patent number: 7915144
    Abstract: The present disclosure relates to methods of forming solid state thermal engines that provides a closely-spaced thermal tunneling gap between a hot and cold electrode. The effective gap may be on the order of one nanometer. In one embodiment, a via is etched through a first side of first and second substrates, and metal electrodes are attached to a second side of the first and second substrates. The second sides are opposite the first sides. The metal electrodes are mated by bonding the second side of the first substrate to the second side second substrate. The gap may be formed by applying a voltage greater than a threshold voltage across the mated electrodes.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: March 29, 2011
    Assignee: The Boeing Company
    Inventor: Minas H. Tanielian
  • Publication number: 20110065262
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 17, 2011
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Publication number: 20110001117
    Abstract: The present invention generally relates to nanotechnology and sub-microelectronic devices that can be used in circuitry, and, in particular, to nanoscale wires and other nanostructures able to encode data. One aspect of the present invention is directed to a device comprising an electrical crossbar array comprising at least two crossed wires at a cross point. In some cases, at least one of the crossed wires is a nanoscale wire, and in certain instances, at least one of the crossed wires is a nanoscale wire comprising a core and at least one shell surrounding the core. For instance, the core may comprise a crystal (e.g., crystalline silicon) and the shell may be at least partially amorphous (e.g., amorphous silicon). In certain embodiments, the cross point may exhibit intrinsic current rectification, or other electrical behaviors, and the cross point can be used as a memory device.
    Type: Application
    Filed: January 21, 2009
    Publication date: January 6, 2011
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yajie Dong, Wei Lu, Guihua Yu, Michael MeAlphine
  • Patent number: 7855098
    Abstract: A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: December 21, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Peter Kiesel, Oliver Schmidt
  • Publication number: 20100308302
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 7846816
    Abstract: Process for producing a multilayer structure that includes, within the depth thereof, a separating layer, including: producing an initial multilayer structure comprising a base substrate, a surface substrate and, between the base substrate and the surface substrate, an absorbent layer that can absorb a light power flux in at least one zone and a liquefiable intermediate layer that includes, in at least one zone, impurities having a coefficient of segregation relative to the material constituting this intermediate layer of less than unity; and in subjecting, for a defined time and in the form of at least one pulse, said initial structure to said light power flux, this flux being regulated so as to liquefy at least one portion of said intermediate layer under the effect of the propagation of the thermal energy, in such a way that it results, thanks to the initial presence of said impurities, in a modification of at least one characteristic and/or of at least one property of said intermediate layer arising from
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: December 7, 2010
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventor: Michel Bruel