Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.

Abstract: Process for producing a multilayer structure that includes, within the depth thereof, a separating layer, including: producing an initial multilayer structure comprising a base substrate, a surface substrate and, between the base substrate and the surface substrate, an absorbent layer that can absorb a light power flux in at least one zone and a liquefiable intermediate layer that includes, in at least one zone, impurities having a coefficient of segregation relative to the material constituting this intermediate layer of less than unity; and in subjecting, for a defined time and in the form of at least one pulse, said initial structure to said light power flux, this flux being regulated so as to liquefy at least one portion of said intermediate layer under the effect of the propagation of the thermal energy, in such a way that it results, thanks to the initial presence of said impurities, in a modification of at least one characteristic and/or of at least one property of said intermediate layer arising from

Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.

Abstract: A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified.

Abstract: According to one exemplary embodiment, a computer implemented method for detecting multiple failure modes in a set of electromigration failure data points includes sorting the data points by time to failure and dividing the data points to form first and second groups of data points to determine a first combination of first and second seed groups of data points providing an initial highest weighted R-square. The method further includes defining an intermediate group of data points shared between the first and second seed groups of data points and grouping the intermediate group of data points with the first and second seed groups of data points to determine a second combination of the first and second seed groups of data points providing a final highest weighted R-square. The initial highest weighted R-square is then compared to the final highest weighted R-square.

Abstract: A fin-shaped semiconductor region is formed on a substrate, and then the substrate is placed in a chamber. Then, an ignition gas is introduced into a chamber to thereby turn the ignition gas into a plasma, and then a process gas containing an impurity is introduced into the chamber to thereby turn the process gas into a plasma. Then, a bias voltage is applied to the substrate so as to dope the semiconductor region with the impurity after confirming attenuation of an amount of the ignition gas remaining in the chamber.

Abstract: A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.

Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.

Abstract: A method for manufacturing a thin film is provided. A substrate is loaded into a chamber. A first reaction gas and a second reaction gas are supplied into the chamber. The first reaction gas is dissociated to form crystalline nanoparticles. An amorphous material is inhibited from being formed on the substrate using the second reaction gas. Thereafter, a crystalline thin film is formed from the crystalline nanoparticles provided on the substrate.

Abstract: The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

Abstract: An imaging system is presented for imaging objects within a field of view of the system. The imaging system comprises an imaging lens arrangement, a light detector unit at a certain distance from the imaging lens arrangement, and a control unit connectable to the output of the detection unit. The imaging lens arrangement comprises an imaging lens and an optical element located in the vicinity of the lens aperture, said optical element introducing aperture coding by an array of regions differently affecting a phase of light incident thereon which are randomly distributed within the lens aperture, thereby generating an axially-dependent randomized phase distribution in the Optical Transfer Function (OTF) of the imaging system resulting in an extended depth of focus of the imaging system. The control unit is configured to decode the sampled output of the detection unit by using the random aperture coding to thereby extract 3D information of the objects in the field of view of the light detector unit.

Abstract: Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.

Abstract: The invention provides isolated NUE (nitrogen utilization efficiency) nucleic acids and their encoded proteins. The present invention provides methods and compositions relating to altering nitrogen utilization and/or uptake in plants. The invention further provides recombinant expression cassettes, host cells, and transgenic plants.

Abstract: A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink. The residual carrier sink is located at or adjacent to the semiconductor nanowire near the semiconductor junction and employs one or both of enhanced recombination and direct extraction of the residual carriers. The method includes providing a semiconductor nanowire, forming a semiconductor junction within the semiconductor nanowire, forming a residual carrier sink, and removing residual carriers from the semiconductor junction region using the residual carrier sink.

Abstract: A method of electroplating a metal into a plurality of channels within an insulating material includes mounting the material to a cathode; placing the cathode into an electroplating solution containing the metal; placing an anode into the electroplating solution; connecting the cathode and the anode to a power supply; controlling operation of the power supply to provide a beginning current density during deposition at the insulating material and initiating electroplating of the metal within the plurality of channels starting at one face of the insulating material; and controlling operation of the power supply to provide a final current density during deposition at the insulating material and ending electroplating of the metal within the plurality of channels at the other face of the insulating material.

Abstract: A method is shown for manufacturing silicon semiconductor nanowires on graphite cloth conducting substrates. The nanowires are grown on the substrate by first depositing a thin gold film on the graphite cloth using RF sputtering. The substrate structure is then exposed to dilute silane, resulting in a uniform coating of Si nanowires on the cloth. A method is also shown for growing calcified mineral phases on such nanowire surfaces as well as for the incorporation of anti-osteoporotic drugs or anti-bacterial agents onto the surface of the nanowires. Lastly, a method is shown for promoting the growth of bone-forming cells onto the nanowire materials by exposing specially treated nanowires to bone marrow cells.

Abstract: A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

Abstract: A method and apparatus for use in depositing electrical charge and/or nanoparticles is provided. A stamping process is used in which a stamp having a flexible layer such as a flexible semiconductor layer applies a charge pattern on a substrate. Other techniques include lithographic patterning, the use of pre-patterned dissimilar materials, deposition by ions or radiation, the use of differing work functions, the use of liquid phase materials. Deposition monitoring techniques and apparatuses are also provided.

Abstract: A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The deposition environment is chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50–500 ?.

Abstract: A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.

Abstract: Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

Abstract: The present invention is generally directed to various methods of using scatterometry for analysis of electromigration. In one illustrative embodiment, the method comprises forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive structures, forcing an electrical current through at least one of the conductive structures and performing scatterometric measurements of at least one conductive structure to detect a change in shape of at least a portion of the conductive structure. In further embodiments, the method comprises determining a susceptibility of at least one conductive structure to electromigration based upon the detected change in shape of the conductive structure.

Abstract: A p-type InGaAlN layer, an InGaAlN active layer, and an n-type InGaAlN layer each having a composition represented by (AlxGa1-x)yIn1-yN (0?x?1, 0?y?1) are formed on a sapphire substrate. In the as-grown state, Mg is bonded to hydrogen atoms in the p-type InGaAlN layer. Then, the back surface of the sapphire substrate is irradiated with a laser beam in a nitrogen atmosphere. The resistance of the p-type InGaAlN layer is reduced by removing hydrogen therefrom with irradiation with a weak laser beam. During the irradiation with the laser beam, the diffusion of a dopant in a multilayer portion is suppressed such that a dopant profile retains sharpness. It is also possible to separate the sapphire substrate from the multilayer portion by subsequently using an intense laser beam for irradiation.

Abstract: For testing for stress-migration failure of interconnect, an interconnect test structure is formed with a first feeder line coupled to a test line by a first no-flux structure, and with a second feeder line coupled to the test line by a second no-flux structure. A respective width of ea ch of the first and second feeder lines is greater than a width of the test line. A resistance meter and a timer measure a stress-migration life-time of the interconnect test structure with a current being continuously conducted through the interconnect test structure that is continuously heated to a predetermined temperature.

Abstract: A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a copper-alloy is deposited in the opening and the opening is filled with pure copper. The copper is planarized and a passivation layer is deposited. This passivation layer can be thinned over a fuse portion of the copper. The fuse portion can then be laser fused to form a crater in an area surrounding a blown copper fuse. Exposed portions of the pure copper can then be self-passivated by annealing the device.

Abstract: Electromigration testing is accelerated in the batch fabrication of semiconductor integrated circuits by forming test structures during the metal deposition phase of the batch fabrication process. Test metal lines can be formed on steps etched in a silicon oxide insulating layer with the vertical walls of the steps being greater than twice the thickness of the deposited metal whereby metal is not deposited on the side walls. Alternatively, test lines in the deposit metal layer can be formed by laser ablation or by ultrasound erosion. In another embodiment, electromigration tests are performed directly on the deposit metal layer through use of spaced elongated electrical contacts placed on the deposited metal layer surface. The elongated contacts can be wires of known diameter and length, or the elongated contacts can comprise a plurality of point contacts.

Abstract: A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer.

Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using electrostatic fields. A method includes applying an electrostatic field across a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).

Abstract: A heat capacity C1 is obtained by conducting two-dimensional thermal analysis simulation to the cross-section of a wiring. Next, based on one-dimensional approximate equation of &thgr;0=(Q0/2) (&lgr;·SC1)−½ along a wiring length direction, a wiring temperature rise &thgr;0 in the void is obtained. In the expression, &thgr;0 is a rise in wiring temperature in the void, Q0 is a thermal quantity of the void in the wiring, &lgr; is a heat conductivity of the wiring and S is a cross-sectional area of the wiring. The heat capacity C1 may be obtained from an expression C1=&lgr;′{(w/t)+(2.80/1.15) (h/t)0.222}. In the expression, W is wiring width, h is wiring thickness, t is substrate film thickness and &lgr;′ is the heat conductivity of the substrate film. By so obtaining, it is possible to shorten analysis time, to save the capacity of a memory and that of a disk for use in calculation, to obtain a simpler analysis model and to facilitate creating a mesh.

Abstract: A fabrication method for a silicon nitride read-only memory is described. A silicon nitride read-only memory and a grounding doped region are formed in the substrate. A contact is formed on the substrate. A metal protection line is also formed, wherein the metal protection line is electrically connected to the word line of the silicon nitride read-only memory. Moreover, the metal protection line is electrically connected the grounding doped region through the contact to conduct charges generated during the manufacturing process to the substrate. The resistance of the metal protection line is higher than that of the word line. A high current is then used to bum out the metal protection line after the formation of the metal interconnect on the substrate to ensure a normal function of the memory device.

Abstract: A first p-type silicon layer (3) is formed as a buried layer in a p-type single crystal silicon substrate (2), and an n-type silicon layer (4) is formed on the upper side of the silicon substrate (2). A second p-type silicon layer (5) for forming an opening is defined in the n-type silicon layer (4), and a metal protecting film (14) is formed on the upper side of the n-type silicon layer (4). An electrode layer (18) is formed on the rear side of the silicon substrate (2) via an oxide film (17). The electrode layer (18) and the silicon substrate (2) are electrically connected to each other via a connecting opening (17a) at portions aligned with the first p-type silicon layer (3). After a positive terminal and a negative terminal of a DC power source (V) are connected to the electrode layer (18) and to a counter electrode (11) respectively, a voltage is applied between the electrode layer (18) and the counter electrode (11) to carry out anodization.

Abstract: A exemplary method of fabricating a semiconductor laser device includes forming an electrode on each of a top surface and a bottom surface of a laminated structure comprised of semiconductor materials, then cleaving the laminated structure to form facets of a cavity, and next epitaxially growing a compound semiconductor on the facets of the cavity. Works involved in the cleavage and the epitaxial crystal growth are performed in a low oxygen and moisture concentration atmosphere, so that the occurrence of COD is suppressed in the fabricated semiconductor laser device.

Abstract: An apparatus for improving electromigration reliability and resistance of a single- or dual-damascene via includes an imperfect barrier formed at the bottom of the via, and a stronger barrier formed at all other portions of the via. The imperfect barrier allows for metal atoms, such as copper atoms, to flow therethrough when the electromigration force pushes the metal atoms against the barrier. That way, the metal atoms that are pushed away from the downstream side of the barrier are replaced by metal atoms that flow through the barrier from the upstream side of the barrier. The imperfect barrier may be formed by biasing a wafer, and having the atoms resputter from the bottom of the via and adhere to the sidewalls of the via. The imperfect barrier may also be formed by a two-layered barrier, where a first layer corresponds to a good step coverage, poor barrier, and where the second barrier corresponds to a poor step coverage, good barrier.

Abstract: A process and system for connecting a semiconductor chip to a substrate is provided. The process includes providing the substrate that is configured to receive the semiconductor chip that has a bonding pad. The substrate has a first side that is suited to be connected to the semiconductor chip and a second side that is opposite the first side. The process then includes designing a metallization bonding structure on the first side of the substrate. The metallization bonding structure has a first end, a second end, and a bend defined between the first end and the second end. Then, an oxide passivation layer is defined over the first side that includes the metallization bonding structure. A bonding via is then defined through the passivation layer. The bonding via is configured to be aligned with the bend of the metallization bonding structure.

Abstract: A semi conductor manufacturing process including uniform negative polarity wafer charging to remove or immobilize alkali ions such that the device becomes immune to their presence. The wafer is charged with a corona discharge at a 1MV/cm-2MV/cm bias field and low temperature (200.degree. C.-300.degree. C.) heating to bring mobile ions to the wafer's surface. Surface mobile ions are removed with a deionized (DI) water rinse or a standard sequential wafer wet cleaning step, immobilized with a normal gate (polysilicon) or metal contact formation step or both, thereby effectively removing mobile ions from the semiconductor structure.

Abstract: A method for measuring resistance changes is described to study electromigration induced failures in conductive patterns. This method can provide a basis for lifetime predictions based on low value failure criteria, i.e. small resistance changes in the conductive patterns in a limited period of time. Two essentially identical so-called test and reference structures are placed close to each other on the same substrate and submitted to at least one sequence of a stress period and a measurement period. During a stress period, a DC current with a high current density is applied to the test structure thereby enhancing electromigration, while substantially simultaneous an AC current is applied to the reference structure leading to the same amount of power dissipation in said reference structure as the amount of power dissipation in said test structure, introduced by said DC stress current.

Abstract: An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Abstract: An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Abstract: A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.

Abstract: A structure of a conductive line. The structure of a conductive line comprises a substrate with two conductive lines formed thereon. These two conductive lines are isolated by the formation of a dielectric layer. The conductive lines are electrically connected by a contact/via array. The contact/via array further comprises contact/via columns and contact/via rows made up of contacts/vias. Each contact/via column and contact/via row are added with a load resistor, so that the equivalent resistance of each contact/via is identical.

Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.