Fluid Growth Step With Preceding And Subsequent Diverse Operation Patents (Class 438/492)
  • Patent number: 10030318
    Abstract: A composite substrate includes a polycrystalline ceramic substrate, a silicon substrate directly bonded to the polycrystalline ceramic substrate, a seed crystal film formed on the silicon substrate by vapor phase process and made of a nitride of a group 13 element, and a gallium nitride crystal layer grown on the seed crystal film by flux method.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 24, 2018
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Yasunori Iwasaki, Takashi Yoshino
  • Patent number: 9887084
    Abstract: A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an opening in the insulating layer, the opening exposing a surface of the substrate. The method also includes growing a nanowire over the exposed surface of the substrate, the nanowire extending out of the opening away from the substrate, the nanowire including a second semiconductor material different from the first semiconductor material. The method also includes laterally growing the second semiconductor material on exposed sidewalls of the nanowire.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Georgios Vellianitis
  • Patent number: 9876088
    Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark Van Dal, Matthias Passlack, Martin Christopher Holland
  • Patent number: 9865730
    Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Shogo Mochizuki
  • Patent number: 9780137
    Abstract: Embodiments of mechanisms for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region formed in the substrate. The radiation-sensing region is operable to detect incident radiation that enters the substrate through the back surface. The radiation-sensing region further includes an epitaxial isolation feature formed in the substrate and adjacent to the radiation-sensing region. The radiation-sensing region and the epitaxial isolation feature have different doping polarities.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 9640533
    Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kwan-Yong Lim, Christopher Michael Prindle
  • Patent number: 9530775
    Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 27, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Xiuyu Cai, Ruilong Xie, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9409771
    Abstract: Disclosed is a structure having a superhydrophobic and amphiphilic (oleophilic) surface and a fabrication method thereof. A polymer surface body disclosed herein may include high aspect ratio nanostructures on a surface thereof, wherein an aspect ration of the high aspect ratio nanostructure is 1 to 100, and may include a hydrophobic thin film on the high aspect ratio nanostructure. A method of fabricating a polymer surface body disclosed herein may include performing a surface modification treatment on a polymer to form a high aspect ratio nanostructure having an aspect ration of 1 to 100, and forming a hydrophobic thin film on a surface containing the nanostructures.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: August 9, 2016
    Assignee: KOREA INSTITUTE OF SCIENCE AN TECHNOLOGY
    Inventors: Myoung-Woon Moon, Kwang Ryeol Lee, Bong Su Shin, Ho-Young Kim
  • Patent number: 9166005
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor body having a main surface. In a vertical cross-section which is substantially orthogonal to the main surface the semiconductor body includes a vertical trench, an n-type silicon semiconductor region, and two p-type silicon semiconductor regions each of which adjoins the n-type silicon semiconductor region and is arranged between the n-type silicon semiconductor region and the main surface. The vertical trench extends from the main surface at least partially into the n-type silicon semiconductor region and includes a compound semiconductor region which includes silicon and germanium and is arranged between the two p-type silicon semiconductor regions. The compound semiconductor region and the two p-type silicon semiconductor regions include n-type dopants and p-type dopants.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Hans Weber, Roman Knoefler, Franz Hirler
  • Publication number: 20150147873
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: carrying a substrate, which has a Ge-containing film on at least a portion of a surface thereof, into a process chamber; heating an inside of the process chamber, into which the substrate is carried, to a first process temperature; and terminating a surface of the Ge-containing film, which is exposed at a portion of the surface of the substrate, by Si by supplying at least a Si-containing gas to the inside of the process chamber heated to the first process temperature.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC
    Inventors: Atsushi MORIYA, Kensuke HAGA, Kazuhiro YUASA, Kaichiro MINAMI
  • Patent number: 9040397
    Abstract: There is provided a method for forming a graphene layer. The method includes forming an article that comprises a carbon-containing self-assembled monolayer (SAM). A layer of nickel is deposited on the SAM. The article is heated in a reducing atmosphere and coolded. The heating and cooling steps are carried out so as to convert the SAM to a graphene layer.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: May 26, 2015
    Assignee: LGS INNOVATIONS LLC
    Inventor: Ashok J. Maliakal
  • Patent number: 9034739
    Abstract: A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a second mask layer over the first mask layer; annealing the second mask layer to form islands; etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars; and growing semiconductor material between the pillars and then over the tops of the pillars.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 19, 2015
    Assignee: Seren Photonics Limited
    Inventor: Tao Wang
  • Publication number: 20150126009
    Abstract: A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material.
    Type: Application
    Filed: January 6, 2015
    Publication date: May 7, 2015
    Inventors: KANGGUO CHENG, BRUCE B. DORIS, POUYA HASHEMI, ALI KHAKIFIROOZ
  • Patent number: 9023719
    Abstract: A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: May 5, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Jayavel Pachamuthu, Johann Alsmeier, Raghuveer S. Makala, Yao-Sheng Lee
  • Publication number: 20150102465
    Abstract: Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Inventors: Robert Chen, James S. Harris, JR., Suyog Gupta
  • Patent number: 9006062
    Abstract: A method of manufacturing a semiconductor device includes providing a doped layer containing a first dopant of a first conductivity type and forming a counter-doped zone in the doped layer in an edge area surrounding an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type which is the opposite of the first conductivity type. A concentration of the second dopant is at least 20% and at most 100% of the concentration of the first dopant.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Anton Mauder, Franz Hirler
  • Patent number: 9006083
    Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 14, 2015
    Inventor: Ananda H. Kumar
  • Patent number: 8993418
    Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 31, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Vincent Destefanis, Nicolas Loubet
  • Patent number: 8986464
    Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Yukimune Watanabe
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Publication number: 20150053263
    Abstract: The present invention provides a method for producing a semiconductor laminate including a substrate having formed thereon a silicon layer with small surface unevenness and high continuity. The method of the present invention for producing a semiconductor laminate having a substrate 10 and a sintered silicon particle layer 5 on the substrate includes (a) coating a silicon particle dispersion containing a dispersion medium and silicon particles dispersed in the dispersion medium, on a substrate 10 to form a silicon particle dispersion layer 1, (b) drying the silicon particle dispersion layer 1 to form a green silicon particle layer 2, (c) stacking a light-transmitting layer 3 on the green silicon particle layer, and (d) irradiating the green silicon particle layer 2 with light through the light-transmitting layer 3 to sinter the silicon particles constituting the green silicon particle layer 2, and thereby form a sintered silicon particle layer 5.
    Type: Application
    Filed: March 29, 2013
    Publication date: February 26, 2015
    Applicant: TEIJIN LIMITED
    Inventors: Tetsuya Imamura, Yuka Tomizawa, Yoshinori Ikeda
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8946018
    Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi
  • Publication number: 20150008454
    Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation ? of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation ? of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventor: Keiji ISHIBASHI
  • Publication number: 20150001588
    Abstract: A trench 107 is coated and sealed with a cap film 111 from above an amorphous or polycrystalline InP film 109A buried in the trench 107. Next, a monocrystalline InP film 109B is formed by monocrystallizing the InP film 109A, with a Si (001) plane of the bottom of the trench 107 as a seed crystal plane, by melting InP by heating a Si wafer W at or above a melting point of InP and then solidifying InP by cooling InP.
    Type: Application
    Filed: February 5, 2013
    Publication date: January 1, 2015
    Applicant: Tokyo Electron Limited
    Inventors: Isao Gunji, Yusaku Kashiwagi, Masakazu Sugiyama
  • Publication number: 20140367642
    Abstract: Provided is a process for preparing graphene on a SiC substrate, based on metal film-assisted annealing, comprising the following steps: subjecting a SiC substrate to a standard cleaning process; placing the cleaned SiC substrate into a quartz tube and heating the quartz tube up to a temperature of 750 to 1150° C.; introducing CCl4vapor into the quartz tube to react with SiC for a period of 20 to 100 minutes so as to generate a double-layered carbon film, wherein the CCl4 vapor is carried by Ar gas; forming a metal film with a thickness of 350 to 600 nm on a Si substrate by electron beam deposition; placing the obtained double-layered carbon film sample onto the metal film; subsequently annealing them in an Ar atmosphere at a temperature of 900 to 1100° C. for 10-30 minutes so as to reconstitute the double-layered carbon film into double-layered graphene; and removing the metal film from the double-layered graphene, thereby obtaining double-layered graphene.
    Type: Application
    Filed: September 3, 2012
    Publication date: December 18, 2014
    Applicant: Xidian University
    Inventors: Hui Guo, Keji Zhang, Yuming Zhang, Pengfei Deng, Tianmin Lei
  • Publication number: 20140342522
    Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Yu-Hung Cheng, Yi-Hung Lin, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 8890104
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
  • Patent number: 8890247
    Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahjerdi
  • Publication number: 20140335683
    Abstract: A method for producing a gallium nitride layer using a pulsed laser is disclosed. The method includes (1) providing a substrate; (2) forming a zinc oxide layer on the substrate; and (3) forming a gallium nitride thin film on the zinc oxide layer by pulsed laser deposition (PLD).
    Type: Application
    Filed: September 9, 2013
    Publication date: November 13, 2014
    Applicant: National Taiwan University
    Inventors: CHING-FUH LIN, Chun-Wei Ku, Hao-Yu Wu
  • Patent number: 8883598
    Abstract: Semiconductor devices and methods of forming the same. The method includes providing a semiconductor substrate having a channel layer over the substrate. A capping layer including silicon and having a first thickness is formed over the channel layer. The capping layer is partially oxidized to form an oxidized portion of the capping layer. The oxidized portion of the capping layer is removed to form a thinned capping layer having a second thickness less than the first thickness.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Ting Chu, Shih-Hsun Chang, Pang-Yen Tsai
  • Publication number: 20140329376
    Abstract: Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A <111> surface may be formed on a substrate and a Group III-V material may be grown from the <111> surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure.
    Type: Application
    Filed: April 25, 2014
    Publication date: November 6, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Errol Antonio C. SANCHEZ, Xinyu BAO, Wonseok LEE, David Keith CARLSON, Zhiyuan YE
  • Patent number: 8866227
    Abstract: A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20140299968
    Abstract: A method of making a semiconductor device comprises : providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a second mask layer over the first mask layer; annealing the second mask layer to form islands; etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars; and growing semiconductor material between the pillars and then over the tops of the pillars.
    Type: Application
    Filed: February 29, 2012
    Publication date: October 9, 2014
    Applicant: SEREN PHOTONICS LIMITED
    Inventor: Tao Wang
  • Patent number: 8853064
    Abstract: The present invention is directed to a method of manufacturing a substrate, which includes loading a base substrate into a reaction furnace; forming a buffer layer on the base substrate; forming a separation layer on the buffer layer; forming a semiconductor layer on the separation layer at least two; and separating the semiconductor layer from the base substrate via the separation layer through natural cooling by unloading the base substrate from the reaction furnace.
    Type: Grant
    Filed: October 21, 2012
    Date of Patent: October 7, 2014
    Assignee: Lumigntech Co., Ltd.
    Inventors: Hae Yong Lee, Young Jun Choi, Jin Hun Kim, Hyun soo Jang, Hea Kon Oh, Hyun Hee Hwang
  • Patent number: 8847363
    Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Publication number: 20140285980
    Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
    Type: Application
    Filed: April 13, 2012
    Publication date: September 25, 2014
    Inventors: Annalisa Cappellani, Van H. Le, Glenn A. Glass, Kelin J. Kuhn, Stephen M. Cea
  • Patent number: 8841207
    Abstract: Substrates for electronic device fabrication and methods thereof. A reusable substrate with at least a plurality of grooves for electronic device fabrication includes a substrate body made of one or more substrate materials and including a top planar surface, the top planar surface being divided into a plurality of planer regions by the plurality of grooves, the plurality of grooves including a plurality of bottom planar surfaces. Each of the plurality of grooves includes a bottom planar surface and two side surfaces, the bottom planar surface being selected from the plurality of bottom planar surfaces, the two side surfaces being in contact with the top surface and the bottom surface. The bottom planar surface is associated with a groove width from one of the two side surfaces to the other of the two side surfaces, the groove width ranging from 0.1 ?m to 5 mm.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: September 23, 2014
    Assignee: Lux Material Co., Ltd.
    Inventor: Baoguo Zhang
  • Patent number: 8815712
    Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tien Wan, You-Ru Lin, Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20140220751
    Abstract: A method includes recessing a portion of a semiconductor substrate between opposite isolation regions to form a recess. After the step of recessing, the portion of the semiconductor substrate includes a top surface. The top surface includes a flat surface, and a slant surface having a (111) surface plane. The slant surface has a bottom edge connected to the flat surface, and a top edge connected to one of the isolation regions. The method further includes performing an epitaxy to grow a semiconductor material in the recess, wherein the semiconductor material is grown from the flat surface and the slant surface, and performing an annealing on the semiconductor material.
    Type: Application
    Filed: March 11, 2013
    Publication date: August 7, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8779423
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 15, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Company, Limited
    Inventors: Jiquan Liu, Shengan Xiao, Wei Ji
  • Publication number: 20140193967
    Abstract: In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 10, 2014
    Applicants: Kookje Electric Korea Co., Ltd., Samsung Electronics Co., Ltd.
    Inventors: Sung-Ho KANG, Bong-Jin KUH, Yong-Kyu JOO, Sung-Ho HEO, Hee-Seok KIM, Yong-Sung PARK
  • Publication number: 20140191283
    Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20140179043
    Abstract: A method of fabricating a semiconductor device, the method including: forming a first mask pattern including a masking region and an open region on a substrate; forming a sacrificial layer to cover the substrate and the first mask pattern; patterning the sacrificial layer to form a seed layer and to expose the first mask pattern; forming a second mask pattern on the exposed first mask pattern; forming an epitaxial layer on the seed layer and the second mask pattern, and forming a void between the second mask pattern and the epitaxial layer; and separating the substrate from the epitaxial layer.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 26, 2014
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Hwa Mok Kim, Kyu Ho Lee, Chang Hoon Kim, Daewoong Suh, Chi Hyun In, Dae Seok Park, Jong Hyeon Chae
  • Publication number: 20140170840
    Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Publication number: 20140167086
    Abstract: An epitaxial wafer having a void for separation of a substrate and a semiconductor device fabricated using the same. The epitaxial wafer includes a substrate, a mask pattern disposed on the substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern. The epitaxial layer includes a void disposed on the masking region. The epitaxial layer can be separated from the growth substrate by applying chemical lift-off or stress lift-off, at the void.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Min JANG, Kyu-Ho LEE, Chang Suk HAN, Hwa Mok KIM, Daewoong SUH, Chi Hyun IN, Jong Hyeon CHAE
  • Patent number: 8729672
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 20, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Publication number: 20140131831
    Abstract: A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Andy C. Wei, Konstantin Korablev, Francis Tambwe
  • Patent number: 8703551
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Andreas Ott
  • Patent number: 8691672
    Abstract: A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: April 8, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Themistokles Afentakis, Karen Yuri Nishimura