Formation Of Semiconductive Active Region On Any Substrate (e.g., Fluid Growth, Deposition) Patents (Class 438/478)
  • Patent number: 11451189
    Abstract: The method of the present invention improves mechanical integrity of a crystalline silicon solar cell having an exposed layer of n-type silicon. A solution of electrically-conductive nanowires in an inert liquid is sprayed onto the exposed layer in order to form a grid pattern of the nanowires on the exposed layer after the inert liquid dries or evaporates.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: September 20, 2022
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Edward E. Foos, Richard Jason Jouet
  • Patent number: 11450737
    Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 20, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yeon Goog Sung
  • Patent number: 11443919
    Abstract: Systems and methods of using pulsed RF plasma to form amorphous and microcrystalline films are discussed herein. Methods of forming films can include (a) forming a plasma in a process chamber from a film precursor and (b) pulsing an RF power source to cause a duty cycle on time (TON) of a duty cycle of a pulse generated by the RF power source to be less than about 20% of a total cycle time (TTOT) of the duty cycle to form the film. The methods can further include (c) depositing a first film interlayer on a substrate in the process chamber; (d) subsequent to (c), purging the process chamber; and (e) subsequent to (d), introducing a hydrogen plasma to the process chamber. Further in the method, (b)-(e) are repeated to form a film. The film can have an in-film hydrogen content of less than about 10%.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: September 13, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Krishna Nittala, Diwakar N. Kedlaya, Karthik Janakiraman, Yi Yang, Rui Cheng
  • Patent number: 11430862
    Abstract: A semiconductor device has an active region through which current flows and a termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer in the active region, a first parallel pn structure is provided including first columns of the first conductivity type and second columns of a second conductivity type disposed repeatedly alternating one another in a plane parallel to the front surface. In the termination structure region, a second parallel pn structure is provided including third columns of the first conductivity type and fourth columns of the second conductivity type disposed repeatedly alternating one another. On a surface of the second parallel pn structure, a first semiconductor region of the second conductivity type is provided including plural regions apart from one another.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 30, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Toshiaki Sakata
  • Patent number: 11430907
    Abstract: In an embodiment a method includes providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region, directly applying a nucleation layer of oxygen-containing AlN to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 30, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Werner Bergbauer, Thomas Lehnhardt, Jürgen Off, Joachim Hertkorn
  • Patent number: 11417522
    Abstract: The present invention discloses a two-dimensional AlN material and its preparation method and application, wherein the preparation method comprises the following steps: (1) selecting a substrate and its crystal orientation; (2) cleaning the surface of the substrate; (3) transferring a graphene layer to the substrate layer; (4) annealing the substrate; (5) using the MOCVD process to introduce H2 to open the graphene layer and passivate the surface of the substrate; and (6) using the MOCVD process to grow a two-dimensional AlN layer. The preparation method of the present invention has the advantages that the process is simple, time saving and efficient. Besides, the two-dimensional AlN material prepared by the present invention can be widely used in HEMT devices, deep ultraviolet detectors or deep ultraviolet LEDs, and other fields.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 16, 2022
    Assignee: South China University of Technology
    Inventors: Wenliang Wang, Guoqiang Li, Yulin Zheng
  • Patent number: 11417794
    Abstract: A growth mask layer is formed over a semiconductor material layer on a substrate. Optionally, a patterned hard mask layer can be formed over the growth mask layer. A nano-imprint lithography (NIL) resist layer is applied, and is imprinted with a pattern of recesses by stamping. The pattern in the NIL resist layer through the growth mask layer to provide a patterned growth mask layer with clusters of openings therein. If a patterned hard mask layer is employed, the patterned hard mask can prevent transfer of the pattern in the area covered by the patterned hard mask layer. Semiconductor material portions, such as nanowires can be formed in a cluster configuration through the clusters of openings in the patterned growth mask layer. Alignment marks can be formed concurrently with formation of semiconductor material portions by employing nano-imprint lithography.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 16, 2022
    Assignee: NANOSYS, INC.
    Inventors: Zulal Tezcan Ozel, Tsun Lau, Benjamin Leung, Fariba Danesh
  • Patent number: 11393672
    Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Damir Fazil
  • Patent number: 11393685
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Bo Su, Shiliang Ji, Erhu Zheng, Yan Wang, Haiyang Zhang
  • Patent number: 11374149
    Abstract: Provided are a method of manufacturing a display device and a source substrate structure. The method of manufacturing the display device includes holding a light-emitting element on a source substrate that passes laser light of a certain wavelength therethrough, the holding being performed by a release layer between the source substrate and the light-emitting element, forming an adhesive layer on a driving substrate on which a driving substrate-side electrode is formed, moving the light-emitting element to a surface of the adhesive layer on the driving substrate from the source substrate by irradiating laser light of the certain wavelength to the release layer through the source substrate, and adhering the moved light-emitting element to the driving substrate by using the adhesive layer, and the release layer comprises a resin material with a thickness that is greater than or equal to 0.1 ?m and is less than or equal to 0.5 ?m.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 28, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Takashi Takagi
  • Patent number: 11342192
    Abstract: A technique for making etching amounts uniform in selectively etching SiGe layers formed on a wafer with respect to at least one of an Si layer, an SiO2 layer, and an SiN layer is provided. In an etching process where SiGe layers in a wafer W in which the SiGe layers and Si layers are alternately stacked and exposed in a recess are removed by side etching, ClF3 gas and HF gas are simultaneously supplied to the wafer W. Accordingly, it is possible to make the etching rates for respective SiGe layers uniform, and it becomes possible to obtain a uniform etching amount for respective SiGe layers.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 24, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobuhiro Takahashi, Yasuo Asada, Junichiro Matsunaga
  • Patent number: 11339417
    Abstract: Systems, methods, and devices are described herein for identifying, monitoring, isolating, or selecting a cell having a predefined characteristic in a mixed population of cells utilizing a combination of any one or more of iDEP, a region of localized field enhancement, a variable frequency electric field, a wide bandwidth amplifier, and/or an imaging apparatus.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 24, 2022
    Assignee: University of Virginia Patent Foundation
    Inventors: Nathan Swami, Yi-Hsuan Su, Cirle Alcantara Warren, Ali Rohani, Vahid Farmehini
  • Patent number: 11299821
    Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber; a substrate holder having a holding wall capable holding an outer periphery of the substrate; a process gas supply part provided above the reaction chamber, the process gas supply part having a first region supplying a first process gas and a second region around the first region supplying a second process gas having a carbon/silicon atomic ratio higher than that of the first process gas, an inner peripheral diameter of the second region being 75% or more and 130% or less of a diameter of the holding wall; a sidewall provided between the process gas supply part and the substrate holder, an inner peripheral diameter of the sidewall being 110% or more and 200% or less of an outer peripheral diameter of the second region; a first heater; a second heater; and a rotation driver.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: April 12, 2022
    Assignee: NuFlare Technology, Inc.
    Inventors: Yoshiaki Daigo, Akio Ishiguro, Hideki Ito
  • Patent number: 11302824
    Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
  • Patent number: 11296103
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Kunal Shrotri, Matthew Thorum
  • Patent number: 11296210
    Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-Bae Kim, Seung Hyun Song, Young Chai Jung
  • Patent number: 11276805
    Abstract: A method includes depositing a layer comprising a photoinitiator and a curable material onto a surface and applying a nanoimprint mold on the layer of curable material to form a mesh comprising intersecting walls defining cavities. After applying the nanoimprint mold, the mesh is illuminated with light causing decarboxylation of the photoinitator to initiate curing of the curable material. After curing the curable material, the nanoimprint mold is removed and a wavelength converting material is deposited in the cavities to form an array of wavelength converting pixels.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 15, 2022
    Assignee: Lumileds LLC
    Inventors: Danielle Russell Chamberlin, Erik Roeling, Daniel Bernardo Roitman, Kentaro Shimizu
  • Patent number: 11264536
    Abstract: A composition of matter comprising: a graphitic substrate optionally carried on a support, a seed layer having a thickness of no more than 50 nm deposited directly on top of said substrate, opposite any support; and an oxide or nitride masking layer e directly on top of said seed layer; wherein a plurality of holes are present through said seed layer and through said masking layer to C said graphitic substrate; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowres or nanopyramids comprising at least one semiconducting group III-V compound.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 1, 2022
    Assignees: CRAYONANO AS, NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY (NTNU)
    Inventors: Dong Chul Kim, Ida Marie E. Høiaas, Carl Philip J. Heimdal, Bjørn Ove M. Fimland, Helge Weman
  • Patent number: 11257671
    Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Andrew Joseph Kelly
  • Patent number: 11222756
    Abstract: Graphene photodetectors capable of operating in the sub-bandgap region relative to the bandgap of semiconductor nanoparticles, as well as methods of manufacturing the same, are provided. A photodetector can include a layer of graphene, a layer of semiconductor nanoparticles, a dielectric layer, a supporting medium, and a packaging layer. The semiconductor nanoparticles can be semiconductors with bandgaps larger than the energy of photons meant to be detected.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: January 11, 2022
    Assignee: The University of Hong Kong
    Inventors: Jinyao Tang, Ze Xiong, Jiawei Chen
  • Patent number: 11208328
    Abstract: A method for carbon nanotube purification, preferably including: providing carbon nanotubes; depositing a mask; and/or selectively removing a portion of the mask; and optionally including removing a subset of the carbon nanotubes and/or removing the remaining mask.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 28, 2021
    Assignee: Aligned Carbon, Inc.
    Inventors: John Provine, Cara Beasley, Gregory Pitner
  • Patent number: 11198612
    Abstract: A method for manufacturing graphene having a wrinkle pattern is provided. The method includes forming a wrinkle providing layer having a first thermal expansion coefficient on one surface of a graphene layer, forming a substrate having a second thermal expansion coefficient on one surface of the wrinkle providing layer, and performing a heat treatment to form wrinkles on the wrinkle providing layer by a difference between the first and second thermal expansion coefficients, thereby forming wrinkle patterns on the graphene layer.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 14, 2021
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Wanjun Park, Sungwoo Chun
  • Patent number: 11186922
    Abstract: An apparatus for producing a Group-III nitride semiconductor crystal includes a raw material reaction chamber, a raw material reactor which is provided in the raw material reaction chamber and configured to generate a Group-III element-containing gas, a board-holding member configured to hold a board in the raw material reaction chamber, a raw material nozzle configured to spray the Group-III element-containing gas toward the board, a nitrogen source nozzle configured to spray a nitrogen element-containing gas toward the board, in which, in a side view seen in a direction perpendicular to a vertical direction, a spray direction of the nitrogen source nozzle intersects with a spray direction of the raw material nozzle before the board, and a mixing part in which the Group-III element-containing gas and the nitrogen element-containing gas are mixed together is formed around the intersection as a center, a heater, and a rotation mechanism.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 30, 2021
    Assignee: PANASONIC CORPORATION
    Inventors: Masayuki Hoteida, Shunichi Matsuno, Junichi Takino
  • Patent number: 11183563
    Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 23, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fong Lin, Cheng-Tao Chou
  • Patent number: 11183382
    Abstract: There is provided a technique that includes: (a) forming a first film containing boron and at least first bonds selected from the group of Si—C bonds and Si—N bonds on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a boron-containing pseudo-catalyst gas to the substrate; and supplying a first precursor gas containing at least the first bonds selected from the group of the Si—C bonds and the Si—N bonds to the substrate; (b) modifying the first film to a second film by supplying a gas containing hydrogen and oxygen to the substrate; and (c) modifying the second film to a third film by performing a thermal annealing process to the second film.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: November 23, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Kimihiko Nakatani, Yoshitomo Hashimoto
  • Patent number: 11177278
    Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Lifang Xu
  • Patent number: 11167262
    Abstract: Disclosed are amorphous nanostructure and methods of making amorphous nanostructure. The amorphous nanostructure has a transition metal and a halogen element in the main chain, and the transition metal has an oxidation number of +1. In addition, the inorganic polymer forming the amorphous nanostructure forms hydrogen bonding with an adjacent inorganic polymer. The side chain of the inorganic polymer for hydrogen bonding has hydrogen and elements for hydrogen bonding. Through this, various characteristics can be confirmed.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 9, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Ka Hyun Hur, Min Seok Kim
  • Patent number: 11152205
    Abstract: A silicon chalcogenate precursor comprising the chemical formula of Si(XR1)nR24-n, where X is sulfur, selenium, or tellurium, R1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each R2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy A. Quick, Sumeet C. Pandey, Stefan Uhlenbrock
  • Patent number: 11133386
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu
  • Patent number: 11127637
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 11087982
    Abstract: The present disclosure provides a method and system for fabricating a semiconductor device. The method and system of the present disclosure, after obtaining the polysilicon layer, first form the protective oxide layer on the surface of the polysilicon layer, and then etch the protective oxide layer and the protrusions on the surface of the polysilicon layer with the buffered oxide etchant based on controllability of the buffered oxide etchant, thereby reducing the protrusions on the surface of the polysilicon layer, while well protecting the surface of the polysilicon layer. Therefore, the technical problem of surface roughness in the existing polysilicon layers is solved.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 10, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yuanming Meng, Yu Yan
  • Patent number: 11081344
    Abstract: Provided is a method for manufacturing a semiconductor substrate including: preparing a semiconductor substrate having a front surface on which an epitaxial layer has been formed; and forming a fracture layer on a rear surface of the semiconductor substrate before forming elements on the epitaxial layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 3, 2021
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Atsushi Fukugawa, Michiaki Murata
  • Patent number: 11075266
    Abstract: Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praveen Joseph, Tao Li, Indira Seshadri, Ekmini A. De Silva
  • Patent number: 11075114
    Abstract: There is provided a technique which includes (a) forming a seed layer on a substrate by supplying a first process gas to the substrate at a first temperature, (b) forming a film on the seed layer by supplying a second process gas to the substrate at a second temperature, and (c) annealing the seed layer and the film at a third temperature, wherein at least one selected from the group of a crystal grain size and a surface roughness of the film after performing the annealing in (c) is adjusted by controlling a thickness of the seed layer formed in (a).
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 27, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Masahito Kitamura
  • Patent number: 11056389
    Abstract: A method for manufacturing a group III nitride semiconductor without causing adverse effects on device characteristics includes: preparing a group III nitride substrate having a first group III nitride layer and a second group III nitride layer laminated in this order from a back-surface side to a front-surface side, the first group III nitride layer being a layer having a transmittance of 60% or more for a predetermined wavelength of 400 nm to 700 nm, the second group III nitride layer being a layer provided on the first group III nitride layer and containing impurity oxygen in a concentration of 1×1020 cm?3 or more and having a transmittance of 0.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 6, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ayako Iwasawa, Yoshio Okayama, Takatoshi Okamoto
  • Patent number: 11029213
    Abstract: Devices including graphene quantum dots yield extremely high performance THz bolometers, by measuring the current of hot electrons formed in the graphene source and drain electrodes of the device and propagating through the graphene quantum dot connected thereto. Devices may also include additional materials such as MoS2, as well as one or more gate electrodes to alter performance as needed.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 8, 2021
    Assignees: Georgetown University, The Government of the United States, as Repressented by the Secretary of the Navy
    Inventors: Abdel El Fatimy, Paola Barbara, David Kurt Gaskill
  • Patent number: 11011391
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 18, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Fong Lin, Yu-Chieh Chou
  • Patent number: 11004745
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 11004984
    Abstract: Embodiments of the present invention are directed to forming a nanosheet field effect transistor (FET) having a low resistivity region that reduces the nanosheet external resistance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. An inner layer is formed over nanosheets in the nanosheet stack. The inner layer includes a first material having a first melting point. An outer layer is formed over the inner layer. The outer layer includes a second material having a second melting point that is lower than the first melting point. A heavily doped region is formed on a surface of the outer layer and the nanosheet stack is annealed at a temperature between the first melting point and the second melting point such that the outer layer is selectively liquified, distributing the dopants throughout the outer layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Oleg Gluschenkov, Lan Yu, Ruilong Xie
  • Patent number: 10995267
    Abstract: Disclosed herein are methods and compositions of nanoparticles having one or more layers of organic coating. In some embodiments, a nanoparticle comprises a core/shell nanocrystal comprising a first coating layer comprising a plurality of organic molecules, and a second organic coating layer surrounding the first organic coating layer, wherein the second coating layer comprises a plurality of organic molecules. Further, the organic molecules of the second coating layer are intercalated between the organic molecules of the first coating layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 4, 2021
    Assignee: CRYSTALPLEX CORPORATION
    Inventor: Matthew W. Bootman
  • Patent number: 10985021
    Abstract: A gallium nitride (GaN) substrate is injected with magnesium as a p-type dopant. The GaN substrate undergoes preheating through irradiation with light from halogen lamps in an atmosphere containing nitrogen and hydrogen, and further undergoes heating to a high temperature for a super-short time through irradiation with flashes of light from flash lamps. Heating the GaN substrate in the atmosphere containing nitrogen and hydrogen complements removed nitrogen, thus preventing nitrogen shortage. Such a heating process also enables heat treatment while supplying hydrogen to the GaN substrate. The heating process further enables crystal defects in the GaN substrate to be recovered. With these effects, the p-type dopant injected into the GaN substrate is activated with high efficiency.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 20, 2021
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Hideaki Tanimura, Takahiro Yamada, Shinichi Kato, Takayuki Aoyama
  • Patent number: 10978298
    Abstract: Disclosed is a process for producing semiconductor nanowires having a diameter or thickness from 2 nm to 100 nm, the process comprising: (A) preparing a semiconductor material particulate having a size from 50 nm to 500 ?m, selected from Ga, In, Ge, Sn, Pb, P, As, Sb, Bi, Te, a combination thereof, a compound thereof, or a combination thereof with Si; (B) depositing a catalytic metal, in the form of nanoparticles having a size from 1 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the semiconductor material particulate to form a catalyst metal-coated semiconductor material; and (C) exposing the catalyst metal-coated semiconductor material to a high temperature environment, from 100° C. to 2,500° C., for a period of time sufficient to enable a catalytic metal-assisted growth of multiple semiconductor nanowires from the particulate.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 13, 2021
    Assignee: Global Graphene Group, Inc.
    Inventor: Bor Z. Jang
  • Patent number: 10971367
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhaoxu Shen, Duohui Bei
  • Patent number: 10947638
    Abstract: An underlying substrate including a seed crystal layer of a group 13 nitride, wherein projections and recesses repeatedly appear in stripe shapes at a principal surface of the seed crystal layer, and the projections have a level difference of 0.3 to 40 ?m and a width of 5 to 100 ?m, and the recesses have a bottom thickness of 2 ?m or more and a width of 50 to 500 ?m.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: March 16, 2021
    Inventors: Takayuki Hirao, Makoto Iwai, Katsuhiro Imai, Takashi Yoshino
  • Patent number: 10943925
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien
  • Patent number: 10930497
    Abstract: A method for producing a semiconductor substrate and a semiconductor substrate for use in epitaxial methods of a semiconductor material are described. The semiconductor substrate includes a support slice, an intermediate layer situated on the support slice, and an active layer situated on the intermediate layer. The intermediate layer includes a material which has a reduced viscosity or flows when the semiconductor substrate is used in an epitaxial method in order to enable at least a partial adaptation of a crystal lattice of the active layer to a crystal lattice of the semiconductor material at the transition between the active layer and the semiconductor material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 23, 2021
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventor: Ralf Lerner
  • Patent number: 10886123
    Abstract: A method for forming a metal nitride film with good film closure at low temperatures is disclosed. The method may comprise utilizing plasma to form NH and NH2 radicals to allow for the formation of the metal nitride at low temperatures. The method may also comprise flowing an etch gas to result in an amorphous film with uniform thickness. The method may also comprise flowing an alkyl hydrazine to inhibit three-dimensional island growth of the metal nitride film.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 5, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Petri Raisanen, Moataz Bellah Mousa, Peng-Fu Hsu
  • Patent number: 10879469
    Abstract: A semiconductor device includes a substrate, a nanotube structure, and a gate structure. The nanotube structure is disposed over the substrate. The nanotube structure includes a semiconducting carbon nanotube (s-CNT) and a first insulating nanotube. The first insulating nanotube has an inert surface on the s-CNT. The gate structure includes a first metallic carbon nanotube (m-CNT) over the nanotube structure.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Timothy Vasen
  • Patent number: 10847350
    Abstract: A heat treatment apparatus includes: a rotation table installed in a vacuum container, the rotation table mounting a substrate in a mounting area formed in one surface side of the rotation table and revolving the substrate; a heater that heats the rotation table; a plasma processing part that generates a plasma in a plasma generation region, which is formed in the one surface side of the rotation table at a region through which the substrate passes, and processes the substrate; a temperature measurement terminal installed in the rotation table at a region, which passes through a position facing the plasma generation region when the rotation table is rotated, the temperature measurement terminal outputting a temperature measurement result of the rotation table as an electric signal; and a conductive plasma shield part installed to cover the temperature measurement terminal when viewed from the plasma generation region.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Soichi Kanno
  • Patent number: 10811351
    Abstract: A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventor: Elliot N. Tan