Formation Of Semiconductive Active Region On Any Substrate (e.g., Fluid Growth, Deposition) Patents (Class 438/478)
  • Patent number: 11075266
    Abstract: Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praveen Joseph, Tao Li, Indira Seshadri, Ekmini A. De Silva
  • Patent number: 11075114
    Abstract: There is provided a technique which includes (a) forming a seed layer on a substrate by supplying a first process gas to the substrate at a first temperature, (b) forming a film on the seed layer by supplying a second process gas to the substrate at a second temperature, and (c) annealing the seed layer and the film at a third temperature, wherein at least one selected from the group of a crystal grain size and a surface roughness of the film after performing the annealing in (c) is adjusted by controlling a thickness of the seed layer formed in (a).
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 27, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Masahito Kitamura
  • Patent number: 11056389
    Abstract: A method for manufacturing a group III nitride semiconductor without causing adverse effects on device characteristics includes: preparing a group III nitride substrate having a first group III nitride layer and a second group III nitride layer laminated in this order from a back-surface side to a front-surface side, the first group III nitride layer being a layer having a transmittance of 60% or more for a predetermined wavelength of 400 nm to 700 nm, the second group III nitride layer being a layer provided on the first group III nitride layer and containing impurity oxygen in a concentration of 1×1020 cm?3 or more and having a transmittance of 0.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 6, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ayako Iwasawa, Yoshio Okayama, Takatoshi Okamoto
  • Patent number: 11029213
    Abstract: Devices including graphene quantum dots yield extremely high performance THz bolometers, by measuring the current of hot electrons formed in the graphene source and drain electrodes of the device and propagating through the graphene quantum dot connected thereto. Devices may also include additional materials such as MoS2, as well as one or more gate electrodes to alter performance as needed.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 8, 2021
    Assignees: Georgetown University, The Government of the United States, as Repressented by the Secretary of the Navy
    Inventors: Abdel El Fatimy, Paola Barbara, David Kurt Gaskill
  • Patent number: 11011391
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 18, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Fong Lin, Yu-Chieh Chou
  • Patent number: 11004984
    Abstract: Embodiments of the present invention are directed to forming a nanosheet field effect transistor (FET) having a low resistivity region that reduces the nanosheet external resistance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. An inner layer is formed over nanosheets in the nanosheet stack. The inner layer includes a first material having a first melting point. An outer layer is formed over the inner layer. The outer layer includes a second material having a second melting point that is lower than the first melting point. A heavily doped region is formed on a surface of the outer layer and the nanosheet stack is annealed at a temperature between the first melting point and the second melting point such that the outer layer is selectively liquified, distributing the dopants throughout the outer layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heng Wu, Oleg Gluschenkov, Lan Yu, Ruilong Xie
  • Patent number: 11004745
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 10995267
    Abstract: Disclosed herein are methods and compositions of nanoparticles having one or more layers of organic coating. In some embodiments, a nanoparticle comprises a core/shell nanocrystal comprising a first coating layer comprising a plurality of organic molecules, and a second organic coating layer surrounding the first organic coating layer, wherein the second coating layer comprises a plurality of organic molecules. Further, the organic molecules of the second coating layer are intercalated between the organic molecules of the first coating layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 4, 2021
    Assignee: CRYSTALPLEX CORPORATION
    Inventor: Matthew W. Bootman
  • Patent number: 10985021
    Abstract: A gallium nitride (GaN) substrate is injected with magnesium as a p-type dopant. The GaN substrate undergoes preheating through irradiation with light from halogen lamps in an atmosphere containing nitrogen and hydrogen, and further undergoes heating to a high temperature for a super-short time through irradiation with flashes of light from flash lamps. Heating the GaN substrate in the atmosphere containing nitrogen and hydrogen complements removed nitrogen, thus preventing nitrogen shortage. Such a heating process also enables heat treatment while supplying hydrogen to the GaN substrate. The heating process further enables crystal defects in the GaN substrate to be recovered. With these effects, the p-type dopant injected into the GaN substrate is activated with high efficiency.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 20, 2021
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Hideaki Tanimura, Takahiro Yamada, Shinichi Kato, Takayuki Aoyama
  • Patent number: 10978298
    Abstract: Disclosed is a process for producing semiconductor nanowires having a diameter or thickness from 2 nm to 100 nm, the process comprising: (A) preparing a semiconductor material particulate having a size from 50 nm to 500 ?m, selected from Ga, In, Ge, Sn, Pb, P, As, Sb, Bi, Te, a combination thereof, a compound thereof, or a combination thereof with Si; (B) depositing a catalytic metal, in the form of nanoparticles having a size from 1 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the semiconductor material particulate to form a catalyst metal-coated semiconductor material; and (C) exposing the catalyst metal-coated semiconductor material to a high temperature environment, from 100° C. to 2,500° C., for a period of time sufficient to enable a catalytic metal-assisted growth of multiple semiconductor nanowires from the particulate.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 13, 2021
    Assignee: Global Graphene Group, Inc.
    Inventor: Bor Z. Jang
  • Patent number: 10971367
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zhaoxu Shen, Duohui Bei
  • Patent number: 10947638
    Abstract: An underlying substrate including a seed crystal layer of a group 13 nitride, wherein projections and recesses repeatedly appear in stripe shapes at a principal surface of the seed crystal layer, and the projections have a level difference of 0.3 to 40 ?m and a width of 5 to 100 ?m, and the recesses have a bottom thickness of 2 ?m or more and a width of 50 to 500 ?m.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: March 16, 2021
    Inventors: Takayuki Hirao, Makoto Iwai, Katsuhiro Imai, Takashi Yoshino
  • Patent number: 10943925
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien
  • Patent number: 10930497
    Abstract: A method for producing a semiconductor substrate and a semiconductor substrate for use in epitaxial methods of a semiconductor material are described. The semiconductor substrate includes a support slice, an intermediate layer situated on the support slice, and an active layer situated on the intermediate layer. The intermediate layer includes a material which has a reduced viscosity or flows when the semiconductor substrate is used in an epitaxial method in order to enable at least a partial adaptation of a crystal lattice of the active layer to a crystal lattice of the semiconductor material at the transition between the active layer and the semiconductor material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 23, 2021
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventor: Ralf Lerner
  • Patent number: 10886123
    Abstract: A method for forming a metal nitride film with good film closure at low temperatures is disclosed. The method may comprise utilizing plasma to form NH and NH2 radicals to allow for the formation of the metal nitride at low temperatures. The method may also comprise flowing an etch gas to result in an amorphous film with uniform thickness. The method may also comprise flowing an alkyl hydrazine to inhibit three-dimensional island growth of the metal nitride film.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 5, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Petri Raisanen, Moataz Bellah Mousa, Peng-Fu Hsu
  • Patent number: 10879469
    Abstract: A semiconductor device includes a substrate, a nanotube structure, and a gate structure. The nanotube structure is disposed over the substrate. The nanotube structure includes a semiconducting carbon nanotube (s-CNT) and a first insulating nanotube. The first insulating nanotube has an inert surface on the s-CNT. The gate structure includes a first metallic carbon nanotube (m-CNT) over the nanotube structure.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Timothy Vasen
  • Patent number: 10847350
    Abstract: A heat treatment apparatus includes: a rotation table installed in a vacuum container, the rotation table mounting a substrate in a mounting area formed in one surface side of the rotation table and revolving the substrate; a heater that heats the rotation table; a plasma processing part that generates a plasma in a plasma generation region, which is formed in the one surface side of the rotation table at a region through which the substrate passes, and processes the substrate; a temperature measurement terminal installed in the rotation table at a region, which passes through a position facing the plasma generation region when the rotation table is rotated, the temperature measurement terminal outputting a temperature measurement result of the rotation table as an electric signal; and a conductive plasma shield part installed to cover the temperature measurement terminal when viewed from the plasma generation region.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Soichi Kanno
  • Patent number: 10811351
    Abstract: A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventor: Elliot N. Tan
  • Patent number: 10804294
    Abstract: In a method of manufacturing a ferroelectric device, a substrate is provided. A ferroelectric material film is formed over the substrate. A crystallization seed film is formed over the ferroelectric material film. The ferroelectric material film is heat-treated to covert the ferroelectric material film into a crystalline ferroelectric film. The crystallization seed film is removed to expose the crystalline ferroelectric film. An electrode film is formed over the ferroelectric film.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10801129
    Abstract: A nucleation structure for the epitaxial growth of three-dimensional semiconductor elements, including a substrate including a monocrystalline material forming a growth surface, a plurality of intermediate portions made of an intermediate crystalline material epitaxied from the growth surface and defining an upper intermediate surface, and a plurality of nucleation portions, made of a material including a transition metal forming a nucleation crystalline material, each epitaxied from the upper intermediate surface, and defining a nucleation surface suitable for the epitaxial growth of a three-dimensional semiconductor element.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 13, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, ALEDIA
    Inventors: Benoit Amstatt, Florian Dupont, Ewen Henaff, Berangere Hyot
  • Patent number: 10734518
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10727341
    Abstract: A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 28, 2020
    Inventor: Qiuming Huang
  • Patent number: 10711347
    Abstract: Processing chambers having a lid with a lower surface, a substrate support with an upper surface facing the lid and an inner baffle ring between the substrate support and the lid are described. Methods of using the processing chamber are described.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 14, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Dale R. DuBois, Karthik Janakiraman, Kien N. Chuc
  • Patent number: 10691270
    Abstract: A method is provided for manufacturing a wiring board that includes a conductor part including a first line and a second line wider than the first line. The method includes: a first process of forming the first line and a boundary line corresponding to at least a portion of an outline of the second line near the first line; and a second process of forming a remaining portion of the second line.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 23, 2020
    Assignee: Fujikura Ltd.
    Inventors: Shinsuke Aoshima, Kazutoshi Koshimizu
  • Patent number: 10692819
    Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a substrate; and at least one composition adjusting layer disposed above the substrate; wherein each of the at least one composition adjusting layer is made of a semiconductor compound, the semiconductor compound at least comprises a first element and a second element, and an atomic number of the first element is less than an atomic number of the second element, wherein in each of the at least one composition adjusting layer, along an epitaxial direction of the substrate, an atomic percentage of the first element in a compound composition is gradually decreased at first and then gradually increased, a thickness of a gradual decrease section is greater than a thickness of a gradual increase section.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 23, 2020
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Peng Xiang, Kai Cheng
  • Patent number: 10685884
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Cheng-Yi Peng, Ziwei Fang, I-Ming Chang, Akira Mineji, Yu-Ming Lin, Meng-Hsuan Hsiao
  • Patent number: 10672606
    Abstract: A method of forming a coating film includes horizontally supporting a substrate, supplying a coating solution to a central portion of the substrate and spreading the coating solution by a centrifugal force by rotating the substrate at a first rotational speed, decreasing a speed of the substrate from the first rotational speed toward a second rotational speed and rotating the substrate at the second rotational speed to make a surface of a liquid film of the coating solution even, supplying a gas to a surface of the substrate when the substrate is rotated at the second rotational speed to reduce fluidity of the coating solution, and drying the surface of the substrate by rotating the substrate at a third rotational speed faster than the second rotational speed.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kousuke Yoshihara, Takafumi Niwa
  • Patent number: 10672867
    Abstract: A method includes forming a fin structure over a substrate; forming an isolation structure around the fin structure; etching the fin structure to form a recess in the fin structure; epitaxially growing a source drain structure in the recess; depositing a capping layer over a first portion of the source drain structure, in which the first portion of the source drain structure is over the isolation structure; recessing the isolation structure to expose a second portion of the source drain structure; and etching the second portion of the source drain structure, in which the first portion of the source drain structure remains over the isolation structure after etching the second portion of the source drain structure.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 10662549
    Abstract: The present invention relates to a process for the production of III-V-, IV-IV- or II-VI-compound semiconductor crystals. The process starts with providing of a substrate with optionally one crystal layer (buffer layer). Subsequently, a gas phase is provided, which comprises at least two reactants of the elements of the compound semiconductor (II, III, IV, V, VI) which are gaseous at a reaction temperature in the crystal growth reactor and can react with each other at the selected reactor conditions. The ratio of the concentrations of two of the reactants is adjusted such that the compound semiconductor crystal can crystallize from the gas phase, wherein the concentration is selected that high, that crystal formation is possible, wherein by an adding or adjusting of reducing agent and of co-reactant, the activity of the III-, IV- or II-compound in the gas phase is decreased, so that the growth rate of the crystals is lower compared to a state without co-reactant.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: May 26, 2020
    Assignee: Freiberger Compound Materials GMBH
    Inventors: Berndt Weinert, Frank Habel, Gunnar Leibiger
  • Patent number: 10665467
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Patent number: 10633253
    Abstract: A method for carbon nanotube purification, preferably including: providing carbon nanotubes; depositing a mask; and/or selectively removing a portion of the mask; and optionally including removing a subset of the carbon nanotubes and/or removing the remaining mask.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 28, 2020
    Assignee: Aligned Carbon, Inc.
    Inventors: John Provine, Cara Beasley, Gregory Pitner
  • Patent number: 10629759
    Abstract: In an aspect of the disclosure, a process for forming nanostructuring on a silicon-containing substrate is provided. The process comprises (a) performing metal-assisted chemical etching on the substrate, (b) performing a clean, including partial or total removal of the metal used to assist the chemical etch, and (c) performing an isotropic or substantially isotropic chemical etch subsequently to the metal-assisted chemical etch of step (a). In an alternative aspect of the disclosure, the process comprises (a) performing metal-assisted chemical etching on the substrate, (b) cleaning the substrate, including removal of some or all of the assisting metal, and (c) performing a chemical etch which results in regularized openings in the silicon substrate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 21, 2020
    Assignee: Advanced Silicon Group, Inc.
    Inventors: Joanne Yim, Jeffrey B. Miller, Michael Jura, Marcie R. Black, Joanne Forziati, Brian P. Murphy, Lauren Magliozzi
  • Patent number: 10619243
    Abstract: A method and system is provided to improve precursor utilization in pulsed atomic layer processes. The system integrates a chiller with a precursor ampoule to lower the temperature of the precursor ampoule, and thereby reduce the precursor vapor pressure. By lowering the ampoule temperature, the loss of excess unreacted precursor molecules is reduced, in order to improve precursor utilization efficiency in atomic layer processes.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 14, 2020
    Inventors: Triratna P. Muneshwar, Ken Cadien
  • Patent number: 10622447
    Abstract: A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 14, 2020
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Theodore D. Kennedy, Amanda Kerr, William E. Hoke
  • Patent number: 10615353
    Abstract: A method for manufacturing an organic thin film transistor includes steps of: forming a graphene layer on a surface of a metal substrate; covering a surface of the graphene layer with an organic solution and heating the graphene layer to form organic semiconductor nano lines on the surface of the graphene layer; and transferring the organic semiconductor nano lines to a target substrate. The graphene layer is formed on the surface of the metal substrate in mass production. The organic semiconductor nano lines (monocrystalline semiconductor) are grown in mass production by the graphene layer. The semiconductor layer having organic thin film transistors is formed after transferring the organic semiconductor nano lines on the target substrate. A large amount of the organic semiconductor nano lines can be formed simultaneously on the surface of the metal substrate with a large area.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 7, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Bo Liang, Wei Wang
  • Patent number: 10597795
    Abstract: Semiconductor wafers with an epitaxial layer are produced in a deposition chamber by placing a substrate wafer in the edge region of the rear side of the substrate wafer onto a placement area of a susceptor; loading the deposition chamber with the susceptor and the substrate wafer lying on the susceptor by contacting the susceptor and transporting the susceptor and the substrate wafer lying on the susceptor from a load lock chamber into the deposition chamber; depositing an epitaxial layer on the substrate wafer; and unloading the deposition chamber by contacting the susceptor and transporting the susceptor and a semiconductor wafer with epitaxial layer, the semiconductor wafer having been produced in the course of depositing the epitaxial layer and lying on the susceptor, from the deposition chamber into the load lock chamber.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: March 24, 2020
    Assignee: SILTRONIC AG
    Inventors: Patrick Moos, Reinhard Schauer
  • Patent number: 10566189
    Abstract: Disclosed is a process for manufacturing a deep junction electronic device including steps of: b) Depositing a layer of non-monocrystalline semiconductor material on a plane surface of a substrate of a monocrystalline semiconductor material; c) Incorporating inactivated dopant elements prior to step b) into said substrate (1) and/or, respectively, during or after step b) into said layer, so as to form an inactivated doped layer; d) Exposing, an external surface of the layer formed at step b) to a laser thermal anneal beam, so as to melt said layer down to the substrate and so as to activate said dopant elements incorporated at step c); e) Stopping exposure to the laser beam so as to induce epi-like crystallization of the melted layer, so that said substrate and/or, respectively, an epi-like monocrystalline semiconductor material, comprises a layer of activated doped monocrystalline semiconductor material.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 18, 2020
    Assignee: LASER SYSTEMS & SOLUTIONS OF EUROPE
    Inventor: Fulvio Mazzamuto
  • Patent number: 10559711
    Abstract: Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H2 and/or NH3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: February 11, 2020
    Assignee: Gallium Enterprises Pty Ltd
    Inventors: Ian Mann, Satyanarayan Barik, Joshua David Brown, Danyu Liu
  • Patent number: 10553747
    Abstract: A semiconductor device comprises a substrate, a first semiconductor unit on the substrate, and an first adhesion structure between the substrate and the first semiconductor unit, and directly contacting the first semiconductor unit and the substrate, wherein the first adhesion structure comprises an adhesion layer and a sacrificial layer, and the adhesion layer and the sacrificial layer are made of different materials, and wherein an adhesion between the first semiconductor unit and the adhesion layer is different from that between the first semiconductor unit and the sacrificial layer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 4, 2020
    Assignee: Epistar Corporation
    Inventors: Chih-Chiang Lu, Yi-Ming Chen, Chun-Yu Lin, Ching-Pei Lin, Chung-Hsun Chien, Chien-Fu Huang, Hao-Min Ku, Min-Hsun Hsieh, Tzu-Chieh Hsu
  • Patent number: 10549483
    Abstract: A structured composite surface includes a backing layer and a plurality of composite posts in contact with the backing layer, each composite post having a core made of a first material and an outer shell made of a second material, the outer shell is in contact with and surrounding the core, the core has a Young's modulus of at least 50 times greater than the outer shell. A method of transfer printing includes pressing a stamp including at least one composite post to a substrate, the at least one composite post having a core made of a first material and an outer shell made of a second material, the outer shell is in contact with and surrounding the core, the core has a Young's modulus at least 50 times greater than the outer shell, and retracting the stamp from the substrate by applying a shear load to the stamp.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 4, 2020
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Kevin Turner, Helen Minsky
  • Patent number: 10546893
    Abstract: A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Young Hee Yoon, Eun Jeong Kwak
  • Patent number: 10529857
    Abstract: A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 7, 2020
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Qiuming Huang, Jun Tan, Qiang Yan
  • Patent number: 10522363
    Abstract: Methods and systems for forming a device structure free of a substrate are described. Exemplary embodiments include a device structure comprising of device layers, a release layer, an etch stop layer, and a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device layers from the substrate. The device structure can include a contact layer, an etch stop layer, or both in some embodiments.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 31, 2019
    Assignee: MICROLINK DEVICES, INC.
    Inventors: Christopher Youtsey, Robert McCarthy, Rekha Reddy
  • Patent number: 10516039
    Abstract: A tunnel field-effect transistor (TFET), comprising a first source/drain layer comprising a first polar sidewall; a second source/drain layer surrounding the first source/drain layer, wherein the second source/drain layer and the first source/drain layer are of opposite conductivity types; and a semiconductor interlayer between the second source/drain layer and first polar sidewall of the first source/drain layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Ramvall, Matthias Passlack, Gerben Doornbos
  • Patent number: 10510607
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 10505094
    Abstract: Superconducting nanowire avalanche photodetectors (SNAPs) have using meandering nanowires to detect incident photons. When a superconducting nanowire absorbs a photon, it switches from a superconducting state to a resistive state, producing a change in voltage that can be measured across the nanowire. A SNAP may include multiple nanowires in order to increase the fill factor of the SNAP's active area and the SNAP's detection efficiency. But using multiple meandering nanowires to achieve high fill-factor in SNAPs can lead to current crowding at bends in the nanowires. This current crowding degrades SNAP performance by decreasing the switching current, which the current at which the nanowire transitions from a superconducting state to a resistive state. Fortunately, staggering the bends in the nanowires reduces current crowding, increasing the nanowire switching current, which in turn increases the SNAP dynamic range.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 10, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Kristen Ann Sunter, Faraz Najafi, Adam Nykoruk McCaughan, Karl Kimon Berggren
  • Patent number: 10446571
    Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gurtej S. Sandhu, Kunal R. Parekh
  • Patent number: 10392297
    Abstract: A method for manufacturing a substrate is disclosed. The method comprises the following steps: step one, depositing an amorphous silicon layer on a base material; step two, depositing a silicon dioxide layer with a first thickness on the amorphous silicon layer; and step three, etching the silicon dioxide layer until a thickness thereof is reduced to a second thickness. According to the method of the present disclosure, the silicon dioxide layer with a needed thickness can be manufactured on the amorphous silicon layer. When the ELA procedure is performed, the silicon dioxide layer has an enough thickness to prevent the formation of protrusions at grain boundary of polysilicon, so that the semi-conductive layer manufactured therein can have a relatively low roughness.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 27, 2019
    Assignees: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventor: Zijian Li
  • Patent number: 10388762
    Abstract: Described is a technique for uniformly doping a silicon substrate having a Fin structure with a dopant. A method of manufacturing a semiconductor device may includes: (a) forming a dopant-containing film containing a dopant on a silicon film by performing a cycle a predetermined number of times, the cycle including: (a-1) forming a first dopant-containing film by supplying a first dopant-containing gas containing the dopant and a first ligand to a substrate having thereon the silicon film and one of a silicon oxide film and a silicon nitride film; and (a-2) forming a second dopant-containing film by supplying a second dopant-containing gas containing the dopant and a second ligand different from and reactive with the first ligand to the substrate; and (b) forming a doped silicon film by annealing the substrate having the dopant-containing film thereon to diffuse the dopant into the silicon film.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 20, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Masahito Kitamura, Hiroshi Ashihara
  • Patent number: 10364493
    Abstract: An exhaust apparatus using a gas curtain instead of a mechanical opening/closing structure is provided. The exhaust apparatus includes: a first region; a second region connected to the first region; a third region connected to the first region; and a first gas line connected to the second region, wherein when gas is supplied to the first gas line, the first region does not communicate with the second region but communicates with the third region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 30, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Hak Joo Lee, Dae Youn Kim, Seung Wook Kim, Jin Seok Park, Jae Hyun Kim