Abstract: Provided is a method for producing a GaN layered substrate, comprising the steps of: subjecting a C-plane sapphire substrate 11 having an off-angle of 0.5° to 5° to a high-temperature nitriding treatment at 800° C. to 1,000° C. to carry out a surface treatment of the C-plane sapphire substrate; carrying out epitaxial growth of GaN on the surface of the surface-treated C-plane sapphire substrate 11 to produce a GaN film carrier having a surface of an N polar face; forming an ion implantation region 13ion by carrying out ion implantation on the GaN film 13; laminating and joining a support substrate 12 with the GaN film-side surface of the ion-implanted GaN film carrier; and separating at the ion-implanted region 13ion in the GaN film 13 to transfer a GaN thin film 13a onto the support substrate 12, to produce a GaN layered substrate 10 having, on the support substrate 12, a GaN thin film 13a having a surface of a Ga polar face.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: A SiC ohmic contact preparation method is provided and includes: selecting a SiC substrate; preparing a graphene/SiC structure by forming a graphene on a Si-face of the SiC substrate; depositing an Au film on the graphene of the graphene/SiC structure; forming a first transfer electrode pattern on the Au film by a first photolithography; etching the Au film uncovered by the first transfer electrode pattern through a wet etching; etching the graphene uncovered by the Au film through a plasma etching after the wet etching; forming a second transfer electrode pattern on the SiC substrate by a second photolithography; depositing an Au material on the Au film exposed by the second transfer electrode pattern and forming an Au electrode and then annealing. The graphene reduces potential barrier associated with the SiC interface, specific contact resistance of ohmic contact reaches the order of 10?7˜10?8 ?·cm2, and the method has high repeatability.

Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.

Abstract: In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface including a flat region having a plurality of three-dimensionally designed surface structures on the flat region, a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures and a nitride-based semiconductor layer sequence on the nucleation layer, wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and wherein the oxygen content in the nucleation layer is greater than 1019 cm?3.

Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

Abstract: A manufacturing method of a fin semiconductor device comprises: providing a substrate, wherein a fin channel base is patterned on and in contact with the substrate; epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core; oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer at the top part of the fin channel base and an intermediate part of the fin channel base under the top part; and removing the oxide layer to expose the fin channel core, wherein the fin channel core suspends over the substrate.

Abstract: A strain gauge includes a flexible substrate, a resistor formed of material containing at least one from among chromium and nickel, on or above the substrate, and a pair of electrodes electrically connected to the resistor. Each electrode includes a plurality of first patterns that are juxtaposed at predetermined intervals and that are electrically connected to each other. A plurality of second patterns of which longitudinal directions are toward a same direction as a longitudinal direction of each of the first patterns are disposed between opposing electrodes.

Abstract: Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

Abstract: Disclosed is a process for producing graphene-semiconductor nanowire hybrid material, comprising: (A) preparing a catalyst metal-coated mixture mass, which includes mixing graphene sheets with micron or sub-micron scaled semiconductor particles to form a mixture and depositing a nano-scaled catalytic metal onto surfaces of the graphene sheets and/or semiconductor particles; and (B) exposing the catalyst metal-coated mixture mass to a high temperature environment (preferably from 100° C. to 2,500° C.) for a period of time sufficient to enable a catalytic metal-catalyzed growth of multiple semiconductor nanowires using the semiconductor particles as a feed material to form the graphene-semiconductor nanowire hybrid material composition. An optional etching or separating procedure may be conducted to remove catalytic metal or graphene from the semiconductor nanowires.

Abstract: A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.

Abstract: A method for fabricating an image sensor is described which includes forming an insulating layer on a semiconductor substrate and forming a recess in the semiconductor substrate and the insulating layer. An epitaxial structure is grown in the recess. A first polish treatment is then performed to the insulating layer and the epitaxial structure. The insulating layer is detected to obtain a signal intensity, and the signal intensity increases as a thickness of the insulating layer decreases. The first polish treatment stops when the signal intensity reaches a target value.

Abstract: There is provided a technique having a process that includes forming a film, which contains a first element and a second element on a substrate by performing a cycle a predetermined number of times, the cycle sequentially performing: (a) supplying a first precursor gas containing the first element to the substrate in a process chamber; (b) supplying a second precursor gas, which contains the first element and has a pyrolysis temperature lower than a pyrolysis temperature of the first precursor gas, to the substrate; and (c) supplying a reaction gas, which contains the second element that is different from the first element, to the substrate.

Abstract: An epitaxial silicon wafer includes: a silicon wafer doped with phosphorus as a dopant and having an electrical resistivity of less than 1.0 m ?·cm; and an epitaxial film formed on the silicon wafer. The silicon wafer includes: a main surface to which a (100) plane is inclined; and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°30? to 0°55? in any direction with respect to an axis perpendicular to the main surface. The epitaxial silicon wafer has at most 1/cm2 of a density of a hillock defect generated thereon.

Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

Abstract: The method of the present invention improves mechanical integrity of a crystalline silicon solar cell having an exposed layer of n-type silicon. A solution of electrically-conductive nanowires in an inert liquid is sprayed onto the exposed layer in order to form a grid pattern of the nanowires on the exposed layer after the inert liquid dries or evaporates.

Abstract: Systems and methods of using pulsed RF plasma to form amorphous and microcrystalline films are discussed herein. Methods of forming films can include (a) forming a plasma in a process chamber from a film precursor and (b) pulsing an RF power source to cause a duty cycle on time (TON) of a duty cycle of a pulse generated by the RF power source to be less than about 20% of a total cycle time (TTOT) of the duty cycle to form the film. The methods can further include (c) depositing a first film interlayer on a substrate in the process chamber; (d) subsequent to (c), purging the process chamber; and (e) subsequent to (d), introducing a hydrogen plasma to the process chamber. Further in the method, (b)-(e) are repeated to form a film. The film can have an in-film hydrogen content of less than about 10%.

Abstract: In an embodiment a method includes providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region, directly applying a nucleation layer of oxygen-containing AlN to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, wherein the nucleation layer is applied onto both the planar region and the three-dimensional surface structures of the growth surface, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.

Abstract: A semiconductor device has an active region through which current flows and a termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer in the active region, a first parallel pn structure is provided including first columns of the first conductivity type and second columns of a second conductivity type disposed repeatedly alternating one another in a plane parallel to the front surface. In the termination structure region, a second parallel pn structure is provided including third columns of the first conductivity type and fourth columns of the second conductivity type disposed repeatedly alternating one another. On a surface of the second parallel pn structure, a first semiconductor region of the second conductivity type is provided including plural regions apart from one another.

Abstract: A growth mask layer is formed over a semiconductor material layer on a substrate. Optionally, a patterned hard mask layer can be formed over the growth mask layer. A nano-imprint lithography (NIL) resist layer is applied, and is imprinted with a pattern of recesses by stamping. The pattern in the NIL resist layer through the growth mask layer to provide a patterned growth mask layer with clusters of openings therein. If a patterned hard mask layer is employed, the patterned hard mask can prevent transfer of the pattern in the area covered by the patterned hard mask layer. Semiconductor material portions, such as nanowires can be formed in a cluster configuration through the clusters of openings in the patterned growth mask layer. Alignment marks can be formed concurrently with formation of semiconductor material portions by employing nano-imprint lithography.

Abstract: The present invention discloses a two-dimensional AlN material and its preparation method and application, wherein the preparation method comprises the following steps: (1) selecting a substrate and its crystal orientation; (2) cleaning the surface of the substrate; (3) transferring a graphene layer to the substrate layer; (4) annealing the substrate; (5) using the MOCVD process to introduce H2 to open the graphene layer and passivate the surface of the substrate; and (6) using the MOCVD process to grow a two-dimensional AlN layer. The preparation method of the present invention has the advantages that the process is simple, time saving and efficient. Besides, the two-dimensional AlN material prepared by the present invention can be widely used in HEMT devices, deep ultraviolet detectors or deep ultraviolet LEDs, and other fields.

Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.

Abstract: Provided are a method of manufacturing a display device and a source substrate structure. The method of manufacturing the display device includes holding a light-emitting element on a source substrate that passes laser light of a certain wavelength therethrough, the holding being performed by a release layer between the source substrate and the light-emitting element, forming an adhesive layer on a driving substrate on which a driving substrate-side electrode is formed, moving the light-emitting element to a surface of the adhesive layer on the driving substrate from the source substrate by irradiating laser light of the certain wavelength to the release layer through the source substrate, and adhering the moved light-emitting element to the driving substrate by using the adhesive layer, and the release layer comprises a resin material with a thickness that is greater than or equal to 0.1 ?m and is less than or equal to 0.5 ?m.

Abstract: A technique for making etching amounts uniform in selectively etching SiGe layers formed on a wafer with respect to at least one of an Si layer, an SiO2 layer, and an SiN layer is provided. In an etching process where SiGe layers in a wafer W in which the SiGe layers and Si layers are alternately stacked and exposed in a recess are removed by side etching, ClF3 gas and HF gas are simultaneously supplied to the wafer W. Accordingly, it is possible to make the etching rates for respective SiGe layers uniform, and it becomes possible to obtain a uniform etching amount for respective SiGe layers.

Abstract: Systems, methods, and devices are described herein for identifying, monitoring, isolating, or selecting a cell having a predefined characteristic in a mixed population of cells utilizing a combination of any one or more of iDEP, a region of localized field enhancement, a variable frequency electric field, a wide bandwidth amplifier, and/or an imaging apparatus.

Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber; a substrate holder having a holding wall capable holding an outer periphery of the substrate; a process gas supply part provided above the reaction chamber, the process gas supply part having a first region supplying a first process gas and a second region around the first region supplying a second process gas having a carbon/silicon atomic ratio higher than that of the first process gas, an inner peripheral diameter of the second region being 75% or more and 130% or less of a diameter of the holding wall; a sidewall provided between the process gas supply part and the substrate holder, an inner peripheral diameter of the sidewall being 110% or more and 200% or less of an outer peripheral diameter of the second region; a first heater; a second heater; and a rotation driver.

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: A method includes depositing a layer comprising a photoinitiator and a curable material onto a surface and applying a nanoimprint mold on the layer of curable material to form a mesh comprising intersecting walls defining cavities. After applying the nanoimprint mold, the mesh is illuminated with light causing decarboxylation of the photoinitator to initiate curing of the curable material. After curing the curable material, the nanoimprint mold is removed and a wavelength converting material is deposited in the cavities to form an array of wavelength converting pixels.

Abstract: A composition of matter comprising: a graphitic substrate optionally carried on a support, a seed layer having a thickness of no more than 50 nm deposited directly on top of said substrate, opposite any support; and an oxide or nitride masking layer e directly on top of said seed layer; wherein a plurality of holes are present through said seed layer and through said masking layer to C said graphitic substrate; and wherein a plurality of nanowires or nanopyramids are grown from said substrate in said holes, said nanowres or nanopyramids comprising at least one semiconducting group III-V compound.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: Graphene photodetectors capable of operating in the sub-bandgap region relative to the bandgap of semiconductor nanoparticles, as well as methods of manufacturing the same, are provided. A photodetector can include a layer of graphene, a layer of semiconductor nanoparticles, a dielectric layer, a supporting medium, and a packaging layer. The semiconductor nanoparticles can be semiconductors with bandgaps larger than the energy of photons meant to be detected.

Abstract: A method for carbon nanotube purification, preferably including: providing carbon nanotubes; depositing a mask; and/or selectively removing a portion of the mask; and optionally including removing a subset of the carbon nanotubes and/or removing the remaining mask.

Abstract: A method for manufacturing graphene having a wrinkle pattern is provided. The method includes forming a wrinkle providing layer having a first thermal expansion coefficient on one surface of a graphene layer, forming a substrate having a second thermal expansion coefficient on one surface of the wrinkle providing layer, and performing a heat treatment to form wrinkles on the wrinkle providing layer by a difference between the first and second thermal expansion coefficients, thereby forming wrinkle patterns on the graphene layer.

Abstract: An apparatus for producing a Group-III nitride semiconductor crystal includes a raw material reaction chamber, a raw material reactor which is provided in the raw material reaction chamber and configured to generate a Group-III element-containing gas, a board-holding member configured to hold a board in the raw material reaction chamber, a raw material nozzle configured to spray the Group-III element-containing gas toward the board, a nitrogen source nozzle configured to spray a nitrogen element-containing gas toward the board, in which, in a side view seen in a direction perpendicular to a vertical direction, a spray direction of the nitrogen source nozzle intersects with a spray direction of the raw material nozzle before the board, and a mixing part in which the Group-III element-containing gas and the nitrogen element-containing gas are mixed together is formed around the intersection as a center, a heater, and a rotation mechanism.

Abstract: There is provided a technique that includes: (a) forming a first film containing boron and at least first bonds selected from the group of Si—C bonds and Si—N bonds on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a boron-containing pseudo-catalyst gas to the substrate; and supplying a first precursor gas containing at least the first bonds selected from the group of the Si—C bonds and the Si—N bonds to the substrate; (b) modifying the first film to a second film by supplying a gas containing hydrogen and oxygen to the substrate; and (c) modifying the second film to a third film by performing a thermal annealing process to the second film.

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

Abstract: Disclosed are amorphous nanostructure and methods of making amorphous nanostructure. The amorphous nanostructure has a transition metal and a halogen element in the main chain, and the transition metal has an oxidation number of +1. In addition, the inorganic polymer forming the amorphous nanostructure forms hydrogen bonding with an adjacent inorganic polymer. The side chain of the inorganic polymer for hydrogen bonding has hydrogen and elements for hydrogen bonding. Through this, various characteristics can be confirmed.

Abstract: A silicon chalcogenate precursor comprising the chemical formula of Si(XR1)nR24-n, where X is sulfur, selenium, or tellurium, R1 is hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, each R2 is independently hydrogen, an alkyl group, a substituted alkyl group, an alkoxide group, a substituted alkoxide group, an amide group, a substituted amide group, an amine group, a substituted amine group, or a halogen group, and n is 1, 2, 3, or 4. Methods of forming the silicon chalcogenate precursor, methods of forming silicon nitride, and methods of forming a semiconductor structure are also disclosed.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.

Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.

Abstract: The present disclosure provides a method and system for fabricating a semiconductor device. The method and system of the present disclosure, after obtaining the polysilicon layer, first form the protective oxide layer on the surface of the polysilicon layer, and then etch the protective oxide layer and the protrusions on the surface of the polysilicon layer with the buffered oxide etchant based on controllability of the buffered oxide etchant, thereby reducing the protrusions on the surface of the polysilicon layer, while well protecting the surface of the polysilicon layer. Therefore, the technical problem of surface roughness in the existing polysilicon layers is solved.