Formation Of Semiconductive Active Region On Any Substrate (e.g., Fluid Growth, Deposition) Patents (Class 438/478)
  • Patent number: 10364493
    Abstract: An exhaust apparatus using a gas curtain instead of a mechanical opening/closing structure is provided. The exhaust apparatus includes: a first region; a second region connected to the first region; a third region connected to the first region; and a first gas line connected to the second region, wherein when gas is supplied to the first gas line, the first region does not communicate with the second region but communicates with the third region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 30, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Hak Joo Lee, Dae Youn Kim, Seung Wook Kim, Jin Seok Park, Jae Hyun Kim
  • Patent number: 10361216
    Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
  • Patent number: 10353127
    Abstract: The wire grid polarizer (WGP) comprises an array of parallel, elongated nanostructures located over a surface of a transparent substrate and a plurality of spaces, including a space between adjacent nanostructures. Each of the nanostructures can include (1) a plurality of parallel, elongated wires located on the substrate, including an inner-pair located between an outer-pair; (2) lateral-gaps between each wire of the outer-pair and an adjacent wire of the inner-pair; (3) and a center-gap between the two wires of the inner-pair.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 16, 2019
    Assignee: Moxtek, Inc.
    Inventors: Bin Wang, Hua Li, Brian Bowers
  • Patent number: 10332691
    Abstract: A method for manufacturing a HEMT/HHMT device based on CH3NH3PbI3 material are provided. The method includes: selecting an Al2O3 substrate; manufacturing a source electrode and a drain electrode; forming a first electron transport layer on a surface of the source electrode, a surface of the drain electrode, and a surface of the Al2O3 substrate not covered by the source electrode and the drain electrode; manufacturing CH3NH3PbI3 material on a surface of the first electron transport layer to form a first light absorbing layer; and forming a gate electrode on a surface of the first light absorbing layer to complete the manufacture of the HEMT device.
    Type: Grant
    Filed: September 1, 2018
    Date of Patent: June 25, 2019
    Assignee: XIDIAN UNIVERSITY
    Inventors: Renxu Jia, Lei Yuan, Yucheng Wang, Tiqiang Pang, Yuming Zhang
  • Patent number: 10332889
    Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
  • Patent number: 10319586
    Abstract: An example method comprises an ALD sequence including contacting an outer substrate surface at a temperature T1 with a first precursor to form a monolayer onto the outer substrate surface. Temperature of the outer substrate surface and the monolayer thereon is increased to a temperature T2 that is at least 200° C. greater than a maximum of the temperature T1. The temperature-increasing is at a temperature-increasing rate that takes no more than 10 seconds to get the outer substrate surface and the monolayer thereon at least 200° C. above the maximum temperature T1. At the temperature T2, the monolayer is contacted with a second precursor that reacts with the monolayer to form a reaction product and a new outer substrate surface that each comprise a component from the monolayer and a component from the second precursor. With the monolayer not having been allowed to be at least 200° C.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Woohee Kim, Stefan Uhlenbrock
  • Patent number: 10312465
    Abstract: A method for making an organic light emitting diode includes providing a preform structure including an anode electrode, a hole transport layer, and an organic light emitting layer stacked on each other in that order. The organic light emitting layer has a first surface and a second surface opposite to the first surface, and the second surface is in direct contact with the hole transport layer. A carbon nanotube structure is located on the first surface. A monomer solution is disposed on the carbon nanotube structure, and the monomer solution is formed by dispersing a monomer into an organic solvent. The monomer is polymerized to form a polymer, and a cathode electrode is formed on the polymer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 4, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen Ning, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10273579
    Abstract: An apparatus for processing two or more substrates in a batch process by subjecting at least part of the surface of the substrates to alternating surface reactions of at least a first and a second precursor. The apparatus includes: multiple substrate holders for supporting the substrates, and a reaction chamber that includes a reaction space for depositing material on the surface of the substrates during a processing phase. The substrate holders are installed or arranged to be installed inside the reaction chamber for processing of the substrates inside the reaction chamber during the processing phase. During a loading phase in which the substrates are loaded to the substrate holders by a loading device, at least some of the substrate holders are arranged to be movable relative to each other.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 30, 2019
    Assignee: Beneq Oy
    Inventor: Leif Keto
  • Patent number: 10262859
    Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 16, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle, Gregory Bartlett, Nupur Bhargava
  • Patent number: 10256079
    Abstract: An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Xinglong Chen, Shankar Venkataraman
  • Patent number: 10253429
    Abstract: A method includes: a step of forming an oxide film on a backside of a silicon wafer; a step of removing the oxide film present at an outer periphery of the silicon wafer; a step of argon annealing in which a heat treatment is performed in an argon gas atmosphere; and a step of forming an epitaxial film on a surface of the silicon wafer, the step of forming the epitaxial film including: a step of pre-baking in which the silicon wafer is subjected to a heat treatment in an gas atmosphere containing hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer; and a step of growing the epitaxial film on the surface of the silicon wafer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: April 9, 2019
    Assignee: SUMCO CORPORATION
    Inventors: Naoya Nonaka, Tadashi Kawashima
  • Patent number: 10242868
    Abstract: In one instance, the seed crystal of this invention provides a nitrogen-polar c-plane surface of a GaN layer supported by a metallic plate. The coefficient of thermal expansion of the metallic plate matches that of GaN layer. The GaN layer is bonded to the metallic plate with bonding metal. The bonding metal not only bonds the GaN layer to the metallic plate but also covers the entire surface of the metallic plate to prevent corrosion of the metallic plate and optionally spontaneous nucleation of GaN on the metallic plate during the bulk GaN growth in supercritical ammonia. The bonding metal is compatible with the corrosive environment of ammonothermal growth.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 26, 2019
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Daryl Key
  • Patent number: 10236291
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie, Kwan-Yong Lim
  • Patent number: 10196845
    Abstract: A substrate carrier door assembly including relatively high sealing force that can be modulated. Substrate carrier door assembly includes a carrier door configured to seal to a carrier body, a first attraction member on the carrier body, and a second attraction member on the carrier door. Attraction members are selected from a group of a magnetic material and a permanent magnet. Substrate carrier door assembly includes a magnetic field generator energizable to reduce attraction force between the attraction members making the carrier door relatively easier to remove, yet providing enhanced sealing when not energized. Substrate carriers including the substrate carrier door assembly and methods of processing substrates are provided. A substrate carrier including a port configured to allow gas to be injected into, or removed from, a carrier chamber, and a magnetic port seal is also disclosed, as are numerous other aspects.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: February 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: John J. Mazzocco, Nir Merry
  • Patent number: 10170620
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10163932
    Abstract: A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 25, 2018
    Assignee: NUtech Ventures
    Inventors: Alexander Sinitskii, Alexei Grouverman, Alexey Lipatov
  • Patent number: 10151703
    Abstract: A method for imaging one dimension nanomaterials is provided. Firstly, one dimension nanomaterials sample, an optical microscope with a liquid immersion objective and a liquid are provided. Secondly, the one dimensional nanomaterials sample is immersed in the liquid. Thirdly, the one dimensional nanomaterials sample is illuminated by an incident beam to generate resonance Rayleigh scattering. Forthly, the liquid immersion objective is immersed into the liquid to get a resonance Rayleigh scattering (RRS) image of the one dimensional nanomaterials sample. Fifthly, spectra of the one dimensional nanomaterials sample are measured to obtain chirality of the one dimensional nanomaterials sample.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 11, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Yun Wu, Jing-Ying Yue, Xiao-Yang Lin, Qing-Yu Zhao, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10147634
    Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ritesh Jhaveri, Jeanne L. Luce, Sang-Won Park, Dennis G. Hanken
  • Patent number: 10134590
    Abstract: Systems and methods for growing high-quality CdTe-based materials at high growth rates are provided. According to an aspect of the invention, a method includes depositing a first CdTe-based layer on a CdTe-based template at a rate of greater than 1 ?m/min. Each of the first CdTe-based layer and the CdTe-based template has a single-crystal structure and/or a large-grain polycrystalline structure. The depositing is performed by physical vapor deposition.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: James M. Burst, David S. Albin, Eric Colegrove, Matthew O. Reese, Helio R. Moutinho, Wyatt K. Metzger, Joel N. Duenow
  • Patent number: 10134900
    Abstract: A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: November 20, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Qiuming Huang, Jun Tan, Qiang Yan
  • Patent number: 10119201
    Abstract: The present disclosure provides a method of fabricating a diamond membrane. The method comprises providing a substrate and a support structure. The substrate comprises a diamond material having a first surface and the substrate further comprises a sub-surface layer that is positioned below the first surface and has a crystallographic structure that is different to that of the diamond material. The sub-surface layer is positioned to divide the diamond material into first and second regions wherein the first region is positioned between the first surface and the sub-surface layer. The support structure also comprises a diamond material and is connected to, and covers a portion of, the first surface of the substrate. The method further comprises selectively removing the second region of the diamond material from the substrate by etching away at least a portion of the sub-surface layer of the substrate.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: November 6, 2018
    Assignee: The University of Melbourne
    Inventors: Afaq Habib Piracha, Steven Prawer, Kumaravelu Ganesan, Snjezana Tomljenovic-Hanic, Desmond Lau
  • Patent number: 10096464
    Abstract: Atomic layer deposition methods for the low temperature deposition of silicon dioxide films having low nitrogen content and low wet etch rates. Silicon dioxide films are deposited and treated with plasma and re-oxidized resulting in low nitrogen content films.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 9, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Mark Saly
  • Patent number: 10096701
    Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: October 9, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
  • Patent number: 10083774
    Abstract: The present invention provides a quantum dot encapsulated by a siloxane including an alkyl group having 4 or more carbon atoms, a composition including the same, and a device to which the composition is applied, and when the encapsulated quantum dot is used, quantum yield and dispersion stability may be enhanced.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 25, 2018
    Assignee: LMS Co., Ltd.
    Inventors: Doo Hyo Kwon, Jeong Og Choi, Oh Kwan Kwon
  • Patent number: 10084089
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 10084086
    Abstract: A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 25, 2018
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Qiuming Huang
  • Patent number: 10079242
    Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 18, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Thomas Melde, Elke Erben
  • Patent number: 10079328
    Abstract: Disclosed are a semiconductor nanocrystal comprising an alloy comprising an alloy including a Group III element, a Group II element, antimony, and a Group VI element; a method for preparing a semiconductor nanocrystal comprising an alloy comprising an alloy including a Group III element, a Group II element, antimony, and a Group VI element, and a light emitting device including an emissive material comprising a semiconductor nanocrystal comprising an alloy comprising an alloy including a Group III element, a Group II element, antimony, and a Group VI element.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Justin W. Kamplain
  • Patent number: 10074717
    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
  • Patent number: 10056252
    Abstract: A process of forming a semiconductor device by use of a MOCVD technique is disclosed. The semiconductor device, which is made of primarily nitride semiconductor materials, includes a GaN channel layer, an AlGaN barrier layer, and a GaN cap layer on a substrate. The barrier layer and the cap layer are grown under a gradient temperature condition where the upstream side of the substrate with respect to the flow of the MOCVD source gases is at a higher temperature as compared with the temperature at the downstream side of the substrate with respect to the flow of the source gases.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 21, 2018
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tadashi Watanabe, Hajime Matsuda
  • Patent number: 10050110
    Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy M. Cohen
  • Patent number: 10029277
    Abstract: The invention relates to a method of producing at least one layer of solid material.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 24, 2018
    Assignee: Siltectra, GmbH
    Inventors: Lukas Lichtensteiger, Jan Richter, Wolfram Drescher
  • Patent number: 9997615
    Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Yu Yeh, Chung-Cheng Wu, Cheng-Long Chen, Gwan-Sin Chang, Pang-Yen Tsai, Yen-Ming Chen, Yasutoshi Okuno, Ying-Hsuan Wang
  • Patent number: 9991341
    Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 5, 2018
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Arnaud Yvon
  • Patent number: 9982360
    Abstract: A method for transferring a graphene layer from a metal substrate to a second substrate is provided comprising: providing a graphene layer on the metal substrate, adsorbing hydrogen atoms on the metal substrate by passing protons through the graphene layer, treating the metal substrate having adsorbed hydrogen atoms thereon in such a way as to form hydrogen gas from the adsorbed hydrogen atoms, thereby detaching the graphene layer from the metal substrate, transferring the graphene layer to the second substrate, and optionally reusing the metal substrate by repeating the aforementioned steps.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 29, 2018
    Assignee: IMEC VZW
    Inventors: Cedric Huyghebaert, Philippe M. Vereecken, Geoffrey Pourtois
  • Patent number: 9978651
    Abstract: A silicon carbide single crystal substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface includes a central square region and an outer square region. When viewed in a thickness direction, each of the central square region and the outer square region has a side having a length of 15 mm. The first main surface has a maximum diameter of not less than 100 mm. The silicon carbide single crystal substrate has a TTV of not more than 5 ?m. A value obtained by dividing a LTIR in the central square region by a LTV in the central square region is not less than 0.8 and not more than 1.2. A value obtained by dividing a LTV in the outer square region by the LTV in the central square region is not less than 1 and not more than 3.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: May 22, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tsubasa Honke, Kyoko Okita
  • Patent number: 9966254
    Abstract: A substrate in which a high-dielectric-constant gate insulator is formed on a silicon substrate with an interface layer film sandwiched in between is housed in a chamber. The method of the invention including: (a) housing the substrate in a chamber; (b) supplying ammonia to the chamber to foam an ammonia atmosphere; and (c) applying flash light to a surface of the substrate housed in the chamber to heat the high dielectric constant film, wherein the flash light applied in said step (c) has a spectral distribution that has a peak in a wavelength range of 200 to 300 nm.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 8, 2018
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Hikaru Kawarazaki
  • Patent number: 9947533
    Abstract: A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 9934961
    Abstract: Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Chen Wang, Sai-Hooi Yeong, Tsung-Yao Wen, Yen-Ming Chen
  • Patent number: 9926427
    Abstract: Provided is a simple, fast, scalable, and environmentally benign method of producing a graphene-reinforced polymer matrix composite directly from a graphitic material, the method comprising: (a) mixing multiple particles of a graphitic material and multiple particles of a solid polymer carrier material to form a mixture in an impacting chamber of an energy impacting apparatus; (b) operating the energy impacting apparatus with a frequency and an intensity for a length of time sufficient for peeling off graphene sheets from the graphitic material and transferring the graphene sheets to surfaces of solid polymer carrier material particles to produce graphene-coated or graphene-embedded polymer particles inside the impacting chamber; and (c) forming graphene-coated or graphene-embedded polymer particles into the graphene-reinforced polymer matrix composite. Also provided is a mass of the graphene-coated or graphene-embedded polymer particles produced by this method.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 27, 2018
    Assignee: Nanotek Instruments, Inc.
    Inventors: Aruna Zhamu, Bor Z Jang
  • Patent number: 9920077
    Abstract: Halogen free amine substituted trisilylamine and tridisilylamine compounds and a method of their preparation via de-hydrogenative coupling between the corresponding unsubstituted trisilylamines and amines catalyzed by transition metal catalysts is described. This new approach is based on the catalytic dehydrocoupling of a Si—H and a N—H moiety to form an Si—N containing compound and hydrogen gas. The process can be catalyzed by transition metal heterogenous catalysts such as Ru(0) on carbon, Pd(0) on MgO) as well as transition metal organometallic complexes that act as homogeneous catalysts. The —Si—N containing products are halide free. Such compounds can be useful for the deposition of thin films by chemical vapor deposition or atomic layer deposition of Si containing films.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 20, 2018
    Assignee: L'Air Liquide, SociétéAnonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Antonio Sanchez, Jean-Marc Girard
  • Patent number: 9917105
    Abstract: A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Hong He, Ali Khakifirooz, Junli Wang
  • Patent number: 9911805
    Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
  • Patent number: 9905420
    Abstract: Methods of forming silicon germanium tin (SixGe1-xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 27, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 9899441
    Abstract: A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Lung Wu, Tung-I Lin, Yeur-Luen Tu
  • Patent number: 9899399
    Abstract: A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Hiroyuki Tanaka
  • Patent number: 9881831
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yi Chiu, Shih-Fang Hong, Chao-Hung Lin
  • Patent number: 9876121
    Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 23, 2018
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Sylvain Barraud, Shay Reboh, Maud Vinet
  • Patent number: 9865699
    Abstract: A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: January 9, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Daiyu Kondo, Shintaro Sato
  • Patent number: 9853119
    Abstract: Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 26, 2017
    Assignee: Bourns, Inc.
    Inventors: Andrew J. Morrish, Tao Wei