Formation Of Semiconductive Active Region On Any Substrate (e.g., Fluid Growth, Deposition) Patents (Class 438/478)
  • Patent number: 10734518
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10727341
    Abstract: A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: July 28, 2020
    Inventor: Qiuming Huang
  • Patent number: 10711347
    Abstract: Processing chambers having a lid with a lower surface, a substrate support with an upper surface facing the lid and an inner baffle ring between the substrate support and the lid are described. Methods of using the processing chamber are described.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 14, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Dale R. DuBois, Karthik Janakiraman, Kien N. Chuc
  • Patent number: 10692819
    Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a substrate; and at least one composition adjusting layer disposed above the substrate; wherein each of the at least one composition adjusting layer is made of a semiconductor compound, the semiconductor compound at least comprises a first element and a second element, and an atomic number of the first element is less than an atomic number of the second element, wherein in each of the at least one composition adjusting layer, along an epitaxial direction of the substrate, an atomic percentage of the first element in a compound composition is gradually decreased at first and then gradually increased, a thickness of a gradual decrease section is greater than a thickness of a gradual increase section.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 23, 2020
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Peng Xiang, Kai Cheng
  • Patent number: 10691270
    Abstract: A method is provided for manufacturing a wiring board that includes a conductor part including a first line and a second line wider than the first line. The method includes: a first process of forming the first line and a boundary line corresponding to at least a portion of an outline of the second line near the first line; and a second process of forming a remaining portion of the second line.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 23, 2020
    Assignee: Fujikura Ltd.
    Inventors: Shinsuke Aoshima, Kazutoshi Koshimizu
  • Patent number: 10685884
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Cheng-Yi Peng, Ziwei Fang, I-Ming Chang, Akira Mineji, Yu-Ming Lin, Meng-Hsuan Hsiao
  • Patent number: 10672867
    Abstract: A method includes forming a fin structure over a substrate; forming an isolation structure around the fin structure; etching the fin structure to form a recess in the fin structure; epitaxially growing a source drain structure in the recess; depositing a capping layer over a first portion of the source drain structure, in which the first portion of the source drain structure is over the isolation structure; recessing the isolation structure to expose a second portion of the source drain structure; and etching the second portion of the source drain structure, in which the first portion of the source drain structure remains over the isolation structure after etching the second portion of the source drain structure.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 10672606
    Abstract: A method of forming a coating film includes horizontally supporting a substrate, supplying a coating solution to a central portion of the substrate and spreading the coating solution by a centrifugal force by rotating the substrate at a first rotational speed, decreasing a speed of the substrate from the first rotational speed toward a second rotational speed and rotating the substrate at the second rotational speed to make a surface of a liquid film of the coating solution even, supplying a gas to a surface of the substrate when the substrate is rotated at the second rotational speed to reduce fluidity of the coating solution, and drying the surface of the substrate by rotating the substrate at a third rotational speed faster than the second rotational speed.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kousuke Yoshihara, Takafumi Niwa
  • Patent number: 10662549
    Abstract: The present invention relates to a process for the production of III-V-, IV-IV- or II-VI-compound semiconductor crystals. The process starts with providing of a substrate with optionally one crystal layer (buffer layer). Subsequently, a gas phase is provided, which comprises at least two reactants of the elements of the compound semiconductor (II, III, IV, V, VI) which are gaseous at a reaction temperature in the crystal growth reactor and can react with each other at the selected reactor conditions. The ratio of the concentrations of two of the reactants is adjusted such that the compound semiconductor crystal can crystallize from the gas phase, wherein the concentration is selected that high, that crystal formation is possible, wherein by an adding or adjusting of reducing agent and of co-reactant, the activity of the III-, IV- or II-compound in the gas phase is decreased, so that the growth rate of the crystals is lower compared to a state without co-reactant.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: May 26, 2020
    Assignee: Freiberger Compound Materials GMBH
    Inventors: Berndt Weinert, Frank Habel, Gunnar Leibiger
  • Patent number: 10665467
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Patent number: 10633253
    Abstract: A method for carbon nanotube purification, preferably including: providing carbon nanotubes; depositing a mask; and/or selectively removing a portion of the mask; and optionally including removing a subset of the carbon nanotubes and/or removing the remaining mask.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 28, 2020
    Assignee: Aligned Carbon, Inc.
    Inventors: John Provine, Cara Beasley, Gregory Pitner
  • Patent number: 10629759
    Abstract: In an aspect of the disclosure, a process for forming nanostructuring on a silicon-containing substrate is provided. The process comprises (a) performing metal-assisted chemical etching on the substrate, (b) performing a clean, including partial or total removal of the metal used to assist the chemical etch, and (c) performing an isotropic or substantially isotropic chemical etch subsequently to the metal-assisted chemical etch of step (a). In an alternative aspect of the disclosure, the process comprises (a) performing metal-assisted chemical etching on the substrate, (b) cleaning the substrate, including removal of some or all of the assisting metal, and (c) performing a chemical etch which results in regularized openings in the silicon substrate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 21, 2020
    Assignee: Advanced Silicon Group, Inc.
    Inventors: Joanne Yim, Jeffrey B. Miller, Michael Jura, Marcie R. Black, Joanne Forziati, Brian P. Murphy, Lauren Magliozzi
  • Patent number: 10619243
    Abstract: A method and system is provided to improve precursor utilization in pulsed atomic layer processes. The system integrates a chiller with a precursor ampoule to lower the temperature of the precursor ampoule, and thereby reduce the precursor vapor pressure. By lowering the ampoule temperature, the loss of excess unreacted precursor molecules is reduced, in order to improve precursor utilization efficiency in atomic layer processes.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 14, 2020
    Inventors: Triratna P. Muneshwar, Ken Cadien
  • Patent number: 10622447
    Abstract: A structure having: a nucleation layer; and a Group III-Nitride structure disposed on a surface of the nucleation layer, the Group III-Nitride structure comprising a plurality of pairs of stacked Group III-Nitride layers, each one of the pairs of layers having a lower layer having a 3D growth structure and each one of the upper one of the pairs of layers having a 2D growth structure. Each one of the lower layers at completion has a surface roughness greater than a surface roughness at completion of an upper one of the pair of layers. Interfaces between each one of the upper layers and each one of the lower layers of the plurality of pairs of stacked Group III-Nitride layers have crystallographic dislocation combinations and/or annihilations therein.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 14, 2020
    Assignee: Raytheon Company
    Inventors: Brian D. Schultz, Theodore D. Kennedy, Amanda Kerr, William E. Hoke
  • Patent number: 10615353
    Abstract: A method for manufacturing an organic thin film transistor includes steps of: forming a graphene layer on a surface of a metal substrate; covering a surface of the graphene layer with an organic solution and heating the graphene layer to form organic semiconductor nano lines on the surface of the graphene layer; and transferring the organic semiconductor nano lines to a target substrate. The graphene layer is formed on the surface of the metal substrate in mass production. The organic semiconductor nano lines (monocrystalline semiconductor) are grown in mass production by the graphene layer. The semiconductor layer having organic thin film transistors is formed after transferring the organic semiconductor nano lines on the target substrate. A large amount of the organic semiconductor nano lines can be formed simultaneously on the surface of the metal substrate with a large area.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 7, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Bo Liang, Wei Wang
  • Patent number: 10597795
    Abstract: Semiconductor wafers with an epitaxial layer are produced in a deposition chamber by placing a substrate wafer in the edge region of the rear side of the substrate wafer onto a placement area of a susceptor; loading the deposition chamber with the susceptor and the substrate wafer lying on the susceptor by contacting the susceptor and transporting the susceptor and the substrate wafer lying on the susceptor from a load lock chamber into the deposition chamber; depositing an epitaxial layer on the substrate wafer; and unloading the deposition chamber by contacting the susceptor and transporting the susceptor and a semiconductor wafer with epitaxial layer, the semiconductor wafer having been produced in the course of depositing the epitaxial layer and lying on the susceptor, from the deposition chamber into the load lock chamber.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: March 24, 2020
    Assignee: SILTRONIC AG
    Inventors: Patrick Moos, Reinhard Schauer
  • Patent number: 10566189
    Abstract: Disclosed is a process for manufacturing a deep junction electronic device including steps of: b) Depositing a layer of non-monocrystalline semiconductor material on a plane surface of a substrate of a monocrystalline semiconductor material; c) Incorporating inactivated dopant elements prior to step b) into said substrate (1) and/or, respectively, during or after step b) into said layer, so as to form an inactivated doped layer; d) Exposing, an external surface of the layer formed at step b) to a laser thermal anneal beam, so as to melt said layer down to the substrate and so as to activate said dopant elements incorporated at step c); e) Stopping exposure to the laser beam so as to induce epi-like crystallization of the melted layer, so that said substrate and/or, respectively, an epi-like monocrystalline semiconductor material, comprises a layer of activated doped monocrystalline semiconductor material.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 18, 2020
    Assignee: LASER SYSTEMS & SOLUTIONS OF EUROPE
    Inventor: Fulvio Mazzamuto
  • Patent number: 10559711
    Abstract: Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H2 and/or NH3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: February 11, 2020
    Assignee: Gallium Enterprises Pty Ltd
    Inventors: Ian Mann, Satyanarayan Barik, Joshua David Brown, Danyu Liu
  • Patent number: 10553747
    Abstract: A semiconductor device comprises a substrate, a first semiconductor unit on the substrate, and an first adhesion structure between the substrate and the first semiconductor unit, and directly contacting the first semiconductor unit and the substrate, wherein the first adhesion structure comprises an adhesion layer and a sacrificial layer, and the adhesion layer and the sacrificial layer are made of different materials, and wherein an adhesion between the first semiconductor unit and the adhesion layer is different from that between the first semiconductor unit and the sacrificial layer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 4, 2020
    Assignee: Epistar Corporation
    Inventors: Chih-Chiang Lu, Yi-Ming Chen, Chun-Yu Lin, Ching-Pei Lin, Chung-Hsun Chien, Chien-Fu Huang, Hao-Min Ku, Min-Hsun Hsieh, Tzu-Chieh Hsu
  • Patent number: 10549483
    Abstract: A structured composite surface includes a backing layer and a plurality of composite posts in contact with the backing layer, each composite post having a core made of a first material and an outer shell made of a second material, the outer shell is in contact with and surrounding the core, the core has a Young's modulus of at least 50 times greater than the outer shell. A method of transfer printing includes pressing a stamp including at least one composite post to a substrate, the at least one composite post having a core made of a first material and an outer shell made of a second material, the outer shell is in contact with and surrounding the core, the core has a Young's modulus at least 50 times greater than the outer shell, and retracting the stamp from the substrate by applying a shear load to the stamp.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 4, 2020
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Kevin Turner, Helen Minsky
  • Patent number: 10546893
    Abstract: A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Young Hee Yoon, Eun Jeong Kwak
  • Patent number: 10529857
    Abstract: A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 7, 2020
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Qiuming Huang, Jun Tan, Qiang Yan
  • Patent number: 10522363
    Abstract: Methods and systems for forming a device structure free of a substrate are described. Exemplary embodiments include a device structure comprising of device layers, a release layer, an etch stop layer, and a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device layers from the substrate. The device structure can include a contact layer, an etch stop layer, or both in some embodiments.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 31, 2019
    Assignee: MICROLINK DEVICES, INC.
    Inventors: Christopher Youtsey, Robert McCarthy, Rekha Reddy
  • Patent number: 10516039
    Abstract: A tunnel field-effect transistor (TFET), comprising a first source/drain layer comprising a first polar sidewall; a second source/drain layer surrounding the first source/drain layer, wherein the second source/drain layer and the first source/drain layer are of opposite conductivity types; and a semiconductor interlayer between the second source/drain layer and first polar sidewall of the first source/drain layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peter Ramvall, Matthias Passlack, Gerben Doornbos
  • Patent number: 10510607
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 10505094
    Abstract: Superconducting nanowire avalanche photodetectors (SNAPs) have using meandering nanowires to detect incident photons. When a superconducting nanowire absorbs a photon, it switches from a superconducting state to a resistive state, producing a change in voltage that can be measured across the nanowire. A SNAP may include multiple nanowires in order to increase the fill factor of the SNAP's active area and the SNAP's detection efficiency. But using multiple meandering nanowires to achieve high fill-factor in SNAPs can lead to current crowding at bends in the nanowires. This current crowding degrades SNAP performance by decreasing the switching current, which the current at which the nanowire transitions from a superconducting state to a resistive state. Fortunately, staggering the bends in the nanowires reduces current crowding, increasing the nanowire switching current, which in turn increases the SNAP dynamic range.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 10, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Kristen Ann Sunter, Faraz Najafi, Adam Nykoruk McCaughan, Karl Kimon Berggren
  • Patent number: 10446571
    Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gurtej S. Sandhu, Kunal R. Parekh
  • Patent number: 10392297
    Abstract: A method for manufacturing a substrate is disclosed. The method comprises the following steps: step one, depositing an amorphous silicon layer on a base material; step two, depositing a silicon dioxide layer with a first thickness on the amorphous silicon layer; and step three, etching the silicon dioxide layer until a thickness thereof is reduced to a second thickness. According to the method of the present disclosure, the silicon dioxide layer with a needed thickness can be manufactured on the amorphous silicon layer. When the ELA procedure is performed, the silicon dioxide layer has an enough thickness to prevent the formation of protrusions at grain boundary of polysilicon, so that the semi-conductive layer manufactured therein can have a relatively low roughness.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 27, 2019
    Assignees: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventor: Zijian Li
  • Patent number: 10388762
    Abstract: Described is a technique for uniformly doping a silicon substrate having a Fin structure with a dopant. A method of manufacturing a semiconductor device may includes: (a) forming a dopant-containing film containing a dopant on a silicon film by performing a cycle a predetermined number of times, the cycle including: (a-1) forming a first dopant-containing film by supplying a first dopant-containing gas containing the dopant and a first ligand to a substrate having thereon the silicon film and one of a silicon oxide film and a silicon nitride film; and (a-2) forming a second dopant-containing film by supplying a second dopant-containing gas containing the dopant and a second ligand different from and reactive with the first ligand to the substrate; and (b) forming a doped silicon film by annealing the substrate having the dopant-containing film thereon to diffuse the dopant into the silicon film.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 20, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Masahito Kitamura, Hiroshi Ashihara
  • Patent number: 10364493
    Abstract: An exhaust apparatus using a gas curtain instead of a mechanical opening/closing structure is provided. The exhaust apparatus includes: a first region; a second region connected to the first region; a third region connected to the first region; and a first gas line connected to the second region, wherein when gas is supplied to the first gas line, the first region does not communicate with the second region but communicates with the third region.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 30, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Hak Joo Lee, Dae Youn Kim, Seung Wook Kim, Jin Seok Park, Jae Hyun Kim
  • Patent number: 10361216
    Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
  • Patent number: 10353127
    Abstract: The wire grid polarizer (WGP) comprises an array of parallel, elongated nanostructures located over a surface of a transparent substrate and a plurality of spaces, including a space between adjacent nanostructures. Each of the nanostructures can include (1) a plurality of parallel, elongated wires located on the substrate, including an inner-pair located between an outer-pair; (2) lateral-gaps between each wire of the outer-pair and an adjacent wire of the inner-pair; (3) and a center-gap between the two wires of the inner-pair.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 16, 2019
    Assignee: Moxtek, Inc.
    Inventors: Bin Wang, Hua Li, Brian Bowers
  • Patent number: 10332691
    Abstract: A method for manufacturing a HEMT/HHMT device based on CH3NH3PbI3 material are provided. The method includes: selecting an Al2O3 substrate; manufacturing a source electrode and a drain electrode; forming a first electron transport layer on a surface of the source electrode, a surface of the drain electrode, and a surface of the Al2O3 substrate not covered by the source electrode and the drain electrode; manufacturing CH3NH3PbI3 material on a surface of the first electron transport layer to form a first light absorbing layer; and forming a gate electrode on a surface of the first light absorbing layer to complete the manufacture of the HEMT device.
    Type: Grant
    Filed: September 1, 2018
    Date of Patent: June 25, 2019
    Assignee: XIDIAN UNIVERSITY
    Inventors: Renxu Jia, Lei Yuan, Yucheng Wang, Tiqiang Pang, Yuming Zhang
  • Patent number: 10332889
    Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
  • Patent number: 10319586
    Abstract: An example method comprises an ALD sequence including contacting an outer substrate surface at a temperature T1 with a first precursor to form a monolayer onto the outer substrate surface. Temperature of the outer substrate surface and the monolayer thereon is increased to a temperature T2 that is at least 200° C. greater than a maximum of the temperature T1. The temperature-increasing is at a temperature-increasing rate that takes no more than 10 seconds to get the outer substrate surface and the monolayer thereon at least 200° C. above the maximum temperature T1. At the temperature T2, the monolayer is contacted with a second precursor that reacts with the monolayer to form a reaction product and a new outer substrate surface that each comprise a component from the monolayer and a component from the second precursor. With the monolayer not having been allowed to be at least 200° C.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Woohee Kim, Stefan Uhlenbrock
  • Patent number: 10312465
    Abstract: A method for making an organic light emitting diode includes providing a preform structure including an anode electrode, a hole transport layer, and an organic light emitting layer stacked on each other in that order. The organic light emitting layer has a first surface and a second surface opposite to the first surface, and the second surface is in direct contact with the hole transport layer. A carbon nanotube structure is located on the first surface. A monomer solution is disposed on the carbon nanotube structure, and the monomer solution is formed by dispersing a monomer into an organic solvent. The monomer is polymerized to form a polymer, and a cathode electrode is formed on the polymer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 4, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen Ning, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10273579
    Abstract: An apparatus for processing two or more substrates in a batch process by subjecting at least part of the surface of the substrates to alternating surface reactions of at least a first and a second precursor. The apparatus includes: multiple substrate holders for supporting the substrates, and a reaction chamber that includes a reaction space for depositing material on the surface of the substrates during a processing phase. The substrate holders are installed or arranged to be installed inside the reaction chamber for processing of the substrates inside the reaction chamber during the processing phase. During a loading phase in which the substrates are loaded to the substrate holders by a loading device, at least some of the substrate holders are arranged to be movable relative to each other.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 30, 2019
    Assignee: Beneq Oy
    Inventor: Leif Keto
  • Patent number: 10262859
    Abstract: A gas distribution system is disclosed in order to obtain better film uniformity on a substrate in a cross-flow reactor. The better film uniformity may be achieved by an asymmetric bias on individual injection ports of the gas distribution system. The gas distribution may allow for varied tunability of the film properties.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 16, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle, Gregory Bartlett, Nupur Bhargava
  • Patent number: 10256079
    Abstract: An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Xinglong Chen, Shankar Venkataraman
  • Patent number: 10253429
    Abstract: A method includes: a step of forming an oxide film on a backside of a silicon wafer; a step of removing the oxide film present at an outer periphery of the silicon wafer; a step of argon annealing in which a heat treatment is performed in an argon gas atmosphere; and a step of forming an epitaxial film on a surface of the silicon wafer, the step of forming the epitaxial film including: a step of pre-baking in which the silicon wafer is subjected to a heat treatment in an gas atmosphere containing hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer; and a step of growing the epitaxial film on the surface of the silicon wafer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: April 9, 2019
    Assignee: SUMCO CORPORATION
    Inventors: Naoya Nonaka, Tadashi Kawashima
  • Patent number: 10242868
    Abstract: In one instance, the seed crystal of this invention provides a nitrogen-polar c-plane surface of a GaN layer supported by a metallic plate. The coefficient of thermal expansion of the metallic plate matches that of GaN layer. The GaN layer is bonded to the metallic plate with bonding metal. The bonding metal not only bonds the GaN layer to the metallic plate but also covers the entire surface of the metallic plate to prevent corrosion of the metallic plate and optionally spontaneous nucleation of GaN on the metallic plate during the bulk GaN growth in supercritical ammonia. The bonding metal is compatible with the corrosive environment of ammonothermal growth.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: March 26, 2019
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Daryl Key
  • Patent number: 10236291
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie, Kwan-Yong Lim
  • Patent number: 10196845
    Abstract: A substrate carrier door assembly including relatively high sealing force that can be modulated. Substrate carrier door assembly includes a carrier door configured to seal to a carrier body, a first attraction member on the carrier body, and a second attraction member on the carrier door. Attraction members are selected from a group of a magnetic material and a permanent magnet. Substrate carrier door assembly includes a magnetic field generator energizable to reduce attraction force between the attraction members making the carrier door relatively easier to remove, yet providing enhanced sealing when not energized. Substrate carriers including the substrate carrier door assembly and methods of processing substrates are provided. A substrate carrier including a port configured to allow gas to be injected into, or removed from, a carrier chamber, and a magnetic port seal is also disclosed, as are numerous other aspects.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: February 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: John J. Mazzocco, Nir Merry
  • Patent number: 10170620
    Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10163932
    Abstract: A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 25, 2018
    Assignee: NUtech Ventures
    Inventors: Alexander Sinitskii, Alexei Grouverman, Alexey Lipatov
  • Patent number: 10151703
    Abstract: A method for imaging one dimension nanomaterials is provided. Firstly, one dimension nanomaterials sample, an optical microscope with a liquid immersion objective and a liquid are provided. Secondly, the one dimensional nanomaterials sample is immersed in the liquid. Thirdly, the one dimensional nanomaterials sample is illuminated by an incident beam to generate resonance Rayleigh scattering. Forthly, the liquid immersion objective is immersed into the liquid to get a resonance Rayleigh scattering (RRS) image of the one dimensional nanomaterials sample. Fifthly, spectra of the one dimensional nanomaterials sample are measured to obtain chirality of the one dimensional nanomaterials sample.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 11, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wen-Yun Wu, Jing-Ying Yue, Xiao-Yang Lin, Qing-Yu Zhao, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10147634
    Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ritesh Jhaveri, Jeanne L. Luce, Sang-Won Park, Dennis G. Hanken
  • Patent number: 10134590
    Abstract: Systems and methods for growing high-quality CdTe-based materials at high growth rates are provided. According to an aspect of the invention, a method includes depositing a first CdTe-based layer on a CdTe-based template at a rate of greater than 1 ?m/min. Each of the first CdTe-based layer and the CdTe-based template has a single-crystal structure and/or a large-grain polycrystalline structure. The depositing is performed by physical vapor deposition.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: James M. Burst, David S. Albin, Eric Colegrove, Matthew O. Reese, Helio R. Moutinho, Wyatt K. Metzger, Joel N. Duenow
  • Patent number: 10134900
    Abstract: A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: November 20, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Qiuming Huang, Jun Tan, Qiang Yan
  • Patent number: 10119201
    Abstract: The present disclosure provides a method of fabricating a diamond membrane. The method comprises providing a substrate and a support structure. The substrate comprises a diamond material having a first surface and the substrate further comprises a sub-surface layer that is positioned below the first surface and has a crystallographic structure that is different to that of the diamond material. The sub-surface layer is positioned to divide the diamond material into first and second regions wherein the first region is positioned between the first surface and the sub-surface layer. The support structure also comprises a diamond material and is connected to, and covers a portion of, the first surface of the substrate. The method further comprises selectively removing the second region of the diamond material from the substrate by etching away at least a portion of the sub-surface layer of the substrate.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: November 6, 2018
    Assignee: The University of Melbourne
    Inventors: Afaq Habib Piracha, Steven Prawer, Kumaravelu Ganesan, Snjezana Tomljenovic-Hanic, Desmond Lau