Recoil Implantation Patents (Class 438/536)
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Patent number: 10651037Abstract: One embodiment of the invention relates to a method for fabricating a doped semiconductor zone in a semiconductor body. The method includes implanting dopant particles via one side into the semiconductor body or applying a layer containing dopant particles to one side of the semiconductor body. The method also includes irradiating the semiconductor body via the one side with further particles at least in the region containing the dopant particles. The method finally includes carrying out a thermal treatment by means of which the semiconductor body is heated, at least in the region containing the dopant particles, to a predetermined temperature in order to activate the implanted dopant particles, said temperature being less than 700° C.Type: GrantFiled: September 22, 2005Date of Patent: May 12, 2020Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Anton Mauder, Helmut Strack, Holger Schulze
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Patent number: 10546971Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.Type: GrantFiled: January 10, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Ning Li, Devendra Sadana, Yao Yao
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Patent number: 8497194Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: GrantFiled: November 12, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Lequn Jennifer Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
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Patent number: 8329567Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.Type: GrantFiled: November 3, 2010Date of Patent: December 11, 2012Assignee: Micron Technology, Inc.Inventors: Jennifer Lequn Liu, Shu Qin, Allen McTeer, Yongjun Jeff Hu
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Patent number: 8108159Abstract: A method of detecting a degradation of a semiconductor device including calculating a first number of first traps accumulated in a gate insulation layer of the semiconductor device over an operation time of the semiconductor device; calculating the second number of second traps accumulated at an interface between the gate insulation layer and a substrate over the operation time; and calculating the degradation of the semiconductor device relative to the operation time using the first number of the first traps and the second number of the second traps.Type: GrantFiled: September 19, 2008Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Gi-Young Yang, Chi-Hwan Lee
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Patent number: 7268065Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: GrantFiled: June 18, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Patent number: 7189623Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.Type: GrantFiled: August 31, 2005Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventors: Salman Akram, Akram Ditali
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Patent number: 7042066Abstract: A memory array dual-trench isolation structure and a method for forming the same have been provided.Type: GrantFiled: January 19, 2005Date of Patent: May 9, 2006Assignee: Sharp Laboratories of America, Inc.Inventors: Sheng Teng Hsu, Wei Pan, Wei-Wei Zhuang
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Publication number: 20020151155Abstract: A structure of a reflector is disclosed. Accordingly the present invention provides a reflector wire structure comprising, an electrical wire having a covering layer formed thereon. A base film is formed over the covering layer. A retroreflective film is formed over the base film. A protective film is formed over the retroreflective film.Type: ApplicationFiled: April 13, 2001Publication date: October 17, 2002Inventor: Yueh Ching
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Patent number: 6083780Abstract: A semiconductor device and a method of fabricating such a semiconductor device in which a silicon nitride film constituting a protective film for ion implantation is used for improving the device structure in order that conversion of a metal film into a silicide for reducing the resistance of a shallow-junction diffused layer may not be prevented by the knock-on phenomenon of oxygen, thereby reduce the fabrication cost. A silicon nitride film, which is used as a protective film for ion implantation into a substrate and a gate polysilicon, is processed into side walls of the gate polysilicon thereby to omit the step of forming side walls by a silicon oxide film. Further, in the case where boron is diffused into the gate polysilicon, boron diffusion is suppressed by nitrogen knock-on, thereby preventing boron from going through the gate oxide film.Type: GrantFiled: April 22, 1997Date of Patent: July 4, 2000Assignee: United Microelectronics CorporationInventor: Hiroyasu Yasuda