Introduction Of Conductivity Modifying Dopant Into Semiconductive Material Patents (Class 438/510)
  • Patent number: 10559683
    Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros
  • Patent number: 10475891
    Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jin Qiu Liu, Fan Zhang, Lai Qiang Luo, Xin Shu Cai, Eugene Kong, Zhiqiang Teo, Fangxin Deng
  • Patent number: 10286484
    Abstract: An additive manufacturing system including a consolidation device, a build platform, an optical detector, and a controller is provided. The consolidation device is configured to form a build layer of a component. The build platform is configured to rotate about a build platform rotation axis extending along a first direction. The optical detector is configured to detect locations of at least two alignment marks. The controller is configured to receive locations of the at least two alignment marks from the optical detector. The controller is also configured to determine the locations of the build platform rotation axis and a build platform rotation center point based on a comparison between the at least two alignment marks, wherein the build platform rotation center point lies along the build platform rotation axis. The controller is further configured to control the consolidation device to consolidate a plurality of particles on the build platform.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 14, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Brian Scott McCarthy, Subhrajit Roychowdhury, Mohammed Shalaby, Victor Petrovich Ostroverkhov, Michael Evans Graham, William Thomas Carter
  • Patent number: 10290646
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. The semiconductor device may include second channel layers adjacent to the first channel layers in a second direction crossing the first direction and arranged in the first direction. The semiconductor device may include insulating layers stacked while surrounding side walls of the first and second channel layers. The semiconductor device may include conductive layers interposed between the insulating layers, and including first metal patterns extended in the first direction and second metal patterns extended in the first direction while surrounding the side walls of the first channel layers.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventor: Do Youn Kim
  • Patent number: 10269815
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: ShihKuang Yang, Hung-Ling Shih, Chieh-Fei Chiu, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair
  • Patent number: 10249477
    Abstract: An ion implanter includes a plasma shower device configured to supply electrons to an ion beam with which a wafer is irradiated. The plasma shower device includes a plasma generating chamber provided with an extraction opening, a first electrode which is provided with an opening communicating with the extraction opening and to which a first voltage is applied with respect to an electric potential of the plasma generating chamber, a second electrode which is disposed at a position facing the first electrode such that the ion beam is interposed between the first and second electrodes and to which a second voltage is applied with respect to the electric potential of the plasma generating chamber, and a controller configured to independently control the first voltage and the second voltage to switch operation modes of the plasma shower device.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 2, 2019
    Assignee: SUMITOMO HEAVY INDUSTRIES ION TECHNOLOGY CO., LTD.
    Inventors: Syuta Ochi, Shiro Ninomiya, Yuuji Takahashi, Tadanobu Kagawa
  • Patent number: 10217860
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: February 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 10211286
    Abstract: A first parallel pn layer having a first n-type region and a first p-type region junctioned alternately and repeatedly is disposed in an element active portion. The first parallel pn layer has a striped planar layout. A second parallel pn layer having a second n-type region and a second p-type region junctioned alternately and repeatedly is disposed in a high voltage structure. The second parallel pn layer has a striped planar layout in a direction identical to that of the first parallel pn layer. An intermediate region having a third parallel pn layer and a fourth parallel pn layer of a lower impurity quantity than the first parallel pn layer is disposed between the first and second parallel pn layers, and formed by diffusing impurity implanting regions becoming the first and the second parallel pn layers formed separated from each other to a region in which no impurity is ion-implanted.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshiaki Sakata, Yasushi Niimura, Shunji Takenoiri
  • Patent number: 10199257
    Abstract: Embodiments of the disclosure include a fixed position mask for workpiece edge treatment. In some embodiments, an apparatus includes a roplat having a rotatable assembly, and a platen coupled to the rotatable assembly, wherein the platen is configured to hold a workpiece. The apparatus further includes a bracket affixed to the rotatable assembly, and a mask directly coupled to the bracket, wherein the mask is positioned adjacent the workpiece. The mask covers an inner portion of the platen and the workpiece, leaving just an outer circumferential edge of the workpiece exposed to an ion treatment. In some embodiments, the platen is permitted to rotate relative to the bracket during an ion treatment. In some embodiments, the mask includes a solid plate section devoid of any openings, and a mounting portion extending from the plate section, wherein the mounting portion is directly coupled to an extension arm of the bracket.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Fletcher Ian Potter, Philip Layne, Keith A. Fernlund, Michael Swears, Richard Allen Sprenkle
  • Patent number: 10186612
    Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: January 22, 2019
    Assignee: NXP USA, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 10077192
    Abstract: Production of highly pure comminuted polycrystalline silicon from polycrystalline silicon rods produced by the Siemens process is facilitated by removal of graphite residues from the electrode ends of the rods by removing the contaminated end portions by means of mechanical impulses.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: September 18, 2018
    Assignee: WACKER CHEMIE AG
    Inventors: Stefan Faerber, Andreas Bergmann, Reiner Pech, Siegfried Riess
  • Patent number: 10014374
    Abstract: In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Patrick Morrow
  • Patent number: 9972640
    Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 15, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Murshed Chowdhury, Jin Liu, Johann Alsmeier
  • Patent number: 9941364
    Abstract: In embodiments, a high voltage semiconductor device includes a gate structure disposed on a substrate, a source region disposed at a surface portion of the substrate adjacent to one side of the gate structure, a drift region disposed at a surface portion of the substrate adjacent to another side of the gate structure, a drain region disposed at a surface portion of the drift region spaced from the gate structure, and an electrode structure disposed on the drift region to generate a vertical electric field between the gate structure and the drain region.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 10, 2018
    Assignee: DB HITEK CO., LTD.
    Inventors: Jin Hyo Jung, Jung Hyun Lee, Bum Seok Kim, Seung Ha Lee, Chang Hee Kim
  • Patent number: 9899214
    Abstract: The present disclosure provides a method for fabricating a vertical heterojunction of metal chalcogenides. The method includes steps of providing a multi-layer material, performing an ion implantation and performing an annealing. The multi-layer material has a carrier and a metal layer, in which the metal layer covers the carrier to form an interface. The carrier includes an oxide of a first metal element, and the metal layer includes a second metal element. The step of performing the ion implantation is to inject a chalcogen ion source into the multi-layer material to allow a plurality of chalcogen ions to be implanted in a depth area of the multi-layer material, and the depth area includes the interface. The step of performing the annealing is to form a first metal chalcogenide and a second metal chalcogenide at two sides of the interface, respectively.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 20, 2018
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Jenq-Horng Liang, Hsu-Sheng Tsai, Wei-Yen Woon
  • Patent number: 9876089
    Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: January 23, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Jin Cho, MiaoMiao Wang, Hui Zang
  • Patent number: 9627536
    Abstract: A method is provided for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is pattered to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the dopes silicon layer is converted to a porous silicon layer. Following the last step, the silicon shell is tensily stressed, making it a good candidate for use as a channel feature in an n-type field effect transistor.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: April 18, 2017
    Assignee: International Busines Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9614153
    Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu, Theodore M. Taylor, Scott E. Sills
  • Patent number: 9611567
    Abstract: Provided is a method for controlling a donor concentration in a Ga2O3-based single crystal body. In addition, an ohmic contact having a low resistance is formed between a Ga2O3-based single crystal body and an electrode. A donor concentration in a Ga2O3-based single crystal body is controlled by a method which includes a step wherein Si, which serves as a donor impurity, is introduced into the Ga2O3-based single crystal body by an ion implantation method at an implantation concentration of 1×1020 cm?3 or less, so that a donor impurity implanted region is formed in the Ga2O3-based single crystal body, the donor impurity implanted region having a higher donor impurity concentration than the regions into which Si is not implanted, and a step wherein Si in the donor impurity implanted region is activated by annealing, so that a high donor concentration region is formed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 4, 2017
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 9530800
    Abstract: The invention provides an array substrate, a display panel and a method for preparing an array substrate. The array substrate includes multiple low temperature poly-silicon (LTPS) thin film transistors arranged in an array. Each LTPS thin film transistor includes: a substrate; a LTPS layer, a source, a drain and a first conductive layer disposed on a same surface of the substrate, the source and the drain respectively being arranged at two sides of the LTPS layer and electrically connected with the LTPS layer, the drain being electrically connected with the first conductive layer; an insulating layer disposed on the LTPS layer, the source, the drain and the first conductive layer; a gate disposed on the insulating layer and corresponding to the LTPS layer; a passivation layer disposed on the gate; and a second conductive layer disposed on the passivation layer and corresponding to the first conductive layer.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: December 27, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Cong Wang, Peng Du, Lixuan Chen
  • Patent number: 9437418
    Abstract: A method for forming spacers of a transistor gate having an active layer surmounted by the gate, including forming a porous layer covering the gate and having a dielectric constant equal to or less than that of silicon oxide, forming a protective layer covering the porous layer and the gate, etching the protective layer anisotropically to preserve residual portions of the protective gate only at the flanks of the gate, forming a modified layer by penetration of ions within the porous layer anisotropically to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer on the flanks of the gate, the latter being protected by protective spacers constituting porous spacers, and removing the modified layer by etching to leave the protective spacers in place.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: September 6, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Posseme
  • Patent number: 9437392
    Abstract: One embodiment of this ion implanter includes an ion source and a process chamber. This process chamber is connected to the ion source and separated from the ion source by a plurality of extraction electrodes. A carrier holds multiple workpieces. A mask loader in the process chamber connects a mask to the carrier. A transfer chamber and load lock may be connected to the process chamber. The ion implanter is configured to perform either blanket or selective implantation of the workpieces.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: September 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: William T. Weaver, Charles T. Carlson, Joseph C. Olson, James Buonodono, Paul Sullivan
  • Patent number: 9379026
    Abstract: A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ting Lin, Wen-Tai Chiang
  • Patent number: 9378958
    Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang
  • Patent number: 9291660
    Abstract: An apparatus includes a probe card, an alpha particle source and a shutter. The probe card includes a plurality of contact elements. The contact elements define a measuring position. The shutter is arranged between the alpha particle source and the measuring position. The shutter is movable between a closed position and an open position. When the shutter is in the open position, alpha particles from the alpha particle source reach the measuring position. When the shutter is in the closed position, the alpha particles are blocked from reaching the measuring position.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elief Paffrath, Frank Schreiter
  • Patent number: 9275905
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes implanting a first type of dopants in a first region and a second region and implanting a second type of dopants in the second region. In addition, an un-doped silicon layer is formed over the first and second regions, and a first and a second fin structures are formed. The first fin structure includes a first type of anti-punch through structure implanted with the first type of dopants and a first un-doped silicon structure over the first type of anti-punch through structure, and the second fin structure includes a second type of anti-punch through structure implanted with the second type of dopants and a second un-doped silicon structure formed over the second type of anti-punch through structure.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: March 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yao Wen, Jui-Yao Lai, Yao-De Chiou, Sai-Hooi Yeong, Yen-Ming Chen
  • Patent number: 9252191
    Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 2, 2016
    Assignee: Crossbar, Inc.
    Inventors: Mark Harold Clark, Scott Brad Herner
  • Patent number: 9136351
    Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
  • Patent number: 9087774
    Abstract: A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 21, 2015
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Jeesung Jung, Joel M. McGregor, Ji-Hyoung Yoo
  • Patent number: 9059201
    Abstract: Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed. For example, implanting ions through the surface silicon layer on either side of the gate structure of the preferred FET implementation into an underlying stressor layer can induce strain in a channel region of the FET. This process can begin with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: June 16, 2015
    Assignee: Acorn Technologies, Inc.
    Inventor: Paul A. Clifton
  • Patent number: 9041090
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 9040399
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • Patent number: 9034741
    Abstract: A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Keith E. Fogel, Judson R. Holt, Balasubramanian Pranatharthiharan, Alexander Reznicek
  • Patent number: 9029248
    Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: May 12, 2015
    Assignee: EWHA University-Industry Collaboration Foundation
    Inventors: William Jo, Ah-Reum Jeong
  • Patent number: 9024328
    Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 5, 2015
    Assignee: General Electric Company
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Patent number: 9023720
    Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 5, 2015
    Assignee: Sen Corporation
    Inventors: Genshu Fuse, Michiro Sugitani
  • Patent number: 9018069
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a diode. The diode comprises a first doped region, a second doped region and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated from each other by the first doped region. The third doped region has a first portion and a second portion adjacent to each other. The first portion and the second portion are respectively adjacent to and away from the second doped region. A dopant concentration of the first portion is bigger than a dopant concentration of the second portion.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chieh-Chih Chen, Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu
  • Patent number: 9006823
    Abstract: A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: April 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Shinya Yamazaki
  • Patent number: 8993423
    Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a dielectric film on a semiconductor substrate doped with a first conductive type impurity, exposing a high concentration doping region of a predetermined selective emitter by partially removing the dielectric film, and ion-implanting a second conductive type impurity into a front surface of the semiconductor substrate with the dielectric film formed thereon to form a high concentration doping layer in the semiconductor substrate to correspond to the high concentration doping region and to form a low concentration doping layer in the semiconductor substrate to correspond to a region in which the dielectric film is formed.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 31, 2015
    Assignee: Shinshung Solar Energy Co., Ltd.
    Inventors: Ji Soo Kim, Ho Sik Kim, Ji Sun Kim, Jong Youb Lim, Yeon Hee Hwang, Hoon Joo Choi, Jeong Jae Jo
  • Patent number: 8994002
    Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Publication number: 20150084162
    Abstract: An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 26, 2015
    Inventor: T. Jordan Davis
  • Publication number: 20150079773
    Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicants: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nathaniel Berliner, Hyun-Jin Cho, Johnathan Faltermeler, Kam-Leung Lee, Tenko Yamashita
  • Patent number: 8980731
    Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Kim, Sunghae Lee, Hanvit Yang, Dongwoo Kim, Chaeho Kim, Daehyun Jang, Ju-Eun Kim, Yong-Hoon Son, Sangryol Yang, Myoungbum Lee, Kihyun Hwang
  • Publication number: 20150069414
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, and first, second, and third semiconductor regions. The first semiconductor region has a first conductivity type. The first electrode is provided above the first semiconductor region. The second semiconductor region has a second conductivity type and is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the first electrode, and has the second conductivity type. The third semiconductor region has an impurity concentration substantially equal to an impurity concentration of the second semiconductor region, and has first and second portions. The first and second portions constitute a concave-convex form on a side of the first semiconductor region of the third semiconductor region. The second electrode is provided above an opposite side of the first semiconductor region from the first electrode.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kono, Ryoichi Ohara
  • Patent number: 8963296
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 24, 2015
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8962460
    Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu, Theodore M. Taylor, Scott E. Sills
  • Publication number: 20150048489
    Abstract: Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Anant Kumar Agarwal
  • Publication number: 20150041892
    Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a source region disposed apart from a drain region, a first body region surrounding the source region, a deep well region disposed below the drain region, and a second body region disposed below the first body region. A bottom surface of the second body region is not coplanar with a bottom surface of the deep well region, and the first body region has a different conductivity type from the second body region.
    Type: Application
    Filed: March 18, 2014
    Publication date: February 12, 2015
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Francois HEBERT, I-Shan SUN, Youngbae KIM, Youngju KIM, Kwangil KIM, Intaek OH, Jinwoo MOON
  • Patent number: 8951896
    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Jeffrey E. Hanrahan, Mark D. Jaffe, Alvin J. Joseph, Dale W. Martin, Gerd Pfeiffer, James A. Slinkman
  • Patent number: 8951895
    Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 10, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin Andrew Brenner, Raghunath Murali