Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Abstract: A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Abstract: The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (103) is formed on a substrate (101), the method including: a substrate processing step of forming, on the (0001) C-plane of the substrate (101), a plurality of convex parts (12) of surfaces (12c) not parallel to the C-plane, to thereby form, on the substrate, an upper surface (10) that is composed of the convex parts (12) and a flat surface (11) of the C-plane; and an epitaxial step of epitaxially growing the group III nitride semiconductor layer (103) on the upper surface (10), to thereby embed the convex parts (12) in the group III nitride semiconductor layer (103).

Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.

Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.

Abstract: Monolithic IC/MEMS processes are disclosed in which high-stress silicon nitride is used as a mechanical material while amorphous silicon serves as a sacrificial layer. Electronic circuits and micro-electromechanical devices are built on separate areas of a single wafer. The sequence of IC and MEMS process steps is designed to prevent alteration of partially completed circuits and devices by subsequent high process temperatures.

Abstract: Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such particles. Methods of forming semiconductor devices include subjecting single source precursors to carbon dioxide to form particles of semiconductor material, and establishing electrical contact between the particles and an electrode.

Abstract: A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.

Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.

Abstract: Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.

Abstract: A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.

Abstract: A method of manufacturing a semiconductor device which includes a gate electrode formed in the shape substantially vertical to a semiconductor substrate is disclosed. A gate electrode is formed by anisotropically etching a gate electrode film having a metal-containing film formed on the semiconductor substrate via a gate insulating film to expose a portion of the gate insulating film. A modified film is formed on a side wall of the metal-containing film by modifying the side wall of the metal-containing film. The exposed portion of the gate insulating film is removed and a portion of the gate insulating film sandwiched between the semiconductor substrate and the metal-containing film is recessed so as to recede from the modified side wall of the metal-containing film by isotropically etching. A side portion of the metal-containing film protruding from the receded gate insulating film is removed by isotropically etching.

Abstract: An electrophoretic display device includes: a transparent substrate positioned at a display side and having a transparent front electrode; a wiring substrate disposed to face the transparent substrate and having a field applying unit; a spacer disposed between the transparent substrate and the wiring substrate and having a plurality of accommodating holes with upper and lower portions open; and a plurality of microcapsules respectively positioned in the plurality of accommodating holes and including a dispersion solvent encapsulated with a plurality of charged particles contained therein, wherein the accommodating holes comprise upper holes with a width for receiving the microcapsules and lower holes allowing the microcapsules to be mounted thereon.

Abstract: In a dual stress liner approach, unwanted material provided between closely spaced gate electrode structures may be removed to a significant degree on the basis of a wet chemical etch process, thereby reducing the risk of creating patterning-related irregularities. Consequently, the probability of contact failures in sophisticated interlayer dielectric material systems formed on the basis of a dual stress liner approach may be reduced.

Abstract: A GaN based III-V nitride semiconductor light-emitting device and a method for fabricating the same are provided. In the GaN based III-V nitride semiconductor light-emitting device including first and second electrodes arranged facing opposite directions or the same direction with a high-resistant substrate therebetween and material layers for light emission or lasing, the second electrode directly contacts a region of the outmost material layer exposed through an etched region of the high-resistant substrate. A thermal conductive layer may be formed on the bottom of the high-resistant substrate to cover the exposed region of the outmost material layer.

Abstract: Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.

Abstract: A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. The first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Abstract: A method of processing a substrate through the use of an apparatus, including a substrate carrier for carrying a substrate; a liquid-applying unit for applying chemical to said substrate; and a gas-applying unit for applying gas atmosphere to said substrate, wherein the method includes processing an organic film pattern formed on a substrate, by, in sequence, removing one of an altered layer and a deposited layer formed on the organic film pattern, and fusing said organic film pattern for deformation by applying gas atmosphere to the organic film pattern in the gas-applying unit, wherein at least a part of the removal step is carried out by applying a liquid to the organic film pattern in the liquid-applying unit. The process may include an ashing unit for ashing the substrate and/or a development unit for developing the organic film pattern.

Abstract: Disclosed is a method for reprocessing a semiconductor substrate which is by-produced in manufacturing a silicon-on-insulator substrate. The method includes: forming an embrittlement layer in a single crystal semiconductor substrate; bonding the single crystal semiconductor substrate with a base substrate having an insulating surface; and separating the single crystal semiconductor substrate along the embrittlement layer to give a silicon-on-insulator substrate and a semiconductor substrate to be reprocessed. The above steps provide, in the peripheral portion on the semiconductor substrate, a projection comprising the embrittlement layer and a single crystal semiconductor layer over the embrittlement layer. The method is characterized by an etching step to selectively remove the projection without etching a portion where the projection is absent, which allows the semiconductor substrate to be reused for the production of another silicon-on-insulator substrate.

Abstract: A method for fabricating semiconductor devices includes: (a) forming over a temporary substrate a sacrificial film layer; (b) growing laterally and epitaxially an epitaxial film layer; (c) forming over the epitaxial film layer a patterned mask that covers partially the epitaxial film layer and that defines a plurality of through holes to expose a plurality of epitaxial surface regions, respectively; (d) forming a plurality of conductive members respectively in the through holes and on the epitaxial surface regions; (e) removing the patterned mask and removing a part of the epitaxial film layer and a part of the sacrificial film layer beneath the patterned mask; (f) removing the sacrificial film layer; and (g) removing the temporary substrate.

Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.

Abstract: An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

Abstract: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.

Abstract: The present invention relates to a novel method for roughening an epitaxy structure layer, including: providing an epitaxy structure layer; and etching a surface of the epitaxy structure layer by an excimer laser having an energy density of 1000 mJ/cm2 or less to form a roughened surface. In addition, the present invention further provides a method for manufacturing a light-emitting diode having a roughened surface. Accordingly, the present invention can resolve the conventional problems of process complexity, time consumption and high cost.

Abstract: A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film.

Abstract: A method for manufacturing a semiconductor device includes: a first etching step of etching a TEOS layer from a glass substrate to partially expose a SiN layer; a second etching step, conducted separately and independently from the first etching step, of wet-etching the exposed SiN layer to partially expose the glass substrate; and a bonding step of bonding a driver portion to the exposed glass substrate.

Abstract: A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. A metal layer is formed on a substrate. The multilayer structure is bonded to the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.

Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.

Abstract: The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.

Abstract: A method of forming a material from a source material including the following steps of grinding the source material to get powders if the source material is not already in the form of powders; sintering the powders with at least one compression step and one thermal processing step; and purifying the material with a gas flow, the gas flow passing through the porosity channels of the material.

Abstract: A method for forming a silicon trench, comprises the steps of: defining an etching area at a silicon substrate; forming metal catalysts at the surface of the etching area; immersing the silicon substrate in a first etching solution thereby forming anisotropic silicon nanostructures in the etching area; immersing the silicon substrate in a second etching solution thereby resulting in the silicon nanostructures being side-etched and detached from the silicon substrate, thus forming the silicon trench.

Abstract: With the present invention, two wafers for a solar cell only whose light receiving surfaces are selectively etched can be simultaneously obtained by overlapping the two wafers and performing a single-sided etching or an asymmetric etching thereon. The present invention provides a method of etching a wafer comprising: performing a single-sided etching or an asymmetric etching on the wafer, wherein the performing the single-sided etching or the asymmetric etching comprises: overlapping two wafers whose one sides face each other; and etching the overlapped two wafers, and a solar cell including the etched wafers.

Abstract: A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

Abstract: In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity.

Abstract: Disclosed is a method of structuring a material surface by dry etching, so that a passivation layer soluble in a solvent forms by the dry etching on parts of the structured material surface, sealing the passivation layer with a substance soluble in the solvent, and removing the sealed passivation layer and the substance by means of the solvent.

Abstract: An object of the present invention is to provided a wafer exhibiting excellent surface properties, in which variation in reaction, which has been concerned in surface treatment with a diffusion controlled process such as conventional wet treatment, is effectively suppressed in a method for surface treatment of a wafer involving a chemical treatment. Provided is a method for surface treatment of a wafer involving a chemical treatment, the chemical treatment including a reaction controlled process, and a diffusion controlled process following the reaction controlled process.

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: A manufacturing method of a nitride crystalline film includes following steps. First, a substrate is provided. Next, a first nitride crystalline film is formed on the substrate. A patterned mask is then formed on the first nitride crystalline film. The patterned mask covers a first part of the first nitride crystalline film and exposes a second part of the first nitride crystalline film. Afterwards, the second part is etched, and the first part is maintained. After that, the patterned mask is removed. The first part is then etched to form a plurality of nitride crystal nuclei. Next, a second nitride crystalline film is formed on the substrate, and the second nitride crystalline film is made to cover the nitride crystal nuclei. A nitride film and a substrate structure are also provided.

Abstract: A method for treating semiconductor wafer includes: providing a stack including a high-k layer including a first oxide material, wherein the first oxide material contains hafnium and/or zirconium, and a cap-layer including a second oxide material, wherein the cap-layer has been deposited on top of the high-k layer, wherein the second oxide material contains lanthanum, a lanthanide and/or aluminium; supplying liquid A to the surface of the semiconductor wafer, liquid A being an aqueous solution containing an oxidizing agent; supplying liquid B to the surface of the semiconductor wafer, liquid B being a liquid with a pH-value lower than 6; and conducting a step SC wherein a liquid C is supplied to the surface of the semiconductor wafer, wherein step SC is carried out after step SB, wherein liquid C is an aqueous acidic solution with a fluorine concentration of at least 10 ppm.

Abstract: A non-destructive and simple analytical method is provided which allows in situ monitoring of plasma damage during the plasma processing such as resist stripping. If a low-k film is damaged during plasma processing, one of the reaction products is water, which is remained adsorbed onto the low-k film (into pores), if the temperature is lower than 100-150 C. A plasma (e.g. He) that emits high energy EUV photons (E>20 eV) which is able to destruct water molecules forming electronically excited oxygen atoms is used to detect the adsorbed water. The excited oxygen is detected from optical emission at 777 nm. Therefore, the higher the adsorbed water concentration (higher damage), a more intensive (oxygen) signal is detected. Therefore, intensity of oxygen signal is a measure of plasma damage in the previous strip step.

Abstract: A plurality of substrate processing devices are disposed in a separated manner within a shared ambient environment. A conveyance device is disposed within the shared ambient environment and is defined to move a substrate through and between each of the substrate processing devices in a continuous manner. Some substrate processing devices are defined to perform dry substrate processing operations in which an energized reactive environment is created in exposure to the substrate in an absence of liquid material. Some substrate processing devices are defined to perform wet substrate processing operations in which at least one material in a liquid state is applied to the substrate. In one embodiment, a complementary pair of dry and wet substrate processing devices are disposed in the shared ambient environment in a sequential manner relative to movement of the substrate by the conveyance device.

Abstract: A substrate processing apparatus comprises a processing chamber for storing a boat supporting multiple substrates and for processing the multiple substrates, a heater unit installed around the processing chamber for heating the substrates, and a coolant gas supply nozzle including a pipe section extending perpendicular to a main surface of the substrate supported in the boat stored in the processing chamber, and a spray hole formed on the pipe section for spraying coolant gas to at least two of the multiple substrates, wherein the coolant gas supply nozzle is formed so that the cross sectional area of the pipe section in the area where the spray hole is formed is larger than the total opening area of the spray hole.

Abstract: A manufacturing method of an electro line for a liquid crystal display device includes depositing a barrier layer made of a conducting material on a substrate, depositing a copper layer (Cu) on the barrier layer, wet-etching the Cu layer using a first etchant, and dry-etching the barrier layer using a second etchant using the wet-etched Cu layer as an etch mask.

Abstract: A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.

Abstract: A method of removing carbon doped silicon oxide between metal contacts is provided. A layer of the carbon doped silicon oxide is converted to a layer of silicon oxide by removing the carbon dopant. The converted layer of silicon oxide is selectively wet etched with respect to the carbon doped silicon oxide and the metal contacts, which forms recess between the metal contacts.

Abstract: A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nanostructures.