Abstract: A static random-access memory (SRAM) cell includes a first inverter and a second inverter being cross-coupled; a first access transistor that accesses an output of the first inverter under control of a word line; a second access transistor that accesses an output of the second inverter under control of the word line; a first passage transistor that passes a common-mode voltage, controlled by the output of the first inverter; a second passage transistor that passes an input signal, controlled by the output of the second inverter; and a capacitor switchably coupled to receive the common-mode voltage and the input signal through the first passage transistor and the second passage transistor respectively.

Abstract: Embodiments of the present disclosure relate generally to microfluidic devices and methods of making microfluidic devices. An exemplary method of making a microfluidic device comprises: providing a substrate; depositing, onto the substrate, a hydrophobic material; and etching, into the substrate, at least one hydrophilic channel into the hydrophobic substrate.

Abstract: Defluorination processes for removing fluorine residuals from a workpiece such as a semiconductor wafer are provided. In one example implementation, a method for processing a workpiece can include supporting a workpiece on a workpiece support. The workpiece can have a photoresist layer. The workpiece can have one or more fluorine residuals on a surface of the workpiece. The method can include performing a defluorination process on the workpiece at least in part using a plasma generated from a first process gas. The first process gas can include a hydrogen gas. Subsequent to performing the defluorination process, the method can include performing a plasma strip process on the workpiece to at least partially remove a photoresist layer from the workpiece.

Abstract: A substrate processing apparatus includes a chemical liquid nozzle 31 that includes a chemical liquid discharge port 95 discharging a chemical liquid in a chemical liquid discharge direction D1, inclined with respect to an upper surface of a substrate W, toward a target position P1 within the upper surface of the substrate W, a spray shield 101 that includes a shield surface 104 directly opposing the upper surface of the substrate W and with which the shield surface 104 overlaps with the target position P1 in plan view and, when the chemical liquid nozzle 31 and the shield surface 104 are viewed from below, all portions of the chemical liquid discharge port 95 are disposed at an outer side of an outer edge of the shield surface 104 or on the outer edge of the shield surface 104, and a nozzle moving unit 38 that moves the chemical liquid nozzle 31 together with the spray shield 101.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Abstract: A testing head for testing the functionality of an electronic device is disclosed having a plurality of contact probes including a probe body extended between respective end portions adapted to contact respective contact pads, a lower guide provided with guide holes for housing the contact probes, and a conductive portion in the lower guide. The conductive portion includes a group of the guide holes and is adapted to contact and short-circuit a corresponding group of contact probes housed in the group of holes. The contact probes housed in the group of holes include a deformable portion adapted to be partially inserted into the guide holes of the group. The deformable portion, when housed in the guide holes, is in a configuration in which it is deformed by the contact with a wall of the guide holes and exerts on the wall a reaction force ensuring a sliding contact during testing of the electronic device.

Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Abstract: Semiconductor structures and fabrication methods are provided. The method includes providing a to-be-etched layer having first regions, second regions and third regions; forming a first core layer on a first region; forming a first sidewall spacer on sidewalls of the first core layer; forming a sacrificial layer covering a portion of the first sidewall spacer on the to-be-etched layer, having a plurality of initial first openings and with a portion of the initial first opening exposing a portion of the first sidewall spacer on the second region; removing the portion of the first sidewall spacer exposed by the portion of the initial first opening to form a first opening; forming a second sidewall spacer in the first opening; and forming second openings in the sacrificial layer. The second openings expose one of or both a portion of the first sidewall spacer and a portion of the second sidewall spacer.

Abstract: A system that predicts an apparatus state of a plasma processing apparatus including a processing chamber in which a sample is processed is configured to have a data recording unit that records emission data of plasma during processing of the sample and electrical signal data obtained from the apparatus during the plasma processing, an arithmetic unit that includes a first calculation unit for calculating a first soundness index value of the plasma processing apparatus and a first threshold for an abnormality determination using a first algorithm with respect to the recorded emission data and a second calculation unit for calculating a second soundness index value of the plasma processing apparatus and a second threshold for the abnormality determination using a second algorithm with respect to the electrical signal data recorded in the data recording unit, and a determination unit that determines soundness of the plasma processing apparatus using the calculated first soundness index value and the first thres

Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

Abstract: A substrate processing method is provided. The method comprises a first step of supplying a processing gas containing a halogen-containing gas and a basic gas to a substrate, which a silicon film is formed on and has a first temperature, and generating a reaction product by deforming a surface of the silicon film; and a second step of removing the reaction product by setting the substrate to a second temperature after the first step.

Abstract: A method can treat a patient suffering from at least one of fibrosis and a fibrotic disorder. The method includes administering a therapeutically effective amount of an anti-?v integrin antibody DI17E6, or a biologically active variant or modification thereof, to the patient.

Abstract: A semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. The drift region and the source area are formed in the semiconductor layer. The well region is formed in the semiconductor layer and between the drift region and the source area. The drain area is formed in the drift region. The dielectric film is formed in the drift region and is located between the source area and the drain area. The dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.

Abstract: A substrate processing apparatus includes: a holding unit that holds a substrate; a liquid discharge unit; a first supply unit; a second supply unit; and a control unit that controls each unit. The liquid discharge unit discharges a processing liquid to the substrate held by the holding unit. The first supply unit supplies the processing liquid to the liquid discharge unit. The second supply unit supplies steam to the liquid discharge unit. The second supply unit includes: a steam generator that generates steam; a supply line; a stabilizing mechanism; a pressure gauge that measures a pressure of the steam flowing through the supply line; and a pressure adjustment mechanism. The control unit controls the pressure adjustment mechanism so that the pressure of the steam measured by the pressure gauge becomes a preset pressure.

Abstract: Embodiments described herein relate to methods for fabricating optical devices. The methods described herein enable the fabrication of one or more optical devices on a substrate with apertures surrounding each of the optical devices having a plurality of structures. One embodiment of the methods described herein includes disposing an aperture material layer on a surface of a substrate, disposing a structure material layer over the apertures and the surface of the substrate, disposing a hardmask over the apertures and the structure material layer, disposing a patterned photoresist over the hardmask, the patterned photoresist defining exposed hardmask portions, removing the exposed hardmask portions to expose structure portions of the structure material layer, and removing the structure portions to form a plurality of structures between the apertures over regions of the surface of the substrate.

Abstract: The embodiment of the application provides a method of manufacturing a semiconductor structure, which comprises the following steps: forming a target layer, a first mask layer, an isolation layer and an intermediate layer sequentially on a substrate, wherein first trench is disposed in the intermediate layer in the first region and second trench is disposed in the intermediate layer in the second region; forming a fill layer, and the difference in the height between the top surface of the fill layer in the first region and in the second region is less than or equal to a first preset value; removing a portion of the fill layer in the first region until the top surface of the sacrificial layer is exposed; removing the sacrificial layer; and etching a portion of the target layer through the first opening, wherein the remaining target layer forms a target pattern.

Abstract: A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming hard masks on the active layer, wherein a first spacing is disposed between two closely spaced hard masks in a predetermined word line region nearest to a predetermined selective gate region, wherein the first spacing is less than a second spacing between any two of the hard masks other than the two closely spaced hard masks; forming spacers on the sidewalls of the hard masks, wherein two spacers on opposite sides of the sidewalls of the closely spaced hard masks merge into a combined spacer; and transferring the patterns of the spacers to the active layer to form word lines. The step of transferring the patterns of the spacers includes transferring the pattern of the combined spacer to the active layer to form a first word line.

Abstract: An etching method of the invention includes: a resist pattern-forming step of forming a resist layer on a target object, the resist layer being formed of a resin, the resist layer having a resist pattern; an etching step of etching the target object via the resist layer having the resist pattern; and a resist protective film-forming step of forming a resist protective film on the resist layer. The etching step is repetitively carried out multiple times. After the etching steps are repetitively carried out multiple times, the resist protective film-forming step is carried out.

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

Abstract: A polishing liquid containing: abrasive grains containing a metal oxide; at least one hydroxy acid compound selected from the group consisting of a hydroxy acid having a structure represented by General Formula (A1) below and a salt thereof; and water: [In the formula, R11 represents a hydrogen atom or a hydroxy group, R12 represents a hydrogen atom, an alkyl group, or an aryl group, n11 represents an integer of 0 or more, and n12 represents an integer of 0 or more; however, a case where both of R11 and R12 are a hydrogen atom is excluded.

Abstract: A substrate processing apparatus 100 includes a processing unit, a reservoir 31, a processing liquid pipe 32, a pump 34, a filter 35, a first flow rate section 36, a first return pipe 51, a first adjustment valve 52, a second return pipe 41, a branch supply pipe 16, a second flow rate section 42, and a controller. The first flow rate section 36 is placed in the processing liquid pipe 32 and measures a flow rate or pressure of the processing liquid flowing through the processing liquid pipe 32. The first adjustment valve 52 is placed in the first return pipe 51 and adjusts a flow rate of the processing liquid flowing through the first return pipe 51. The controller controls an opening degree of the first adjustment valve 52 based on the flow rate or the pressure of the processing liquid measured by the first flow rate section 36.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.

Abstract: An apparatus configured to facilitate identifying a factor for a defect if the defect occurs in a finished surface of the workpiece. An apparatus includes a movement path generation section configured to generate the movement path of the industrial machine when performing a work on a workpiece; a running information acquisition section configured to acquire running information of the industrial machine when performing a work on the workpiece; and an image data generation section configured to generate the image data in which a first point on the movement path corresponding to a change point of first running information, and a second point on the movement path corresponding to a change point of second running information different from the first running information are highlighted on the movement path in display forms visually different from each other.

Abstract: A static random-access memory (SRAM) cell includes a first inverter and a second inverter being cross-coupled; a first access transistor that accesses an output of the first inverter under control of a word line; a second access transistor that accesses an output of the second inverter under control of the word line; a first passage transistor that passes a common-mode voltage, controlled by the output of the first inverter; a second passage transistor that passes an input signal, controlled by the output of the second inverter; and a capacitor switchably coupled to receive the common-mode voltage and the input signal through the first passage transistor and the second passage transistor respectively.

Abstract: A circuit for sensing a current comprises a substrate having a first and a second major surface, the second major surface being opposite to the first major surface. At least one magnetic field sensing element is arranged on the first major surface of the substrate and is suitable for sensing a magnetic field caused by a current flow in a current conductor coupled to the second major surface. The substrate also comprises at least one insulation layer, substantially buried between the first major surface and the second major surface of the substrate.

Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

Abstract: A substrate accommodating device accommodating a substrate transferred by a transfer device having an end effector configured to hold a substrate and a member including a consumable part disposed in a substrate processing apparatus for processing the substrate includes a container. A first opening through which the end effector holding the substrate passes is formed on a sidewall of the container. A recess into which front ends of the end effector are inserted is formed on an inner surface of the container facing the first opening.

Abstract: There is provided a substrate support of a plasma processing apparatus. The substrate support includes a wafer placement surface and a ring placement surface on which a first ring and a second ring disposed at an outer peripheral side of the first ring without overlapping with the first ring in a vertical direction are placed, with a hole at a boundary between the first ring and the second ring. The substrate support further includes a lifter pin having a first holding portion and a second holding portion, the second holding portion being unitary with and extending axially from a base end of the first holding portion and having a protruding portion protruding from an outer circumference of the first holding portion, and a driving mechanism configured to raise and lower the lifter pin.

Abstract: The disclosure provides a transparent display device including a display panel. The display panel includes a display area, a non-display area, and a plurality of pixels. The non-display area is adjacent to the display area. The plurality of pixels are disposed in the display area. A difference between a transmittance of the display area and a transmittance of the non-display area is less than 30% of the transmittance of the display area.

Abstract: A method of providing data on radio frequency pulses in a radio frequency plasma processing system, the method including measuring an electrical parameter within a matching network of the radio frequency plasma processing system; determining an attribute of the measurement of the electrical parameter; defining a first statistic for the attribute of the measurement of the electrical parameter; defining a second statistic based on the first statistic for at least one of a phase and a process; delivering the first statistic and second statistic to a user; and storing the first statistic and the second statistic within the matching network.

Abstract: A substrate processing method is provided, which includes: a sulfuric acid immersing step of immersing a plurality of substrates in a sulfuric acid-containing liquid within a sulfuric acid vessel; a transporting step of taking out the substrates from the sulfuric acid vessel and transporting the substrates to an ozone gas treatment unit; and an ozone exposing step of exposing the substrates transported to the ozone gas treatment unit to an ozone-containing gas. The ozone gas treatment unit may include a gas treatment chamber which accommodates the substrates. The ozone exposing step may include the step of placing the substrates taken out of the sulfuric acid vessel in a treatment space within the gas treatment chamber to expose the substrates to the ozone-containing gas.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: A measurement part controls power supplied to a heater such that a temperature of the heater becomes constant by using a heater controller, and measures the supplied power in an unignited state in which plasma is not ignited and a transient state in which the power supplied to the heater decreases after plasma is ignited. A parameter calculator performs fitting on a calculation model, which includes a heat input amount from the plasma as a parameter, for calculating the power supplied in the transient state by using the power supplied in the unignited state and the transient state and measured by the measurement part, and calculates the heat input amount. An output part configured to output information based on the heat input amount calculated by the parameter calculator.

Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit structure. The integrated circuit structure includes a substrate and a hard mask over the substrate. The hard mask has sidewalls that form a first opening and a second opening exposing an upper surface of the substrate. A block mask is arranged on the hard mask and is set back from the sidewalls of the hard mask. Spacers are disposed over the block mask and have sidewalls that define a spacer opening exposing an upper surface of the block mask. The block mask extends from directly below the spacers to laterally past the sidewalls of the spacers.

Abstract: A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

Abstract: A substrate processing method is provided for removing a resist having a hardened layer from a front surface of a substrate. The substrate processing method includes a hardened-layer removing step and a wet processing step. The hardened-layer removing step includes a heating step of heating the substrate to 150° C. or more and an ozone-gas supplying step of supplying an ozone gas to the front surface of the substrate being heated by the heating step, and the hardened-layer removing step removes the hardened layer by generating an oxygen radical near the front surface of the substrate. The wet processing step removes the resist from the front surface of the substrate by supplying a processing liquid including a sulfuric acid to the front surface of the substrate after the hardened-layer removing step.

Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

Abstract: There is provided a plasma processing apparatus. The apparatus comprises: a chamber body; and a power supply unit configured to output power for exciting a gas supplied to an inside of the chamber body. The power supply unit supplies, as power having a center frequency, a bandwidth, and a carrier pitch respectively corresponding to a set frequency, a set bandwidth, and a set carrier pitch that are indicated by a controller, power which is pulse-modulated so as to be a pulse frequency, a duty ratio, a high level, and a low level respectively corresponding to a set pulse frequency, a set duty ratio, a high-level set power, and a low-level set power indicated by the controller, and in which a pulse on time determined by the set pulse frequency and the set duty ratio is longer than a power fluctuation cycle of the power having the bandwidth.

Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

Abstract: A substrate treatment method according to an embodiment of the present disclosure includes a temperature raising step of raising a temperature of a concentrated sulfuric acid, and a liquid supply step of supplying the concentrated sulfuric acid having the raised temperature to a substrate placed on a substrate processing part.

Abstract: An electrostatic chuck includes a base plate that is made of a metal; a ceramic plate that is fixed to the base plate and configured to adsorb an object by electrostatic force; and a bonding layer that is provided between the base plate and the ceramic plate to bond the base plate and the ceramic plate to each other. The bonding layer is formed of a composite material including the metal forming the base plate and a ceramic forming the ceramic plate.

Abstract: There is provided a technique that includes a precursor vessel in which a liquid precursor is stored; a first heater immersed in the liquid precursor stored in the precursor vessel and configured to heat the liquid precursor; a second heater configured to heat the precursor vessel; a first temperature sensor immersed in the liquid precursor stored in the precursor vessel and configured to measure a temperature of the liquid precursor; a second temperature sensor immersed in the liquid precursor stored in the precursor vessel and configured to measure a temperature of the liquid precursor; and a controller configured to be capable of: controlling the first heater based on the temperature measured by the first temperature sensor; and controlling the second heater based on the temperature measured by the second temperature sensor.

Abstract: According to one embodiment, a wiring fabrication method includes pressing a first template including a first recessed portion and a second recessed portion provided at a bottom of the first recessed portion against a first film to form a first pattern including a first raised portion, corresponding to the first recessed portion, and a second raised portion, corresponding to the second recessed portion. The second raised portion protrudes from the first raised portion once formed. After forming the first pattern, a first wiring, corresponding to the first raised portion, and a via, corresponding to the second raised portion, is formed using the first pattern.

Abstract: A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a step of high pressure bonding.

Abstract: The present application provides a lithium niobate having a p-type nanowire region or an n-type nanowire region and a method for preparing the same. The method includes heating and then cooling a multi-domain lithium niobate crystal to confine hydrogen ions of the multi-domain lithium niobate crystal in domain wall regions; and poling the multi-domain lithium niobate crystal that has been heated by applying a voltage, to reverse a direction of polarization of one or more domains of the multi-domain lithium niobate crystal. The lithium niobate includes a lithium niobate crystal and a p-type nanowire region or an n-type nanowire region located in the lithium niobate crystal and adjacent to a surface of the lithium niobate crystal. The present application also provides a method for converting the charge carrier type of the lithium niobate nanowire region.