Chemical Etching Patents (Class 438/689)
  • Patent number: 11393762
    Abstract: An apparatus system is provided which comprises: a substrate; a metal pillar formed on the substrate, the metal pillar comprising a first section and a second section, wherein the first section of the metal pillar is formed by depositing metal in a first opening of a first photoresist layer, and wherein the second section of the metal pillar is formed by depositing metal in a second opening of a second photoresist layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Sri Chaitra J. Chavali, Liwei Cheng, Siddharth K. Alur, Sheng Li
  • Patent number: 11387071
    Abstract: Apparatus for a multi-source ion beam etching (IBE) system are provided herein. In some embodiments, a multi-source IBE system includes a multi-source lid comprising a multi-source adaptor and a lower chamber adaptor, a plurality of IBE sources coupled to the multi-source adaptor, a rotary shield assembly coupled to a shield motor mechanism configured to rotate the rotary shield, wherein the shield motor mechanism is coupled to a top portion of the multi-source lid, and wherein the rotary shield includes a body that has one IBE source opening formed through the body, and at least one beam conduit that engages the one IBE source opening in the rotary shield on one end, and engages the bottom portion of the IBE sources on the opposite end of the beam conduit.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 12, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Qiwei Liang, Srinivas D Nemani, Ellie Yieh, Douglas Buchberger, Chentsau Chris Ying
  • Patent number: 11367624
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes forming a recess in the first film using the second film as a mask. The second film includes a first layer having carbon and a second layer having carbon formed on the first layer. The second layer has a second carbon density lower than a first carbon density of the first layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Junichi Hashimoto, Kaori Narumiya, Kosuke Horibe, Soichi Yamazaki, Kei Watanabe, Yusuke Kondo, Mitsuhiro Omura, Takehiro Kondoh, Yuya Matsubara, Junya Fujita, Toshiyuki Sasaki
  • Patent number: 11361968
    Abstract: An apparatus and method of processing a workpiece is disclosed, where a coating is applied to a workpiece and the workpiece is subsequently subjected to an etching process. These processes are performed by one semiconductor processing apparatus while the workpiece is scanned relative to the apparatus. A precursor is applied to the workpiece by the apparatus. The apparatus then uses plasma, heat or ultraviolet radiation to activate the precursor to form a coating. After the coating is applied, the apparatus is configured to perform the etching process. In certain embodiments, the etching process is a directional etching process.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Applied Materials, Inc.
    Inventor: Glen F R Gilchrist
  • Patent number: 11346504
    Abstract: A system for dispensing cryogenic liquid includes a container defining an interior with a partition dividing the interior into primary and reserve chambers. Cryogenic liquid within the primary chamber is separated from cryogenic liquid in the reserve chamber. The partition provides a headspace cornrnurrrcation passage. A primary pressure building circuit has an inlet selectively in liquid communication with the primary chamber and an outlet in fluid communication with the headspaces of the primary and reserve chambers. A reserve pressure building circuit has an inlet selectively in liquid communication with the reserve chamber and an outlet in fluid communication with the headspaces of the primary and reserve chambers. An equalizing circuit is selectively in liquid communication with the primary and reserve chambers. A dispensing line is selectively in liquid communication with the primary chamber.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: May 31, 2022
    Assignee: Chart Inc.
    Inventor: Grant Madison
  • Patent number: 11348987
    Abstract: An OLED display substrate, a method of manufacturing the OLED display substrate, and a display device are provided. The OLED display substrate includes a plurality of aperture regions arranged in an array on a base substrate; and a plurality of storage capacitors on the base substrate, an orthographic projection of each storage capacitor of the plurality of storage capacitors on the base substrate having an overlapping region with an orthographic projection of an aperture region corresponding to the storage capacitor in the plurality of aperture regions on the base substrate.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 31, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinling Zhang, Fei Deng
  • Patent number: 11315759
    Abstract: A plasma processing apparatus includes a processing chamber in which a wafer 1 is processed by using plasma, a radio-frequency power supply that supplies radio-frequency power for generating the plasma, a sample table 2 which is arranged in the processing chamber and in which the wafer 1 is mounted, and a DC power supply 106 which is electrically connected to the sample table 2 and which causes the sample table 2 to generate a suction force. The sample table 2 includes a protruded portion 201a that sucks the wafer 1 by the suction force and a level different portion 201b protruding from a lower portion of the protruded portion 201a. A ring 5 that can be in contact with a lower surface of the wafer 1 is provided outside the protruded portion 201a. A space portion 7 formed by the wafer 1, the protruded portion 201a, and the ring 5 is sealed in a state in which the wafer 1 is sucked to an upper surface of the protruded portion 201a of the sample table 2.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 26, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Takamasa Ichino, Kohei Sato, Kazunori Nakamoto
  • Patent number: 11302530
    Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 12, 2022
    Assignees: Cambridge Enterprise Limited, Anvil Semiconductors Limited
    Inventors: David John Wallis, Martin Frentrup, Menno Johannes Kappers, Suman-Lata Sahonta
  • Patent number: 11302634
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Patent number: 11295933
    Abstract: An apparatus for processing a substrate is provided. The apparatus for processing the substrate includes a housing having a process space, a gas supply unit to supply gas into the process space, a support unit including a chuck to support the substrate in the process space and a lower electrode to surround the chuck when viewed from a top, a temperature adjusting plate provided in the housing, a dielectric plate unit coupled to the temperature adjusting plate, and having a dielectric plate disposed in opposite to the substrate supported by the support unit in the process space, and an upper electrode unit coupled to the temperature adjusting plate, and having an upper electrode disposed in opposition to the lower electrode. The dielectric plate unit includes a first base disposed between the dielectric plate and the temperature adjusting plate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 5, 2022
    Assignee: PSK INC.
    Inventors: Geon Jong Kim, Tae Hwan Youn, Jong Chan Lee
  • Patent number: 11270890
    Abstract: Methods for etching features into carbon material using a metal-doped carbon-containing hard mask to reduce and eliminate redeposition of silicon-containing residues are provided herein. Methods involve depositing a metal-doped carbon-containing hard mask over the carbon material prior to etching the carbon material, patterning the metal-doped carbon-containing hard mask, and using the patterned metal-doped carbon-containing hard mask to etch the carbon material such that the use of a silicon-containing mask during etch of the carbon material is eliminated.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 8, 2022
    Assignee: Lam Research Corporation
    Inventors: Amit Jain, Anne Le Gouil, Yasushi Ishikawa
  • Patent number: 11264265
    Abstract: Provided is a lift pin for an epitaxial growth apparatus, which can prevent the back surface of a silicon wafer from being damaged by the lift pin, reduce emission of dust due to the rubbing of the lift pin against the wall surface of a through hole in a susceptor, and prevent peeling of glassy carbon. The lift pin has a straight trunk part to be inserted through the through hole; a head part to be made to abut a silicon wafer; and a cover part covering at least a top of the head part. The straight trunk part and the head part are made of a porous body, the cover part is made of a carbon-based covering material, and at least part of voids of the porous body of the head part is filled with the cover part.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 1, 2022
    Assignee: SUMCO CORPORATION
    Inventor: Masaya Sakurai
  • Patent number: 11264487
    Abstract: A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Yee-Chia Yeo
  • Patent number: 11249393
    Abstract: A method is described for modifying the mechanical properties of NIL materials. The method includes applying an imprint mask to a nano-imprint lithography (NIL) material layer to create an imprinted NIL material layer, with the NIL material layer comprised of a NIL material. The method further includes detaching the imprinted NIL material layer from the imprint mask, with the modulus level of the NIL material below a flexibility threshold to cause a shape of the imprinted NIL material layer to remain unchanged after detachment. The modulus level of the NIL material of the imprinted NIL material layer is increased beyond a strength threshold to create a first imprint layer, with the imprint layer having a structure that remains unaffected by a subsequent process to form a second imprint layer matching a master mold pattern.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 15, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Austin Lane, Matthew E. Colburn, Giuseppe Calafiore, Nihar Ranjan Mohanty
  • Patent number: 11244833
    Abstract: The present disclosure provides a self-aligned two-time forming method capable of preventing sidewalls from being deformed, comprises sequentially growing a first silicon nitride layer, a first silicon oxide layer, a titanium nitride layer, a second silicon oxide layer, a second silicon nitride layer and a polysilicon layer on a via layer from bottom to top; defining a pattern by using the polysilicon layer as a hard mask, and etching the second silicon nitride layer to an upper surface of the second silicon oxide layer to form a plurality of silicon nitride pattern structures from the second silicon nitride layer; forming sidewalls on sidewalls of the plurality of silicon nitride pattern structures; removing the silicon nitride pattern structures in the sidewalls; etching the silicon nitride layer and the titanium nitride layer by using the sidewalls as a hard mask to form a titanium nitride pattern structure.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: February 8, 2022
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Aimei Lin
  • Patent number: 11239176
    Abstract: A package comprising a carrier, an electronic component mounted on the carrier, and an identifier indicative of an origin of the package and being formed on and/or in the carrier is disclosed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jochen Dangelmaier, Klaus Elian
  • Patent number: 11226567
    Abstract: Methods and associated apparatus for reconstructing a free-form geometry of a substrate, the method including: positioning the substrate on a substrate holder configured to retain the substrate under a retaining force that deforms the substrate from its free-form geometry; measuring a height map of the deformed substrate; and reconstructing the free-form geometry of the deformed substrate based on an expected deformation of the substrate by the retaining force and the measured height map.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 18, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Richard Johannes Franciscus Van Haren, Leon Paul Van Dijk, Ilya Malakhovsky, Ronald Henricus Johannes Otten, Mahdi Sadeghinia
  • Patent number: 11198796
    Abstract: A polishing liquid containing abrasive grains, a hydroxy acid, a polyol, a cationic compound, and a liquid medium, in which a zeta potential of the abrasive grains is positive and a weight average molecular weight of the cationic compound is less than 1000.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 14, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tomohiro Iwano, Takaaki Matsumoto, Tomoyasu Hasegawa
  • Patent number: 11183392
    Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
  • Patent number: 11164874
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a dielectric layer on a sidewall of the opening; performing a dry etching process to form a hole in the conductive portion; removing the dielectric layer; and depositing a conductive pattern over the sidewall of the opening and in the hole.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 2, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Chang-Hyeon Nam, Injoon Yeo
  • Patent number: 11152252
    Abstract: An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sean Teehan, Alex J. Varghese
  • Patent number: 11133195
    Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nelson Felix, Ekmini Anuja De Silva, Praveen Joseph, Ashim Dutta
  • Patent number: 11121092
    Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 14, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Lin Chen, Yunfei Liu, Meng Wang
  • Patent number: 11112625
    Abstract: An optical transmission device has a modulator, a first terminal groove, and relay groove. The modulator has a groove on a waveguide formed on a substrate. EO polymer is placed in the groove in the modulator. The modulator modulates light propagated through the waveguide by changing the phase of the light propagated through the waveguide through change of the refractive index of the EO polymer placed in the groove in the modulator by means of an electric signal. The first terminal groove is formed on the substrate and has a width larger than a width of the groove in the modulator. The relay groove is formed on the substrate and communicates with the groove in the modulator and the first terminal groove. Furthermore, the EO polymer is placed in the relay groove and the first terminal groove.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 7, 2021
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Masaki Sugiyama, Tamotsu Akashi
  • Patent number: 11107729
    Abstract: A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11090866
    Abstract: In a an apparatus and a method for manufacturing a stereoscopic shape using a laser and a powder, the apparatus includes a chamber, a powder supplier, a table, a cotter, a first laser head, a first stage, a second laser head and a second stage. The powder supplier provides a predetermined quantity of powder. The powder is sequentially integrated to be a plurality of powder layers in the table. The cotter moves between the powder supplier and the table, and forms the powder to be a predetermined thickness. The first laser head has a first scanner and a first F theta lens, and irradiates a first laser beam to the powder layer. The first stage transfers the first laser head. The second laser head has a second scanner and a second F theta lens, and irradiates a second laser beam. The second stage transfers the second laser head.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: August 17, 2021
    Assignee: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Hyon-kee Sohn, Dong-sig Shin
  • Patent number: 11081432
    Abstract: The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: August 3, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Koshun Saito, Tsuyoshi Tachi
  • Patent number: 11078380
    Abstract: A method of CMP includes providing a slurry solution including ?1 per-compound oxidizer in a concentration between 0.01 M and 2 M with a pH from 2 to 5 or 8 to 11, and ?1 buffering agent which provides a buffering ratio ?1.5 that compares an amount of a strong acid needed to reduce the pH from 9.0 to 3.0 as compared to an amount of strong acid to change the pH from 9.0 to 3.0 without the buffering agent. The slurry solution is exclusive any hard slurry particles or has only soft slurry particles that have throughout a Vickers hardness <300 Kg/mm2 or Mohs Hardness <4. The slurry solution is dispensed on a hard surface having a Vickers hardness >1,000 kg/mm2 is pressed by a polishing pad with the slurry solution in between while rotating the polishing pad relative to the hard surface.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 3, 2021
    Assignees: Entegris, Inc., University of Florida Research Foundation, Inc.
    Inventors: Rajiv K. Singh, Arul Arjunan, Deepika Singh, Chaitanya Ginde, Puneet N. Jawali
  • Patent number: 11073763
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 11043559
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Hsiu Wang, Yean-Zhaw Chen, Ying-Ting Hsia, Jhao-Ping Jiang, Chun-Chih Cheng
  • Patent number: 11036202
    Abstract: Systems and methods for real time semiconductor manufacturing cluster tool health monitoring are provided via an in-situ sensor. In a method embodiment, an operation procedure for pumping/venting load lock (LL), and LL doors facing vacuum transfer module (VTM) and equipment front end module (EFEM), sensor installation location and operation procedure, and data flow and analysis process are provided. The sensor provides real-time data and monitors airborne particle contamination on EFEM, load lock (LL), and VTM, and plurality of process modules (PMs) simultaneously by correlating door open/close time and vent/pump timing in the loadlock to the particle measurement data. The method further provides an operation for determining that a maintenance procedure is recommended on one of the EFEM, the LL, the VTM, or the plurality of PMs based on the real time measurement data, door state data, and using machine learning algorithms.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 15, 2021
    Assignee: Lam Research Corporation
    Inventors: Hossein Sadeghi, Scott Baldwin
  • Patent number: 11004718
    Abstract: Compositions and designs are described for a sectional porous carrier used in processing microelectronics where thin device substrates are affixed by adhesive to the carrier and form an impervious bonded stack that is resistant to thermal and chemical products during processing and is easily handled by a substrate handling vacuum robot, and subsequently allows rapid removal (debonding) in batch operations by directional penetration into sectional porous regions by selective liquids which release the carrier from the device wafer without harm. The invention carrier with porous regions is used for temporary support of thin and fragile device substrates having capabilities of selective penetration of chemical liquids to pass through the porous regions, access and breakdown the bonding adhesive, and allow it to release without damage to the device substrate.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 11, 2021
    Inventors: John Cleaon Moore, Alexander Joseph Brewer, Jared Michael Pettit, Alman XiMin Law
  • Patent number: 11004731
    Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 11, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Yumiko Miyano
  • Patent number: 10994469
    Abstract: A distributed feedback laser having a conjugated dendrimer as the active lasing component, and a method for patterning conjugated dendrimers.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: May 4, 2021
    Assignees: THE UNIVERSITY COURT OF THE UNIVERSITY OF ST. ANDREWS, OXFORD UNIVERSITY INNOVATION LIMITED
    Inventors: Paul Burn, Ifor Samuel, Justin Lawrence, Jonathan Markham
  • Patent number: 10991596
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 10985049
    Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: April 20, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
  • Patent number: 10957580
    Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Wei Liu, Chia-Tien Wu, Wei-Chen Chu
  • Patent number: 10957595
    Abstract: A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 23, 2021
    Assignee: Cerebras Systems Inc.
    Inventor: Jean-Philippe Fricker
  • Patent number: 10948412
    Abstract: Particularly provided is a method and a system for screening nanoparticles which allow effective search of conditions for surface modification of nanoparticles and reduction in the time, the labor, and the amount of a sample required for the surface modification compared with conventional techniques. The method for screening nanoparticles includes the steps of: dividing a nanoparticle suspension for a respective plurality of containers provided in a containment receptacle; performing surface modification on nanoparticles under different conditions for the respective containers; preparing evaluation samples by adding a dispersion medium into each container and mixing the nanoparticles and the dispersion medium; and performing evaluation on the evaluation sample in each container by optical analysis.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 16, 2021
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, NS MATERIALS INC.
    Inventors: Hiroyuki Nakamura, Maki Saeki, Masanori Tanaka, Eiichi Kanaumi
  • Patent number: 10950506
    Abstract: Fabrication methods and resulting structures for single and double diffusion breaks are provided. Aspects include forming one or more fins on a substrate, the substrate including a first region and a second region, forming a plurality of sacrificial gate structures over channel regions associated with the one or more fins, forming a single diffusion break cavity in the first region of the substrate, forming a double diffusion break cavity in the second region of the substrate, depositing a first dielectric material in the single diffusion break cavity, and depositing a second dielectric material in the double diffusion break cavity.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Juntao Li, Kangguo Cheng, Junli Wang
  • Patent number: 10943791
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
  • Patent number: 10942446
    Abstract: Disclosed is a method for cleaning a photo mask. The method includes a pre-treatment operation of wetting a chemical on an entire surface of the photo mask in a state in which the photo mask is stopped, and a cleaning operation of supplying the chemical to a pattern area of the photo mask in a state in which the photo mask is rotated.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 9, 2021
    Assignee: SEMES CO. LTD.
    Inventors: Seong Soo Lee, Jeong Yeong Park, Sung Bum Park, Byung Chul Kang
  • Patent number: 10934614
    Abstract: A vapor deposition mask (100) includes a resin layer (10) including a plurality of openings (11); a magnetic metal layer (20) located so as to overlap the resin layer, the magnetic metal layer including a mask portion (20a) having such a shape as to expose the plurality of openings and a peripheral portion (20b) located so as to enclose the mask portion; and a frame (30) secured to the peripheral portion of the magnetic metal layer. The resin layer is not joined to the mask portion of the magnetic metal layer but is joined to at least a part of the peripheral portion of the magnetic metal layer.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 2, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Susumu Sakio, Katsuhiko Kishimoto, Koshi Nishida, Kozo Yano
  • Patent number: 10923446
    Abstract: A metallic etching process includes applying an anti-reflection coating over a metallic superstrate, applying a dry film photoresist over the anti-reflection coating, removing exposed portions of the dry film photoresist exposing a portion of the anti-reflection coating, etching the exposed portions of the anti-reflection coating exposing portions of the metal superstrate, etching portions of the metallic superstrate not covered by the dry film photoresist, and removing the dry film photoresist and the anti-reflection coating leaving portions of the metallic superstrate. An indium bump liftoff process includes applying a positive photoresist, forming a liftoff mask by applying a dry film photoresist over the positive photoresist, removing exposed portions of the liftoff mask to expose a portion of a substrate, depositing an indium film over the exposed portion of the substrate and remaining portions of the liftoff mask, and removing remaining portions of the liftoff mask.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 16, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: Ari Brown, Vilem Mikula
  • Patent number: 10923327
    Abstract: Embodiments described herein generally relate to apparatus and methods for processing a substrate utilizing a high radio frequency (RF) power. The high RF power enables deposition of films on the substrate with more desirable properties. A first plurality of insulating members is disposed on a plurality of brackets and extends laterally inward from a chamber body. A second plurality of insulating members is disposed on the chamber body and extends from the first plurality of insulating members to a support surface of the chamber body. The insulating members reduce the occurrence of arcing between the plasma and the chamber body.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jianheng Li, Lai Zhao, Robin L. Tiner, Allen K. Lau, Gaku Furuta, Soo Young Choi
  • Patent number: 10923357
    Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Noriyuki Matsubara, Shogo Okita
  • Patent number: 10907073
    Abstract: A polishing composition for use in polishing an object to be polished, which comprises abrasive grains, a dispersing medium, and an additive, wherein the abrasive grains are surface-modified, the additive is represented by the following formula 1: wherein in the formula 1, X1 is O or NR4, X2 is a single bond or NR5, R1 to R5 are each independently a hydrogen atom; a hydroxy group; a nitro group; a nitroso group; a C1-4 alkyl group optionally substituted with a carboxyl group, an amino group, or a hydroxy group; or CONH2; with the proviso that R2 and R5 may form a ring; when X2 is a single bond, R3 is not a hydrogen atom, or R1 to R3 are not a methyl group; and when X2 is NR5 and three of R1 to R3 and R5 are a hydrogen atom, the other one is not a hydrogen atom or a methyl group; and a pH is 5.0 or less.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 2, 2021
    Inventors: Satoru Yarita, Yukinobu Yoshizaki
  • Patent number: 10903110
    Abstract: A method of forming fine interconnection includes: forming spacers on a first and second hard mask layer on a dielectric layer; forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer; oxidizing a sidewall of the first hard mask layer that surrounding the via hole; forming a second via hole in the second hard mask layer; forming a mask to cover the first hard mask layer in the second via hole; forming a line trench in a portion of the second hard mask layer exposed by the spacers and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and forming a conductive material in the line trench and the first via hole.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 26, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10886428
    Abstract: A method of manufacturing a semiconductor element includes: a first providing step comprising providing a structure body comprising a semiconductor stacked body, the structure body including first surfaces that include surfaces defining at least one first recess; a first forming step comprising forming a first rough-surface portion at or inward of at least a portion of the surfaces defining the first recess of the structure body; a second forming step comprising forming a first metal layer at a first surface side of the structure body; a second providing step comprising providing a substrate on which a second metal layer is disposed; and a bonding step comprising heating the first metal layer and the second metal layer in a state in which the first metal layer and the second metal layer face each other.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Hashizume, Eiji Muramoto, Nobuyoshi Niki
  • Patent number: 10886182
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang, Tzu-Chiang Chen