Chemical Etching Patents (Class 438/689)
  • Patent number: 10700071
    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
  • Patent number: 10678007
    Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 9, 2020
    Assignees: IMEC VZW, Universiteit Gent
    Inventors: Joris Van Campenhout, Bernardette Kunert, Maria Ioanna Pantouvaki, Dries Van Thourhout, Yuting Shi
  • Patent number: 10677656
    Abstract: A device is disclosed including a substrate and a floating blinded infrared detector and/or a shunted blinded infrared detector. The floating blinded infrared detector may include an infrared detector coupled to and thermally isolated from the substrate; and a blocking structure disposed above the infrared detector to block external thermal radiation from being received by the infrared detector; and wherein the blocking structure comprises a plurality of openings. The shunted blinded infrared detector may include an additional infrared detector coupled to the substrate; an additional blocking structure disposed above the infrared detector to block external thermal radiation from being received by the additional infrared detector; and a material that thermally couples the additional infrared detector to the substrate and the additional blocking structure. Methods for using and forming the device are also disclosed.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 9, 2020
    Assignee: FLIR Systems, Inc.
    Inventors: Eric A. Kurth, Chris Chan, Kevin Peters, Patrick Franklin, Robert F. Cannata, James L. Dale, Tommy Marx, David Howard, Jefferson Rose, Michael DeBar
  • Patent number: 10672796
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 10658194
    Abstract: A method for processing a substrate in a processing chamber, comprising forming a deposition over the substrate is provided. A silicon containing gas is flowed into the processing chamber. A COS containing gas is flowed into the processing chamber. A plasma is formed from the silicon containing gas and the COS containing gas in the processing chamber, wherein the plasma provides the deposition over the substrate.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 19, 2020
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qing Xu, Qian Fu, Hua Xiang, Lin Zhao
  • Patent number: 10658473
    Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface. A gate stack passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Patent number: 10639766
    Abstract: Described are materials and methods for processing (polishing or planarizing) a substrate that contains pattern dielectric material using a polishing composition (aka “slurry”) and an abrasive pad, e.g., CMP processing.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Viet Lam, Ji Cui
  • Patent number: 10640679
    Abstract: The invention provides a chemical-mechanical polishing composition containing a ceria abrasive, a polyhydroxy aromatic carboxylic acid, an ionic polymer of formula I: wherein X1 and X2, Z1 and Z2, R1, R2, R3, and R4, and n are as defined herein, and water, wherein the polishing composition has a pH of about 1 to about 4.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon oxide, silicon nitride, and/or polysilicon.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 5, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Sudeep Pallikkara Kuttiatoor, Charles Hamilton, Kevin P. Dockery
  • Patent number: 10619075
    Abstract: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a self-stopping agent, an aqueous carrier, and optionally, a cationic polymer, and provides a method suitable for polishing a substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 14, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Juyeon Chang, Tina C. Li, Viet Lam, Ji Cui, Sarah Brosnan, Chul Woo Nam
  • Patent number: 10619076
    Abstract: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a self-stopping agent, an aqueous carrier, and optionally, a cationic polymer, and provides a method suitable for polishing a substrate.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Juyeon Chang, Tina C. Li, Viet Lam, Ji Cui, Sarah Brosnan, Chul Woo Nam
  • Patent number: 10586591
    Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra Sadana
  • Patent number: 10580886
    Abstract: The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chi-Chun Liu, Chun Wing Yeung, Chen Zhang
  • Patent number: 10577706
    Abstract: A plating apparatus includes a processing bath configured to store a processing liquid therein, a transporter configured to immerse a substrate holder, holding a substrate, in the processing liquid, raise the substrate holder out of the processing bath, and transport the substrate holder in a horizontal direction, and a gas flow generator configured to generate a clean gas flow forward of the substrate with respect to a direction in which the substrate holder is transported. The transporter moves the gas flow generator together with the substrate holder in the horizontal direction while transporting the substrate holder in the horizontal direction.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: March 3, 2020
    Assignee: EBARA CORPORATION
    Inventor: Tomonori Hirao
  • Patent number: 10572091
    Abstract: The present application discloses a touch substrate including a base substrate, and a touch electrode layer on the base substrate having a first region having a plurality of first mesh electrode patterns, a second region having a plurality of second mesh electrode patterns corresponding to the plurality of first mesh electrode patterns, and an interface region between the first region and the second region. Each of the plurality of first mesh electrode patterns includes a plurality of first mesh electrode lines having a first line width. A corresponding second mesh electrode pattern includes a plurality of second mesh electrode lines corresponding to the plurality of first mesh electrode lines and having the first line width. The first mesh electrode line in the interface region has a second line width no less than the first line width.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 25, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaodong Xie, Xibin Shao, Ming Hu, Ming Zhang, Jing Wang
  • Patent number: 10563300
    Abstract: A method is employed to separate a carbon structure, which is disposed on a seed structure, from the seed structure. In the method, a carbon structure is deposited on the seed structure in a process chamber of a CVD reactor. The substrate comprising the seed structure (2) and the carbon structure (1) is heated to a process temperature. At least one etching gas is injected into the process chamber, the etching gas having the chemical formula AOmXn, AOmXnYp or AmXn, wherein A is selected from a group of elements that includes S, C and N, wherein O is oxygen, wherein X and Y are different halogens, and wherein m, n and p are natural numbers greater than zero. Through a chemical reaction with the etching gas, the seed structure is converted into a gaseous reaction product. A carrier gas flow is used to remove the gaseous reaction product from the process chamber.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: February 18, 2020
    Assignee: AIXTRON SE
    Inventors: Kenneth B. K. Teo, Alexandre Jouvray, Jai Matharu, Simon Thomas
  • Patent number: 10566477
    Abstract: Provided are a method of manufacturing a flexible device and the flexible device, a solar cell, and a light emitting device. The method of manufacturing a flexible device includes providing a device layer on a sacrificial substrate, contacting a flexible substrate on one side surface of the device layer, and removing the sacrificial substrate. A large area device may be transferred onto the flexible substrate with superior alignment to realize and manufacture the flexible device. In addition, since mass production is possible, the economic feasibility may be superior. Also, when a large area solar cell having a thin thickness is manufactured, since a limitation such as twisting of a thin film of a solar cell may be effectively solved, the economic feasibility and stability may be superior.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 18, 2020
    Assignees: SK Siltron Co., Ltd., Korea Advanced Institute of Science Technology
    Inventors: Keon Jae Lee, Sang Yong Lee
  • Patent number: 10541318
    Abstract: Semiconductor devices and methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
  • Patent number: 10535530
    Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
  • Patent number: 10527896
    Abstract: Various circuits may benefit from suitable protection. For example, certain displays, such as active matrix liquid crystal displays, may benefit from enclosures configured to protect driver circuits from high intensity radiated fields. A system can include a first protective conductive coating layer. The system can also include a first insulating layer on the first protective conductive layer. The system can further include a signal conductive layer on the insulating layer. The system can additionally include a driver layer mounted to the signal conductive layer. The system can also include a second insulating layer above the driver layer. The system can further include a second protective conductive coating layer on the second insulating layer. The system can additionally include one or a plurality of conductive elements disposed between the first protective conductive coating layer and the second protective conductive coating layer to form an enclosure around the driver layer.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 7, 2020
    Assignee: L3 TECHNOLOGIES, INC.
    Inventors: Michael G. Abernathy, Mark W. Fletcher, Sanjay Tripathi
  • Patent number: 10510839
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Hsiu Wang, Yean-Zhaw Chen, Ying-Ting Hsia, Jhao-Ping Jiang, Chun-Chih Cheng
  • Patent number: 10501660
    Abstract: Provided is a slurry composition including abrasive particles, halogen oxide, and nitroxide compound. The combination of halogen oxide and nitroxide compound has a synergistic effect to remove a substrate containing tungsten and silicon oxide. Moreover, a use of the slurry composition and a polishing method using the slurry composition are provided.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 10, 2019
    Assignee: UWIZ Technology Co., Ltd.
    Inventors: Yun-Lung Ho, Chung-Wei Chiang, Song-Yuan Chang, Ming-Hui Lu, Ming-Che Ho
  • Patent number: 10504838
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Troy R. Sorensen
  • Patent number: 10483128
    Abstract: Epitaxial wafers with a high concentration of BMD nuclei or developed BMDs just below a denuded zone, and having low surface roughness, are produced by forming an oxynitride layer on a purposefully oxidized epitaxial layer by a short RTA treatment in a nitriding atmosphere, removing the oxynitride layer, and then polishing the epitaxial surface.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 19, 2019
    Assignee: SILTRONIC AG
    Inventors: Timo Mueller, Michael Gehmlich, Frank Faller
  • Patent number: 10479938
    Abstract: Methods include exposing polysilicon to an aqueous composition comprising nitric acid, poly-carboxylic acid and ammonium fluoride, and removing a portion of the polysilicon selective to an oxide using the aqueous composition.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu
  • Patent number: 10483108
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Patent number: 10475662
    Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Wei-Hsin Liu, Ying-Chih Lin, Jui-Min Lee, Gang-Yi Lin, Fu-Che Lee
  • Patent number: 10470312
    Abstract: There is provided a method for forming an electrically conductive ultrafine pattern which has an excellent pattern cross-sectional shape is provided by a composite technique including a printing process and a plating process, and furthermore, by imparting excellent adhesion to each interface of a laminate including a plating core pattern, an electrically conductive ultrafine pattern which can be preferably used as a highly accurate electric circuit and a method for manufacturing the same are also provided. The method includes (1) a step of applying a resin composition to form a receiving layer on a substrate; (2) a step of printing an ink containing plating core particles by a reverse offset printing method to form a plating core pattern on the receiving layer; and (3) a step of depositing a metal on the plating core pattern formed in the step (2) by an electrolytic plating method.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 5, 2019
    Assignee: DIC CORPORATION (TOKYO)
    Inventors: Sunao Yoshihara, Haruhiko Katsuta, Yoshinori Katayama, Jun Shirakami, Akira Murakawa, Wataru Fujikawa, Yukie Saitou
  • Patent number: 10468246
    Abstract: A method of preparing a diamond crystal substrate for epitaxial deposition thereupon of a delta doping layer includes preparing an atomically smooth, undamaged diamond crystal substrate surface, which can be in the (100) plane, by polishing the surface and then etching the surface to remove subsurface damage caused by the polishing. The polishing can include a rough polish, for example in the (010) direction, followed by a fine polish, for example in the (011) direction, that removes the polishing tracks from the rough polishing. After etching the polished face can have a roughness Sa of less than 0.3 nm. An inductively coupled reactive ion etcher can apply the etching at a homogeneous etch rate using an appropriate gas mixture such as using argon and chlorine to remove between 0.1 and 10 microns of material from the polished surface.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 5, 2019
    Assignee: Euclid Techlabs, LLC
    Inventor: James E Butler
  • Patent number: 10460930
    Abstract: Methods and apparatuses for selectively depositing silicon oxide on dielectric surfaces relative to a metal-containing surface such as copper are provided. Methods involve exposing a substrate having dielectric and copper surfaces to a copper-blocking reagent such as an alkyl thiol to selectively adsorb to the copper surface, exposing the substrate to a silicon-containing precursor for depositing silicon oxide, exposing the substrate to a weak oxidant gas and igniting a plasma to convert the adsorb silicon-containing precursor to form silicon oxide, and exposing the substrate to a reducing agent to reduce any oxidized copper from exposure to the weak oxidant gas.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 29, 2019
    Assignee: Lam Research Corporation
    Inventors: Dennis M. Hausmann, Alexander R. Fox, Colleen Lawlor
  • Patent number: 10449577
    Abstract: A substrate processing apparatus includes a chamber, a substrate holding unit, an elevated/lowered member, and an elevation/lowering driving unit. The chamber includes a base plate having an upper surface that defines a housing space. The substrate holding unit is housed in the housing space, is placed on the upper surface of the base plate, and holds a substrate. The elevated/lowered member is elevated and lowered inside the housing space. The elevation/lowering driving unit drives the elevation and lowering of the elevated/lowered member. The elevation/lowering driving unit includes a driving source, disposed higher than a lower surface of the base plate, and an elevating/lowering head, which is connected to a guard and is moved vertically by the driving source within a movable range in which an entirety of the head is positioned higher than the lower surface of the base plate.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 22, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Koji Hashimoto
  • Patent number: 10446437
    Abstract: Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chin-Cheng Yang
  • Patent number: 10424506
    Abstract: Integrated circuits, as well as methods of their formation, include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tyler G. Hansen, Ming-Chuan Yang, Vishal Sipani
  • Patent number: 10424508
    Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 24, 2019
    Assignee: Delta Electronics, inc.
    Inventors: Hsin-Chang Tsai, Peng-Hsin Lee
  • Patent number: 10410886
    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a lower mold layer on a substrate that includes first and second regions, forming first and second intermediate mold patterns on the first and second regions, respectively, forming first spacers on sidewalls of the first and second intermediate mold patterns, etching the lower mold layer to form first and second lower mold patterns on the first and second regions, respectively, and etching the substrate to form active patterns and dummy patterns on the first and second regions, respectively. A first distance between a pair of the first intermediate mold patterns may be greater than a second distance between a pair of the second intermediate mold patterns, and the second lower mold patterns may include at least one first merged pattern, whose width is substantially equal to the second distance.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: TaeYong Kwon, Sangjin Kim, Donghoon Hwang, Sebeom Oh, Yunkyeong Jang
  • Patent number: 10403518
    Abstract: A plasma processing method includes etching a removing target film by supplying onto a peripheral portion of a substrate being rotated a first processing liquid containing hydrofluoric acid and nitric acid at a first mixing ratio; and etching the removing target film by, after supplying the first processing liquid onto the substrate, supplying onto the peripheral portion of the substrate being rotated a second processing liquid containing the hydrofluoric acid and the nitric acid at a second mixing ratio in which a content ratio of the hydrofluoric acid is lower and a content ratio of the nitric acid is higher than in the first processing liquid. When removing the removing target film made of SiGe, amorphous silicon or polysilicon from the peripheral portion thereof, an underlying film, for example, a film made of SiO2, which exists under the removing target film, can be appropriately left.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 3, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiromitsu Nanba, Tatsuhiro Ueki
  • Patent number: 10396177
    Abstract: Methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
  • Patent number: 10373828
    Abstract: According to one embodiment, a substrate processing method includes providing a substrate containing Si raised features, depositing a conformal film on the Si raised features, and performing a spacer etch process that removes horizontal portions of the conformal film while substantially leaving vertical portions of the conformal film to form sidewall spacers on the Si raised features, the performing including a) exposing the substrate to a plasma-excited first process gas consisting of H2 gas and optionally an inert gas, and b) exposing the substrate to a plasma-excited second process gas containing i) NF3, O2, H2, and Ar, ii) NF3, O2, and H2, iii) NF3 and O2, iv) NF3, O2, and Ar, v) NF3 and H2, or vi) NF3, H2, and Ar. The method further includes removing the Si raised features while maintaining the sidewall spacers on the substrate. The removing may be performed using steps a) and b).
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: August 6, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Sonam D. Sherpa
  • Patent number: 10365562
    Abstract: Organic coating compositions, particularly antireflective coating compositions, are provided that comprise that comprise a component that comprises one or more uracil moieties. Preferred compositions of the invention are useful to reduce reflection of exposing radiation from a substrate back into an overcoated photoresist layer and/or function as a planarizing, conformal or via-fill layer.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 30, 2019
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Owendi Ongayi, Vipul Jain, Suzanne Coley, Anthony Zampini
  • Patent number: 10347604
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Yagyu, Seiya Isozaki
  • Patent number: 10319604
    Abstract: Processing methods comprising depositing a film on a substrate surface and in a surface feature with chemical planarization to remove the film from the substrate surface, leaving the film in the feature. A pillar is grown from the film so that the pillar grows orthogonally to the substrate surface.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 11, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Ziqing Duan, Yihong Chen, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10297496
    Abstract: In a method for processing a target object including a conductive layer and an insulating film formed on the conductive layer, the insulating film is etched by plasma treatment of a fluorine-containing gas to form an opening in the insulating film. A barrier film is formed to cover a surface of the insulating film and a surface of the conductive layer which is exposed through the opening formed in the insulating film. The target object having the barrier film is placed in an atmospheric environment, and the barrier film is removed from the target object by isotropically etching the barrier film. The target object is maintained in a depressurized environment from start of etching the insulating film to end of forming the barrier film. The barrier film is conformally formed on the surfaces of the insulating film and the conductive layer exposed through the opening formed in the insulating film.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 21, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasutaka Hama, Seiji Yokoyama
  • Patent number: 10292384
    Abstract: The method comprises contacting a silicon substrate with a silver salt and an acid for a time effective to produce spikes having a first end disposed on the silicon substrate and a second end extending away from the silicon substrate. The spikes have a second end diameter of about 10 nm to about 200 nm, a height of about 100 nm to 10 micrometers, and a density of about 10 to 100 per square microns. The nanostructures provide antimicrobial properties and can be transferred to the surface of various materials such as polymers.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stacey M. Gifford, Huan Hu, Pablo M. Rojas, Gustavo A. Stolovitzky
  • Patent number: 10287468
    Abstract: The present invention relates to a CMP slurry composition, for an organic film, for polishing an organic film and an organic film polishing method using same, the CMP slurry composition comprising: a polar solvent and/or a non-polar solvent; metal oxide abrasives; an oxidant; and a heterocyclic compound, wherein the heterocyclic compound, as a heteroatom, comprises one or two of oxygen (O) atom, sulfur (S) atom and nitrogen (N) atom and has carbon content of 50-95 atom %.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Yong Sik Yoo, Jung Min Choi, Dong Hun Kang, Tae Wan Kim, Go Un Kim, Yong Kuk Kim
  • Patent number: 10280518
    Abstract: The present invention provides an etching liquid composition consisting of an aqueous solution that contains (A) 0.1 to 30 mass % of at least one type of oxidizing agent selected from among ferric ions and cupric ions; (B) 0.1 to 20 mass % of hydrogen chloride, and an etching method using it.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 7, 2019
    Assignee: ADEKA CORPORATION
    Inventors: Yuji Masamoto, Yoshihide Saio, Tamami Aoki
  • Patent number: 10256147
    Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: April 9, 2019
    Assignee: ams AG
    Inventors: Martin Schrems, Bernhard Stering, Franz Schrank
  • Patent number: 10242870
    Abstract: A method for producing patterns in a layer to be etched, from a stack including at least the layer to be etched and a masking layer overlying the layer to be etched, with the masking layer having at least one pattern. The method includes modifying a first area of the layer to be etched by ion implantation through the masking layer; depositing a buffer layer to cover the pattern of the masking layer; modifying another area of the layer to be etched, different from the first area, by ion implantation through the buffer layer, to a depth of the layer to be etched greater than the implantation depth of the preceding step of modifying; removing the buffer layer; removing the masking layer; removing the modified areas by etching them selectively to the non-modified areas of the layer to be etched.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Stefan Landis, Lamia Nouri
  • Patent number: 10241239
    Abstract: An element substrate is formed as a lens array substrate on which a plurality of lenses are formed. In a method of manufacturing the lens array substrate, first recess sections are formed on one surface of the substrate, and then a plurality of lens surfaces, which include concave surfaces, are formed at the bottoms of the first recess sections 195. Subsequently, after a light-transmitting lens layer is formed to fill the inside of the first recess sections, flattening is performed while the lens layer is removed. Here, the surface of the lens layer on a side opposite to the substrate is a planar surface which is contiguous to an outside area that is positioned on the outer side of the first recess sections on the one surface of the substrate.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 26, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Toru Nimura
  • Patent number: 10228666
    Abstract: A material modification assembly comprises an energy source for generating light beams to modify a substrate. A computing device generates pattern script(s) based on at least one parameter of the modification. The computing device also generates process script(s) including a type of pulse scripts to be used with the light beams and are based on at least one parameter of the interaction between the energy source and the substrate. The computing device combines the pattern script(s) with the process script(s) and generates command signals based on the combination. The computing device transmits the command signals to one or more additional devices of the material modification assembly to facilitate modifying the light beams for the modification to the substrate such that the modification includes a pattern on at least a surface of the substrate having dimensions and includes two or more discrete material alterations or changes spatially overlapped within the pattern.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 12, 2019
    Assignee: The Aerospace Corporation
    Inventors: Frank Edward Livingston, Timothy Ganey
  • Patent number: 10229937
    Abstract: An array structure and a manufacturing method thereof are disclosed. The method for manufacturing the array structure includes: forming a gate insulating layer on a glass substrate; and etching the gate insulating layer at a position corresponding to a source/drain signal access terminal, and forming a through-hole structure provided with an outward-inclined side wall in the gate insulating layer. Conductive films in the source/drain signal access terminal and a gate signal access terminal which have wires thereof alternate with each other have a same height, so that the forces applied to conductive balls can be more uniform, and hence the conductivity can be improved.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: March 12, 2019
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Dawei Shi, Xinyou Ji, Fuqiang Li, Jian Guo
  • Patent number: 10217670
    Abstract: Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. According to one embodiment, a substrate processing method includes providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film, depositing a metal-containing film on the second dielectric film, and forming a patterned metal-containing film by etching mask openings in the metal-containing film. The method further includes anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, where the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 26, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Satoru Nakamura, Soo Doo Chae, Akiteru Ko, Kaoru Maekawa, Gerrit J. Leusink