Chemical Etching Patents (Class 438/689)
  • Patent number: 12027422
    Abstract: A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming hard masks on the active layer, wherein a first spacing is disposed between two closely spaced hard masks in a predetermined word line region nearest to a predetermined selective gate region, wherein the first spacing is less than a second spacing between any two of the hard masks other than the two closely spaced hard masks; forming spacers on the sidewalls of the hard masks, wherein two spacers on opposite sides of the sidewalls of the closely spaced hard masks merge into a combined spacer; and transferring the patterns of the spacers to the active layer to form word lines. The step of transferring the patterns of the spacers includes transferring the pattern of the combined spacer to the active layer to form a first word line.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 2, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Tseng-Yao Pan, Chien-Hsiang Yu, Hung-Sheng Chen, Ching-Yung Wang, Cheng-Hong Wei
  • Patent number: 12020942
    Abstract: An etching method of the invention includes: a resist pattern-forming step of forming a resist layer on a target object, the resist layer being formed of a resin, the resist layer having a resist pattern; an etching step of etching the target object via the resist layer having the resist pattern; and a resist protective film-forming step of forming a resist protective film on the resist layer. The etching step is repetitively carried out multiple times. After the etching steps are repetitively carried out multiple times, the resist protective film-forming step is carried out.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: June 25, 2024
    Assignee: ULVAC, INC.
    Inventors: Taichi Suzuki, Yasuhiro Morikawa, Kenta Doi, Toshiyuki Nakamura
  • Patent number: 12012473
    Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventors: James Munro Blackwell, Robert L. Bristol, Xuanxuan Chen, Lauren Elizabeth Doyle, Florian Gstrein, Eungnak Han, Brandon Jay Holybee, Marie Krysak, Tayseer Mahdi, Richard E. Schenker, Gurpreet Singh, Emily Susan Walker
  • Patent number: 12009212
    Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 11, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 11999875
    Abstract: A polishing liquid containing: abrasive grains containing a metal oxide; at least one hydroxy acid compound selected from the group consisting of a hydroxy acid having a structure represented by General Formula (A1) below and a salt thereof; and water: [In the formula, R11 represents a hydrogen atom or a hydroxy group, R12 represents a hydrogen atom, an alkyl group, or an aryl group, n11 represents an integer of 0 or more, and n12 represents an integer of 0 or more; however, a case where both of R11 and R12 are a hydrogen atom is excluded.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 4, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Yuya Otsuka, Hisataka Minami, Shingo Kobayashi, Mayumi Komine, Hisato Takahashi
  • Patent number: 11996302
    Abstract: A substrate processing apparatus 100 includes a processing unit, a reservoir 31, a processing liquid pipe 32, a pump 34, a filter 35, a first flow rate section 36, a first return pipe 51, a first adjustment valve 52, a second return pipe 41, a branch supply pipe 16, a second flow rate section 42, and a controller. The first flow rate section 36 is placed in the processing liquid pipe 32 and measures a flow rate or pressure of the processing liquid flowing through the processing liquid pipe 32. The first adjustment valve 52 is placed in the first return pipe 51 and adjusts a flow rate of the processing liquid flowing through the first return pipe 51. The controller controls an opening degree of the first adjustment valve 52 based on the flow rate or the pressure of the processing liquid measured by the first flow rate section 36.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: May 28, 2024
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Tomoaki Aihara, Takahiro Yamaguchi, Jun Sawashima
  • Patent number: 11994835
    Abstract: An apparatus configured to facilitate identifying a factor for a defect if the defect occurs in a finished surface of the workpiece. An apparatus includes a movement path generation section configured to generate the movement path of the industrial machine when performing a work on a workpiece; a running information acquisition section configured to acquire running information of the industrial machine when performing a work on the workpiece; and an image data generation section configured to generate the image data in which a first point on the movement path corresponding to a change point of first running information, and a second point on the movement path corresponding to a change point of second running information different from the first running information are highlighted on the movement path in display forms visually different from each other.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: May 28, 2024
    Assignee: Fanuc Corporation
    Inventors: Satoshi Ikai, Tomoyuki Aizawa
  • Patent number: 11997851
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 28, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiang Hui Zhao, Zui Xin Zeng, Jun Hu, Shi Zhang, Baoyou Chen
  • Patent number: 11988689
    Abstract: A circuit for sensing a current comprises a substrate having a first and a second major surface, the second major surface being opposite to the first major surface. At least one magnetic field sensing element is arranged on the first major surface of the substrate and is suitable for sensing a magnetic field caused by a current flow in a current conductor coupled to the second major surface. The substrate also comprises at least one insulation layer, substantially buried between the first major surface and the second major surface of the substrate.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: May 21, 2024
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Bruno Boury, Robert Racz, Antonio Cacciato, Jian Chen
  • Patent number: 11990178
    Abstract: A static random-access memory (SRAM) cell includes a first inverter and a second inverter being cross-coupled; a first access transistor that accesses an output of the first inverter under control of a word line; a second access transistor that accesses an output of the second inverter under control of the word line; a first passage transistor that passes a common-mode voltage, controlled by the output of the first inverter; a second passage transistor that passes an input signal, controlled by the output of the second inverter; and a capacitor switchably coupled to receive the common-mode voltage and the input signal through the first passage transistor and the second passage transistor respectively.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 21, 2024
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Wei-Li He, Soon-Jyh Chang
  • Patent number: 11984323
    Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
  • Patent number: 11974429
    Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee, Nancy M. Lomeli, Alyssa N. Scarbrough
  • Patent number: 11969879
    Abstract: A substrate accommodating device accommodating a substrate transferred by a transfer device having an end effector configured to hold a substrate and a member including a consumable part disposed in a substrate processing apparatus for processing the substrate includes a container. A first opening through which the end effector holding the substrate passes is formed on a sidewall of the container. A recess into which front ends of the end effector are inserted is formed on an inner surface of the container facing the first opening.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 30, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masahiro Dogome
  • Patent number: 11972933
    Abstract: There is provided a substrate support of a plasma processing apparatus. The substrate support includes a wafer placement surface and a ring placement surface on which a first ring and a second ring disposed at an outer peripheral side of the first ring without overlapping with the first ring in a vertical direction are placed, with a hole at a boundary between the first ring and the second ring. The substrate support further includes a lifter pin having a first holding portion and a second holding portion, the second holding portion being unitary with and extending axially from a base end of the first holding portion and having a protruding portion protruding from an outer circumference of the first holding portion, and a driving mechanism configured to raise and lower the lifter pin.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 30, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masahiro Dogome
  • Patent number: 11961444
    Abstract: The disclosure provides a transparent display device including a display panel. The display panel includes a display area, a non-display area, and a plurality of pixels. The non-display area is adjacent to the display area. The plurality of pixels are disposed in the display area. A difference between a transmittance of the display area and a transmittance of the non-display area is less than 30% of the transmittance of the display area.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: April 16, 2024
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Tsung-Han Tsai, Kuan-Feng Lee
  • Patent number: 11961711
    Abstract: A method of providing data on radio frequency pulses in a radio frequency plasma processing system, the method including measuring an electrical parameter within a matching network of the radio frequency plasma processing system; determining an attribute of the measurement of the electrical parameter; defining a first statistic for the attribute of the measurement of the electrical parameter; defining a second statistic based on the first statistic for at least one of a phase and a process; delivering the first statistic and second statistic to a user; and storing the first statistic and the second statistic within the matching network.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: April 16, 2024
    Assignee: COMET TECHNOLOGIES USA, INC.
    Inventor: Alexandre De Chambrier
  • Patent number: 11958087
    Abstract: A substrate processing method is provided, which includes: a sulfuric acid immersing step of immersing a plurality of substrates in a sulfuric acid-containing liquid within a sulfuric acid vessel; a transporting step of taking out the substrates from the sulfuric acid vessel and transporting the substrates to an ozone gas treatment unit; and an ozone exposing step of exposing the substrates transported to the ozone gas treatment unit to an ozone-containing gas. The ozone gas treatment unit may include a gas treatment chamber which accommodates the substrates. The ozone exposing step may include the step of placing the substrates taken out of the sulfuric acid vessel in a treatment space within the gas treatment chamber to expose the substrates to the ozone-containing gas.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 16, 2024
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kei Suzuki, Masaki Inaba
  • Patent number: 11942364
    Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
  • Patent number: 11935731
    Abstract: A measurement part controls power supplied to a heater such that a temperature of the heater becomes constant by using a heater controller, and measures the supplied power in an unignited state in which plasma is not ignited and a transient state in which the power supplied to the heater decreases after plasma is ignited. A parameter calculator performs fitting on a calculation model, which includes a heat input amount from the plasma as a parameter, for calculating the power supplied in the transient state by using the power supplied in the unignited state and the transient state and measured by the measurement part, and calculates the heat input amount. An output part configured to output information based on the heat input amount calculated by the parameter calculator.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 19, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Daisuke Hayashi, Yoshihiro Umezawa, Shinsuke Oka
  • Patent number: 11929423
    Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
  • Patent number: 11923202
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit structure. The integrated circuit structure includes a substrate and a hard mask over the substrate. The hard mask has sidewalls that form a first opening and a second opening exposing an upper surface of the substrate. A block mask is arranged on the hard mask and is set back from the sidewalls of the hard mask. Spacers are disposed over the block mask and have sidewalls that define a spacer opening exposing an upper surface of the block mask. The block mask extends from directly below the spacers to laterally past the sidewalls of the spacers.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 11921318
    Abstract: A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 5, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xiaojun Chen, Honglin Zeng, Xia Feng, Dongsheng Zhang, Xiage Yin, Jiaheng Wu
  • Patent number: 11915930
    Abstract: A substrate processing method is provided for removing a resist having a hardened layer from a front surface of a substrate. The substrate processing method includes a hardened-layer removing step and a wet processing step. The hardened-layer removing step includes a heating step of heating the substrate to 150° C. or more and an ozone-gas supplying step of supplying an ozone gas to the front surface of the substrate being heated by the heating step, and the hardened-layer removing step removes the hardened layer by generating an oxygen radical near the front surface of the substrate. The wet processing step removes the resist from the front surface of the substrate by supplying a processing liquid including a sulfuric acid to the front surface of the substrate after the hardened-layer removing step.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 27, 2024
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Naoko Arima, Masaki Inaba
  • Patent number: 11894250
    Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chih-Yu Wang
  • Patent number: 11887816
    Abstract: There is provided a plasma processing apparatus. The apparatus comprises: a chamber body; and a power supply unit configured to output power for exciting a gas supplied to an inside of the chamber body. The power supply unit supplies, as power having a center frequency, a bandwidth, and a carrier pitch respectively corresponding to a set frequency, a set bandwidth, and a set carrier pitch that are indicated by a controller, power which is pulse-modulated so as to be a pulse frequency, a duty ratio, a high level, and a low level respectively corresponding to a set pulse frequency, a set duty ratio, a high-level set power, and a low-level set power indicated by the controller, and in which a pulse on time determined by the set pulse frequency and the set duty ratio is longer than a power fluctuation cycle of the power having the bandwidth.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: January 30, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazushi Kaneko, Yohei Ishida
  • Patent number: 11877434
    Abstract: A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yan Li, Song Guo, Mohd Kamran Akhtar, Alex J. Schrinsky
  • Patent number: 11875991
    Abstract: A substrate treatment method according to an embodiment of the present disclosure includes a temperature raising step of raising a temperature of a concentrated sulfuric acid, and a liquid supply step of supplying the concentrated sulfuric acid having the raised temperature to a substrate placed on a substrate processing part.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: January 16, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Koji Kagawa
  • Patent number: 11869797
    Abstract: An electrostatic chuck includes a base plate that is made of a metal; a ceramic plate that is fixed to the base plate and configured to adsorb an object by electrostatic force; and a bonding layer that is provided between the base plate and the ceramic plate to bond the base plate and the ceramic plate to each other. The bonding layer is formed of a composite material including the metal forming the base plate and a ceramic forming the ceramic plate.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: January 9, 2024
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Naomi Okamoto, Ryuji Takahashi
  • Patent number: 11866822
    Abstract: There is provided a technique that includes a precursor vessel in which a liquid precursor is stored; a first heater immersed in the liquid precursor stored in the precursor vessel and configured to heat the liquid precursor; a second heater configured to heat the precursor vessel; a first temperature sensor immersed in the liquid precursor stored in the precursor vessel and configured to measure a temperature of the liquid precursor; a second temperature sensor immersed in the liquid precursor stored in the precursor vessel and configured to measure a temperature of the liquid precursor; and a controller configured to be capable of: controlling the first heater based on the temperature measured by the first temperature sensor; and controlling the second heater based on the temperature measured by the second temperature sensor.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 9, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Hirohisa Yamazaki, Ryuichi Nakagawa, Kenichi Suzaki, Yasunori Ejiri
  • Patent number: 11869866
    Abstract: According to one embodiment, a wiring fabrication method includes pressing a first template including a first recessed portion and a second recessed portion provided at a bottom of the first recessed portion against a first film to form a first pattern including a first raised portion, corresponding to the first recessed portion, and a second raised portion, corresponding to the second recessed portion. The second raised portion protrudes from the first raised portion once formed. After forming the first pattern, a first wiring, corresponding to the first raised portion, and a via, corresponding to the second raised portion, is formed using the first pattern.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Ryoichi Suzuki, Hirokazu Kato
  • Patent number: 11855004
    Abstract: A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Shu-Shen Yeh, Che-Chia Yang, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11848227
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a step of high pressure bonding.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 19, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Sasha Joseph Kweskin, Henry Frank Erk
  • Patent number: 11834755
    Abstract: The present application provides a lithium niobate having a p-type nanowire region or an n-type nanowire region and a method for preparing the same. The method includes heating and then cooling a multi-domain lithium niobate crystal to confine hydrogen ions of the multi-domain lithium niobate crystal in domain wall regions; and poling the multi-domain lithium niobate crystal that has been heated by applying a voltage, to reverse a direction of polarization of one or more domains of the multi-domain lithium niobate crystal. The lithium niobate includes a lithium niobate crystal and a p-type nanowire region or an n-type nanowire region located in the lithium niobate crystal and adjacent to a surface of the lithium niobate crystal. The present application also provides a method for converting the charge carrier type of the lithium niobate nanowire region.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: December 5, 2023
    Assignee: NANKAI UNIVERSITY
    Inventors: Guo-Quan Zhang, Xiao-Jie Wang, Yue-Jian Jiao, Fang Bo, Jing-Jun Xu
  • Patent number: 11837502
    Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Che Tu, Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11822242
    Abstract: Describe herein is a composition comprising: an acrylic polymer comprising repeat units selected from ones having structure (1), (2), (3), (4), (5), (6), and (7) wherein these repeat units are present in said acrylic polymer in the mole % ranges as described herein; a Novolak resin having a dissolution rate in 0.26 N aqueous TMAH of at least 50 ?/sec; a diazonaphthoquinone (DNQ) photoactive compound (PAC); and an organic spin casting solvent, and a process of using said composition as a positive photoresist developable in aqueous base.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: November 21, 2023
    Assignee: Merck Patent GmbH
    Inventors: Weihong Liu, Ping-Hung Lu, Chunwei Chen, Medhat A. Toukhy
  • Patent number: 11805657
    Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mauricio Manfrini, Sai-Hooi Yeong, Han-Jong Chia, Bo-Feng Young, Chun-Chieh Lu
  • Patent number: 11803125
    Abstract: There is provided a method of forming a patterned structure on a substrate. The method includes: forming a resist layer on the substrate, the resist layer being a negative tone resist; exposing a first portion of the resist layer to a focused electron beam to form a modified first portion, the modified first portion defining a boundary of a second portion of the resist layer; performing a plasma treatment on a surface of the resist layer, including on a surface of the second portion of the resist layer to form a modified surface portion of the second portion of the resist layer, resulting in a plasma treated resist layer; and performing development of the plasma treated resist layer to form the patterned structure on the substrate corresponding the second portion of the resist layer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 31, 2023
    Assignee: Singapore University of Technology and Design
    Inventors: You Sin Tan, Joel Yang, Hailong Liu, Qifeng Ruan
  • Patent number: 11798820
    Abstract: A system may include a main line for delivering a first gas, and a sensor for measuring a concentration of a precursor in the first gas delivered through the main line. The system may further include first and second sublines for providing fluid access to first and second processing chambers, respectively. The first subline may include a first flow controller for controlling the first gas flowed through the first subline. The second subline may include a second flow controller for controlling the first gas flowed through the second subline. A delivery controller may be configured to control the first and second flow controllers based on the measured concentration of the precursor to deliver a first mixture of the first gas and a second gas and a second mixture of the first and second gases into the first and second semiconductor processing chambers, respectively.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Diwakar Kedlaya, Fang Ruan, Zubin Huang, Ganesh Balasubramanian, Kaushik Alayavalli, Martin Seamons, Kwangduk Lee, Rajaram Narayanan, Karthik Janakiraman
  • Patent number: 11798916
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
  • Patent number: 11785755
    Abstract: A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 10, 2023
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Nan Wang
  • Patent number: 11776823
    Abstract: A substrate processing method includes a process of cooling a substrate to below a freezing point of a processing liquid using a cooling fluid brought into contact with the substrate opposite. While the substrate is cooled to below the freezing point of the processing liquid, a droplet of processing liquid is dispensed onto a surface of the substrate at a specified location of a foreign substance. The droplet then forms a frozen droplet portion at the specified location. The frozen droplet portion is then thawed.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: October 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Mana Tanabe, Kosuke Takai, Kenji Masui, Kaori Umezawa
  • Patent number: 11746337
    Abstract: Disclosed are methods for isolating polymerase complexes from a mixture of polymerase complex components. The polymerase complexes can comprise a nanopore to provide isolated nanopore sequencing complexes. The methods relate to the positive and negative isolation of the polymerase complexes and/or nanopore sequencing complexes. Also disclosed is a nucleic acid adaptor for isolating active polymerase complexes, polymerase complexes comprising the nucleic acid adaptor, and methods for isolating active polymerase complexes using the nucleic acid adaptor.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 5, 2023
    Assignee: Roche Sequencing Solutions, Inc.
    Inventors: Helen Franklin, Cynthia Cech, Timothy Kellogg Craig, Aruna Ayer, Kirti Dhiman, Natalie B. Chechelski Johnston, Joshua N. Mabry, Arkadiusz Bibillo, Peter Crisalli, Randall W. Davis
  • Patent number: 11740227
    Abstract: A nanopore cell includes a conductive layer and a working electrode disposed above the conductive layer and at the bottom of a well into which an electrolyte may be contained, such that at least a portion of a top base surface area of the working electrode is exposed to the electrolyte. The nanopore cell further includes a first insulating wall disposed above the working electrode and surrounding a lower section of a well, and a second insulating wall disposed above the first insulating wall and surrounding an upper section of the well, forming an overhang above the lower section of the well. The upper section of the well includes an opening that a membrane may span across, and wherein a base surface area of the opening is smaller than the at least a portion of the top base surface area of the working electrode that is exposed to the electrolyte.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: August 29, 2023
    Assignee: Roche Sequencing Solutions, Inc.
    Inventors: John Foster, Morgan Mager
  • Patent number: 11735705
    Abstract: Methods of making single walled carbon nanotubes (SWNTs) including a single step for preparing a homogeneous dispersion of SWNTs in a battery electrode powder. The method may comprise providing a reactor in fluid communication with a mixer, wherein an aerosol containing SWNTs is transmitted from the reactor directly to the mixer containing a battery electrode powder.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 22, 2023
    Assignees: HONDA MOTOR CO., LTD., NANOSYNTHESIS PLUS, LTD.
    Inventors: Avetik Harutyunyan, Neal Pierce, Elena Mora Pigos
  • Patent number: 11728175
    Abstract: Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and/or carbon removal, is also disclosed.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 15, 2023
    Assignee: ASM IP HOLDING B.V.
    Inventors: Eva E. Tois, Hidemi Suemori, Viljami J. Pore, Suvi P. Haukka, Varun Sharma, Jan Willem Maes, Delphine Longrie, Krzysztof Kachel
  • Patent number: 11705346
    Abstract: An upper member is disposed at an upper portion within a processing chamber. A ceiling member forms a ceiling of the processing chamber, and is provided with a through hole at a facing surface thereof which faces the upper member. A supporting member supports the upper member with a first end thereof located inside the processing chamber by being inserted through the through hole and slid within the through hole. An accommodation member accommodates therein a second end of the supporting member located outside the processing chamber, and is partitioned into a first space at a first end side and a second space at a second end side in a moving direction with respect to the second end. A pressure controller generates a pressure difference between the first space and the second space. The pressure difference allows the supporting member to be moved.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: July 18, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusei Kuwabara, Takahiro Senda
  • Patent number: 11696506
    Abstract: A piezoelectric device has a layered structure in which at least a first electrode, a plastic layer, an orientation control layer, a piezoelectric layer, and a second electrode are stacked, wherein the orientation control layer is amorphous, and the piezoelectric layer with a thickness of 20 nm to 250 nm is provided over the orientation control layer, the piezoelectric layer having a wurtzite crystal structure, and wherein the orientation control layer and the piezoelectric layer are provided between the first electrode and the second electrode.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 4, 2023
    Assignee: NITTO DENKO CORPORATION
    Inventors: Masaharu Arimoto, Hironobu Machinaga, Masato Katsuda, Manami Kurose
  • Patent number: 11687005
    Abstract: A method and a system for preparing a substrate with three dimensional features for immersion based inspection. The method may include (a) receiving, by a secondary chamber, an article that includes the substrate, a housing, and a transparent element; wherein the transparent element is sealingly coupled to the housing to provide a sealed inner space; wherein the sealed inner space may include a gap between a first surface of the substrate to a second surface of the transparent element; wherein the gap is filled with gas during the receiving of the article; (b) evacuating the gas from the gap while reducing a pressure within the secondary chamber and maintaining an integrity of the transparent element; (c) filling the gap with fluid while increasing the pressure within a secondary chamber inner space and maintaining an integrity of the transparent element; and (d) outputting the article from the secondary chamber.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: June 27, 2023
    Assignee: Applied Materials Israel Ltd.
    Inventor: Tai Kuzniz
  • Patent number: 11688730
    Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Hui-Ting Yang, Shun Li Chen, Ko-Bin Kao, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Patent number: 11689177
    Abstract: An electronic device that includes a base substrate having a mounting surface; an electronic component having a mechanical vibration portion mounted on the mounting surface of the base substrate; an intermediate layer mounted on the base substrate and forming an internal space with the base substrate so as to accommodate the electronic component therein, the intermediate layer having at least one through-hole that opens the internal space to an outside; and a sealing layer on the intermediate layer and sealing the internal space by closing the at least one through-hole.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 27, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeo Ojima, Isao Ikeda, Koki Sai