Chemical Etching Patents (Class 438/689)
  • Patent number: 11043559
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Hsiu Wang, Yean-Zhaw Chen, Ying-Ting Hsia, Jhao-Ping Jiang, Chun-Chih Cheng
  • Patent number: 11036202
    Abstract: Systems and methods for real time semiconductor manufacturing cluster tool health monitoring are provided via an in-situ sensor. In a method embodiment, an operation procedure for pumping/venting load lock (LL), and LL doors facing vacuum transfer module (VTM) and equipment front end module (EFEM), sensor installation location and operation procedure, and data flow and analysis process are provided. The sensor provides real-time data and monitors airborne particle contamination on EFEM, load lock (LL), and VTM, and plurality of process modules (PMs) simultaneously by correlating door open/close time and vent/pump timing in the loadlock to the particle measurement data. The method further provides an operation for determining that a maintenance procedure is recommended on one of the EFEM, the LL, the VTM, or the plurality of PMs based on the real time measurement data, door state data, and using machine learning algorithms.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 15, 2021
    Assignee: Lam Research Corporation
    Inventors: Hossein Sadeghi, Scott Baldwin
  • Patent number: 11004731
    Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 11, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Yumiko Miyano
  • Patent number: 11004718
    Abstract: Compositions and designs are described for a sectional porous carrier used in processing microelectronics where thin device substrates are affixed by adhesive to the carrier and form an impervious bonded stack that is resistant to thermal and chemical products during processing and is easily handled by a substrate handling vacuum robot, and subsequently allows rapid removal (debonding) in batch operations by directional penetration into sectional porous regions by selective liquids which release the carrier from the device wafer without harm. The invention carrier with porous regions is used for temporary support of thin and fragile device substrates having capabilities of selective penetration of chemical liquids to pass through the porous regions, access and breakdown the bonding adhesive, and allow it to release without damage to the device substrate.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 11, 2021
    Inventors: John Cleaon Moore, Alexander Joseph Brewer, Jared Michael Pettit, Alman XiMin Law
  • Patent number: 10994469
    Abstract: A distributed feedback laser having a conjugated dendrimer as the active lasing component, and a method for patterning conjugated dendrimers.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: May 4, 2021
    Assignees: THE UNIVERSITY COURT OF THE UNIVERSITY OF ST. ANDREWS, OXFORD UNIVERSITY INNOVATION LIMITED
    Inventors: Paul Burn, Ifor Samuel, Justin Lawrence, Jonathan Markham
  • Patent number: 10991596
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 10985049
    Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: April 20, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
  • Patent number: 10957595
    Abstract: A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 23, 2021
    Assignee: Cerebras Systems Inc.
    Inventor: Jean-Philippe Fricker
  • Patent number: 10957580
    Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Wei Liu, Chia-Tien Wu, Wei-Chen Chu
  • Patent number: 10948412
    Abstract: Particularly provided is a method and a system for screening nanoparticles which allow effective search of conditions for surface modification of nanoparticles and reduction in the time, the labor, and the amount of a sample required for the surface modification compared with conventional techniques. The method for screening nanoparticles includes the steps of: dividing a nanoparticle suspension for a respective plurality of containers provided in a containment receptacle; performing surface modification on nanoparticles under different conditions for the respective containers; preparing evaluation samples by adding a dispersion medium into each container and mixing the nanoparticles and the dispersion medium; and performing evaluation on the evaluation sample in each container by optical analysis.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 16, 2021
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, NS MATERIALS INC.
    Inventors: Hiroyuki Nakamura, Maki Saeki, Masanori Tanaka, Eiichi Kanaumi
  • Patent number: 10950506
    Abstract: Fabrication methods and resulting structures for single and double diffusion breaks are provided. Aspects include forming one or more fins on a substrate, the substrate including a first region and a second region, forming a plurality of sacrificial gate structures over channel regions associated with the one or more fins, forming a single diffusion break cavity in the first region of the substrate, forming a double diffusion break cavity in the second region of the substrate, depositing a first dielectric material in the single diffusion break cavity, and depositing a second dielectric material in the double diffusion break cavity.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Juntao Li, Kangguo Cheng, Junli Wang
  • Patent number: 10942446
    Abstract: Disclosed is a method for cleaning a photo mask. The method includes a pre-treatment operation of wetting a chemical on an entire surface of the photo mask in a state in which the photo mask is stopped, and a cleaning operation of supplying the chemical to a pattern area of the photo mask in a state in which the photo mask is rotated.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 9, 2021
    Assignee: SEMES CO. LTD.
    Inventors: Seong Soo Lee, Jeong Yeong Park, Sung Bum Park, Byung Chul Kang
  • Patent number: 10943791
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
  • Patent number: 10934614
    Abstract: A vapor deposition mask (100) includes a resin layer (10) including a plurality of openings (11); a magnetic metal layer (20) located so as to overlap the resin layer, the magnetic metal layer including a mask portion (20a) having such a shape as to expose the plurality of openings and a peripheral portion (20b) located so as to enclose the mask portion; and a frame (30) secured to the peripheral portion of the magnetic metal layer. The resin layer is not joined to the mask portion of the magnetic metal layer but is joined to at least a part of the peripheral portion of the magnetic metal layer.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 2, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Susumu Sakio, Katsuhiko Kishimoto, Koshi Nishida, Kozo Yano
  • Patent number: 10923446
    Abstract: A metallic etching process includes applying an anti-reflection coating over a metallic superstrate, applying a dry film photoresist over the anti-reflection coating, removing exposed portions of the dry film photoresist exposing a portion of the anti-reflection coating, etching the exposed portions of the anti-reflection coating exposing portions of the metal superstrate, etching portions of the metallic superstrate not covered by the dry film photoresist, and removing the dry film photoresist and the anti-reflection coating leaving portions of the metallic superstrate. An indium bump liftoff process includes applying a positive photoresist, forming a liftoff mask by applying a dry film photoresist over the positive photoresist, removing exposed portions of the liftoff mask to expose a portion of a substrate, depositing an indium film over the exposed portion of the substrate and remaining portions of the liftoff mask, and removing remaining portions of the liftoff mask.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 16, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: Ari Brown, Vilem Mikula
  • Patent number: 10923357
    Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Itou, Atsushi Harikai, Noriyuki Matsubara, Shogo Okita
  • Patent number: 10923327
    Abstract: Embodiments described herein generally relate to apparatus and methods for processing a substrate utilizing a high radio frequency (RF) power. The high RF power enables deposition of films on the substrate with more desirable properties. A first plurality of insulating members is disposed on a plurality of brackets and extends laterally inward from a chamber body. A second plurality of insulating members is disposed on the chamber body and extends from the first plurality of insulating members to a support surface of the chamber body. The insulating members reduce the occurrence of arcing between the plasma and the chamber body.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jianheng Li, Lai Zhao, Robin L. Tiner, Allen K. Lau, Gaku Furuta, Soo Young Choi
  • Patent number: 10907073
    Abstract: A polishing composition for use in polishing an object to be polished, which comprises abrasive grains, a dispersing medium, and an additive, wherein the abrasive grains are surface-modified, the additive is represented by the following formula 1: wherein in the formula 1, X1 is O or NR4, X2 is a single bond or NR5, R1 to R5 are each independently a hydrogen atom; a hydroxy group; a nitro group; a nitroso group; a C1-4 alkyl group optionally substituted with a carboxyl group, an amino group, or a hydroxy group; or CONH2; with the proviso that R2 and R5 may form a ring; when X2 is a single bond, R3 is not a hydrogen atom, or R1 to R3 are not a methyl group; and when X2 is NR5 and three of R1 to R3 and R5 are a hydrogen atom, the other one is not a hydrogen atom or a methyl group; and a pH is 5.0 or less.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 2, 2021
    Inventors: Satoru Yarita, Yukinobu Yoshizaki
  • Patent number: 10903110
    Abstract: A method of forming fine interconnection includes: forming spacers on a first and second hard mask layer on a dielectric layer; forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer; oxidizing a sidewall of the first hard mask layer that surrounding the via hole; forming a second via hole in the second hard mask layer; forming a mask to cover the first hard mask layer in the second via hole; forming a line trench in a portion of the second hard mask layer exposed by the spacers and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and forming a conductive material in the line trench and the first via hole.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 26, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10886182
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang, Tzu-Chiang Chen
  • Patent number: 10886428
    Abstract: A method of manufacturing a semiconductor element includes: a first providing step comprising providing a structure body comprising a semiconductor stacked body, the structure body including first surfaces that include surfaces defining at least one first recess; a first forming step comprising forming a first rough-surface portion at or inward of at least a portion of the surfaces defining the first recess of the structure body; a second forming step comprising forming a first metal layer at a first surface side of the structure body; a second providing step comprising providing a substrate on which a second metal layer is disposed; and a bonding step comprising heating the first metal layer and the second metal layer in a state in which the first metal layer and the second metal layer face each other.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Hashizume, Eiji Muramoto, Nobuyoshi Niki
  • Patent number: 10886134
    Abstract: A polishing method for polishing by sliding a semiconductor silicon wafer, held by a polishing head, against a polishing pad attached to a turn table while supplying a polishing agent, wherein the semiconductor silicon wafer is subjected to primary polishing, secondary polishing, and final polishing in turn, the secondary polishing comprises polishing by an alkaline based polishing agent which includes free abrasive grains and does not include a water-soluble polymer agent, and subsequent rinse polishing by a polishing agent which includes a water-soluble polymer agent and the rinse polishing includes two stages of polishing, wherein, after performing a first stage of the rinse polishing while supplying a polishing agent which includes a water-soluble polymer agent, a second stage of the rinse polishing is performed while supplying a switched polishing agent whose water-soluble polymer agent has an average molecular weight larger than the polishing agent of the first stage.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 5, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kazuaki Aoki
  • Patent number: 10854479
    Abstract: A substrate processing method is provided, which includes: an ozone-containing hydrofluoric acid solution spouting step of spouting an ozone-containing hydrofluoric acid solution containing ozone dissolved therein from a nozzle toward one major surface of a substrate held by a substrate holding unit; and a brush-cleaning step of cleaning the one major surface of the substrate by bringing a cleaning brush into abutment against the one major surface of the substrate, the brush-cleaning step being performed after the ozone-containing hydrofluoric acid solution spouting step or in parallel with the ozone-containing hydrofluoric acid solution spouting step.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 1, 2020
    Inventors: Nobuyuki Shibayama, Masayuki Hayashi, Seiji Ano, Toru Edo
  • Patent number: 10847379
    Abstract: An etching method includes: adsorbing an adsorbate based on a processing gas containing BCl3 gas onto a target object, which serves as a to-be-etched object, by: supplying H2 gas and the processing gas to a process space in which the target object is disposed; and applying power of a predetermined frequency to the process space, while supplying the H2 gas is stopped, to generate plasma in the process space; and etching the target object by generating plasma of a rare gas in the process space to activate the adsorbate.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masato Sakamoto, Tadahiro Ishizaka, Takeshi Itatani
  • Patent number: 10782460
    Abstract: An optical filter may include a substrate. The optical filter may include a first mirror and a second mirror. Each of the first mirror and the second mirror may include a plurality of quarterwave stacks. The plurality of quarterwave stacks may include a plurality of layers comprising a first material, a second material, and a third material. The optical filter may include a spacer disposed between the first mirror and the second mirror.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 22, 2020
    Assignee: VIAVI Solutions Inc.
    Inventor: Georg J. Ockenfuss
  • Patent number: 10744684
    Abstract: A method of preparing a patterned cured product, the method including: providing a composition including a sol-gel reactive silicon-containing monomer, a polymerizable (meth)acryl monomer, a photoinitiator, and a fluorinating agent on a substrate to form a first layer on the substrate; contacting the first layer with a master mold to form a second layer including a pattern transferred by the master mold; and obtaining the patterned cured product from the second layer, wherein obtaining of the patterned cured product from the second layer includes a sol-gel reaction, a photocuring reaction, and a separating of the master mold.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Heemin Yoo, Yeonjoo Seo, Dahye Yoon, Hyunsup Yoon, Jungwoon Jung, Sungchan Jo, Kyunglae Rho, Sungwook Woo, Sooim Jeong
  • Patent number: 10749073
    Abstract: A method for producing light-emitting UV column structures using the epitaxy of the organometallic compounds of the gaseous phase on a PSS plate having a surface for epitaxy provided with protrusions with a regular shape, having a tip and a side surface, in particular protrusions with a conical shape. The present disclosure also includes structures produced using this method.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 18, 2020
    Assignee: Instytut Technologii Materialow Elektronicznych
    Inventor: Mariusz Rudzinski
  • Patent number: 10741369
    Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a chamber capable of containing a substrate therein. A mount part can have the substrate mounted thereon. A first member is provided between an inner wall of the chamber and a plasma generation region above the mount part. An optical transmitter is provided in an opening that is provided in the first member to extend from a side of the inner wall of the chamber to the plasma generation region or provided in gaps between a plurality of the first members.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Ryo Suemitsu
  • Patent number: 10714389
    Abstract: Semiconductor devices and methods to fabricate the devices are provided. For example, a semiconductor device includes a back-end-of-line (BEOL) structure formed on a semiconductor substrate. The BEOL structure further includes at least one metallization layer comprising a pattern of elongated parallel metal lines. The pattern of elongated metal lines comprises a plurality of metal lines having a minimum width and at least one wider metal line having a width which is greater than the minimum width.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 14, 2020
    Assignee: ELPIS TECHNOLOGIES, INC.
    Inventors: Hsueh-Chung Chen, James Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10700071
    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
  • Patent number: 10678007
    Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 9, 2020
    Assignees: IMEC VZW, Universiteit Gent
    Inventors: Joris Van Campenhout, Bernardette Kunert, Maria Ioanna Pantouvaki, Dries Van Thourhout, Yuting Shi
  • Patent number: 10677656
    Abstract: A device is disclosed including a substrate and a floating blinded infrared detector and/or a shunted blinded infrared detector. The floating blinded infrared detector may include an infrared detector coupled to and thermally isolated from the substrate; and a blocking structure disposed above the infrared detector to block external thermal radiation from being received by the infrared detector; and wherein the blocking structure comprises a plurality of openings. The shunted blinded infrared detector may include an additional infrared detector coupled to the substrate; an additional blocking structure disposed above the infrared detector to block external thermal radiation from being received by the additional infrared detector; and a material that thermally couples the additional infrared detector to the substrate and the additional blocking structure. Methods for using and forming the device are also disclosed.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 9, 2020
    Assignee: FLIR Systems, Inc.
    Inventors: Eric A. Kurth, Chris Chan, Kevin Peters, Patrick Franklin, Robert F. Cannata, James L. Dale, Tommy Marx, David Howard, Jefferson Rose, Michael DeBar
  • Patent number: 10672796
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 10658194
    Abstract: A method for processing a substrate in a processing chamber, comprising forming a deposition over the substrate is provided. A silicon containing gas is flowed into the processing chamber. A COS containing gas is flowed into the processing chamber. A plasma is formed from the silicon containing gas and the COS containing gas in the processing chamber, wherein the plasma provides the deposition over the substrate.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 19, 2020
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qing Xu, Qian Fu, Hua Xiang, Lin Zhao
  • Patent number: 10658473
    Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface. A gate stack passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Patent number: 10640679
    Abstract: The invention provides a chemical-mechanical polishing composition containing a ceria abrasive, a polyhydroxy aromatic carboxylic acid, an ionic polymer of formula I: wherein X1 and X2, Z1 and Z2, R1, R2, R3, and R4, and n are as defined herein, and water, wherein the polishing composition has a pH of about 1 to about 4.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon oxide, silicon nitride, and/or polysilicon.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 5, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Sudeep Pallikkara Kuttiatoor, Charles Hamilton, Kevin P. Dockery
  • Patent number: 10639766
    Abstract: Described are materials and methods for processing (polishing or planarizing) a substrate that contains pattern dielectric material using a polishing composition (aka “slurry”) and an abrasive pad, e.g., CMP processing.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Viet Lam, Ji Cui
  • Patent number: 10619075
    Abstract: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a self-stopping agent, an aqueous carrier, and optionally, a cationic polymer, and provides a method suitable for polishing a substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 14, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Juyeon Chang, Tina C. Li, Viet Lam, Ji Cui, Sarah Brosnan, Chul Woo Nam
  • Patent number: 10619076
    Abstract: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a self-stopping agent, an aqueous carrier, and optionally, a cationic polymer, and provides a method suitable for polishing a substrate.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Juyeon Chang, Tina C. Li, Viet Lam, Ji Cui, Sarah Brosnan, Chul Woo Nam
  • Patent number: 10586591
    Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra Sadana
  • Patent number: 10577706
    Abstract: A plating apparatus includes a processing bath configured to store a processing liquid therein, a transporter configured to immerse a substrate holder, holding a substrate, in the processing liquid, raise the substrate holder out of the processing bath, and transport the substrate holder in a horizontal direction, and a gas flow generator configured to generate a clean gas flow forward of the substrate with respect to a direction in which the substrate holder is transported. The transporter moves the gas flow generator together with the substrate holder in the horizontal direction while transporting the substrate holder in the horizontal direction.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: March 3, 2020
    Assignee: EBARA CORPORATION
    Inventor: Tomonori Hirao
  • Patent number: 10580886
    Abstract: The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chi-Chun Liu, Chun Wing Yeung, Chen Zhang
  • Patent number: 10572091
    Abstract: The present application discloses a touch substrate including a base substrate, and a touch electrode layer on the base substrate having a first region having a plurality of first mesh electrode patterns, a second region having a plurality of second mesh electrode patterns corresponding to the plurality of first mesh electrode patterns, and an interface region between the first region and the second region. Each of the plurality of first mesh electrode patterns includes a plurality of first mesh electrode lines having a first line width. A corresponding second mesh electrode pattern includes a plurality of second mesh electrode lines corresponding to the plurality of first mesh electrode lines and having the first line width. The first mesh electrode line in the interface region has a second line width no less than the first line width.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 25, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaodong Xie, Xibin Shao, Ming Hu, Ming Zhang, Jing Wang
  • Patent number: 10563300
    Abstract: A method is employed to separate a carbon structure, which is disposed on a seed structure, from the seed structure. In the method, a carbon structure is deposited on the seed structure in a process chamber of a CVD reactor. The substrate comprising the seed structure (2) and the carbon structure (1) is heated to a process temperature. At least one etching gas is injected into the process chamber, the etching gas having the chemical formula AOmXn, AOmXnYp or AmXn, wherein A is selected from a group of elements that includes S, C and N, wherein O is oxygen, wherein X and Y are different halogens, and wherein m, n and p are natural numbers greater than zero. Through a chemical reaction with the etching gas, the seed structure is converted into a gaseous reaction product. A carrier gas flow is used to remove the gaseous reaction product from the process chamber.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: February 18, 2020
    Assignee: AIXTRON SE
    Inventors: Kenneth B. K. Teo, Alexandre Jouvray, Jai Matharu, Simon Thomas
  • Patent number: 10566477
    Abstract: Provided are a method of manufacturing a flexible device and the flexible device, a solar cell, and a light emitting device. The method of manufacturing a flexible device includes providing a device layer on a sacrificial substrate, contacting a flexible substrate on one side surface of the device layer, and removing the sacrificial substrate. A large area device may be transferred onto the flexible substrate with superior alignment to realize and manufacture the flexible device. In addition, since mass production is possible, the economic feasibility may be superior. Also, when a large area solar cell having a thin thickness is manufactured, since a limitation such as twisting of a thin film of a solar cell may be effectively solved, the economic feasibility and stability may be superior.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 18, 2020
    Assignees: SK Siltron Co., Ltd., Korea Advanced Institute of Science Technology
    Inventors: Keon Jae Lee, Sang Yong Lee
  • Patent number: 10541318
    Abstract: Semiconductor devices and methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chun W. Yeung, Chen Zhang
  • Patent number: 10535530
    Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
  • Patent number: 10527896
    Abstract: Various circuits may benefit from suitable protection. For example, certain displays, such as active matrix liquid crystal displays, may benefit from enclosures configured to protect driver circuits from high intensity radiated fields. A system can include a first protective conductive coating layer. The system can also include a first insulating layer on the first protective conductive layer. The system can further include a signal conductive layer on the insulating layer. The system can additionally include a driver layer mounted to the signal conductive layer. The system can also include a second insulating layer above the driver layer. The system can further include a second protective conductive coating layer on the second insulating layer. The system can additionally include one or a plurality of conductive elements disposed between the first protective conductive coating layer and the second protective conductive coating layer to form an enclosure around the driver layer.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 7, 2020
    Assignee: L3 TECHNOLOGIES, INC.
    Inventors: Michael G. Abernathy, Mark W. Fletcher, Sanjay Tripathi
  • Patent number: 10510839
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Hsiu Wang, Yean-Zhaw Chen, Ying-Ting Hsia, Jhao-Ping Jiang, Chun-Chih Cheng
  • Patent number: 10504838
    Abstract: A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Troy R. Sorensen