Chemical Etching Patents (Class 438/689)
  • Patent number: 11654461
    Abstract: A plasma ashing method is provided. The plasma ashing method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the semiconductor substrate models utilize a plurality of tested recipes. The plasma ashing method further includes selecting one of the tested recipes as a process recipe for a plasma ash process.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Jen Hsiao, Ya-Ping Chen, Chien-Hung Lin, Wen-Pin Liu, Chin-Wen Chen
  • Patent number: 11652073
    Abstract: A light source unit for a display device includes: a printed circuit board including a soldering pad located on a substrate of glass and including a copper layer, and a first diffusing barrier pattern located on the soldering pad and including a molybdenum alloy; and a light emitting diode mounted on the soldering pad through a solder resist. In one embodiment, the printed circuit board is a glass printed circuit board.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 16, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Tae-Joon Song, Kyu-Hwang Lee, Chul-Ho Kim
  • Patent number: 11643573
    Abstract: The present invention provides a polishing composition with which it is possible to decrease a level difference to be unintentionally generated between dissimilar materials and a level difference to be unintentionally generated between coarse and dense portions of a pattern. The present invention relates to a polishing composition which contains abrasive grains having an average primary particle size of 5 to 50 nm, a level difference modifier containing a compound with a specific structure, having an aromatic ring and a sulfo group or a salt group thereof which is directly bonded to this aromatic ring, and a dispersing medium and of which the pH is less than 7.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 9, 2023
    Assignee: FUJIMI INCORPORATED
    Inventors: Yukinobu Yoshizaki, Koichi Sakabe, Satoru Yarita, Kenichi Komoto
  • Patent number: 11637025
    Abstract: Generation of a deposit can be suppressed and high selectivity can be acquired when etching a first region made of silicon nitride selectively against a second region made of silicon oxide. A method includes preparing a processing target object having the first region and the second region within a chamber provided in a chamber main body of a plasma processing apparatus; generating plasma of a first gas including a gas containing hydrogen within the chamber to form a modified region by modifying a part of the first region with active species of the hydrogen; and generating plasma of a second gas including a gas containing fluorine within the chamber to remove the modified region with active species of the fluorine.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 25, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Sho Kumakura
  • Patent number: 11634824
    Abstract: A device for performing electrolysis of water is disclosed. The device may include a semiconductor structure with a surface and an electron guiding layer below said surface, the electron guiding layer of the semiconductor structure being configured to guide electron movement in a plane parallel to the surface. The electron guiding layer of the semiconductor structure may include an InGaN quantum well or a heterojunction, the heterojunction being a junction between AlN material and GaN material or between AlGaN material and GaN material and at least one metal cathode arranged on the surface of the semiconductor structure. The device may further include at least one photoanode arranged on the surface of the semiconductor structure, wherein the at least one photoanode may include a plurality of quantum dots of InxGa(1-x)N material, wherein 0.4?x?1. A system including such a device is also disclosed.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 25, 2023
    Assignee: Epinovatech AB
    Inventor: Martin Andreas Olsson
  • Patent number: 11608557
    Abstract: In some embodiments, methods are provided for simultaneously and selectively depositing a first material on a first surface of a substrate and a second, different material on a second, different surface of the same substrate using the same reaction chemistries. For example, a first material may be selectively deposited on a metal surface while a second material is simultaneously and selectively deposited on an adjacent dielectric surface. The first material and the second material have different material properties, such as different etch rates.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: March 21, 2023
    Assignee: ASM IP HOLDING B.V.
    Inventors: Michael Eugene Givens, Eva Tois, Suvi Haukka, Daria Nevstrueva, Charles Dezelah
  • Patent number: 11605525
    Abstract: Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 14, 2023
    Assignee: FEI Company
    Inventors: James Vickers, Seema Somani, Cecelia Campochiaro, Yakov Bobrov
  • Patent number: 11600717
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
  • Patent number: 11594165
    Abstract: The disclosure provides a transparent display device including an exposed region and a non-exposed region. The non-exposed region is adapted for being hidden by a frame. The transparent display device includes a plurality of pixels and a driving element. The pixels are disposed in the exposed region. The driving element is adapted for driving the pixels, the driving element is disposed in the non-exposed region, and the non-exposed region partially surrounds the exposed region.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 28, 2023
    Assignee: Innolux Corporation
    Inventors: Yu-Chia Huang, Yuan-Lin Wu, Tsung-Han Tsai, Kuan-Feng Lee
  • Patent number: 11591260
    Abstract: A large-size synthetic quartz glass substrate has a diagonal length of at least 1,000 mm. Provided that an effective range is defined on the substrate surface, and the effective range is partitioned into a plurality of evaluation regions such that the evaluation regions partly overlap each other, a flatness in each evaluation region is up to 3 ?m. From the quartz glass substrate having a high flatness and a minimal local gradient within the substrate surface, a large-size photomask is prepared.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: February 28, 2023
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yoko Ishitsuka, Atsushi Watabe, Daijitsu Harada, Masaki Takeuchi
  • Patent number: 11574811
    Abstract: Techniques for tight pitch patterning are provided. In one aspect, a patterning method includes: forming mandrels on a substrate; forming spacers that are undoped alongside the mandrels, wherein gaps are present between the spacers; filling the gaps with a sacrificial material having a dopant; forming a mask having an opening marking a cut region of at least one of the spacers; removing the sacrificial material from the cut region of the at least one spacer via the mask; removing the mask; performing an anneal to diffuse the dopant from the sacrificial material into the spacers to form doped spacers, wherein following the anneal the cut region of the at least one spacer remains undoped; removing the cut region of the at least one spacer selective to the doped spacers; and patterning features in the substrate using the doped spacers as a hardmask. A patterning structure is also provided.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 7, 2023
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 11530283
    Abstract: A laminate and a method for producing a patterned substrate using the same are disclosed herein. In some embodiments, a laminate includes a substrate, and a stripe pattern having first and second polymer lines alternately and repeatedly disposed on the substrate, wherein the first polymer line comprises a first polymer having a first polymerized unit having a ring structure connected to a main chain and a second polymerized unit represented by Formula 1. The method may be applied to manufacture of devices, such as electronic devices, or of applications, such as integrated optical systems, guidance and detection patterns of magnetic domain memories, flat panel displays, liquid crystal displays (LCDs), thin film magnetic heads or organic light emitting diodes, and may be used to build a pattern on a surface used in manufacture of discrete track media, such as integrated circuits, bit-patterned media and/or magnetic storage devices such as hard drives.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 20, 2022
    Inventors: Na Na Kang, Se Jin Ku, Mi Sook Lee, Eung Chang Lee, Eun Young Choi, Sung Soo Yoon, No Jin Park, Je Gwon Lee, Hyung Ju Ryu, Yoon Hyung Hur
  • Patent number: 11513108
    Abstract: A system and method provides a more precise mole delivery amount of a process gas, for each pulse of a pulse gas delivery, by measuring a concentration of the process gas and controlling the amount of gas mixture delivered in a pulse of gas flow based on the received concentration of the process gas. The control of mole delivery amount for each pulse can be achieved by adjusting flow setpoint, pulse duration, or both.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: November 29, 2022
    Assignee: MKS Instruments, Inc.
    Inventors: Jim Ye, Vidi Saptari, Junhua Ding
  • Patent number: 11495471
    Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 8, 2022
    Inventors: An-Hsuan Lee, Chun-Hung Liao, Chen-Hao Wu, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: 11489176
    Abstract: An assembly for producing energy may include a fuel cell, a fluidic cell circuit configured to receive a first heat-transfer fluid and arranged at least partially around the fuel cell, a reversible thermodynamic system configured to alternatively: (i) evacuate the thermal energy produced by the fuel cell and transform it into mechanical energy through the first heat-transfer fluid, and (ii) input thermal energy to the fuel cell through the first heat-transfer fluid, wherein the thermodynamic system includes: (a) a fluidic thermodynamic circuit to receive a second heat-transfer fluid; (b) a first exchanger to exchange thermal energy between the fluidic thermodynamic circuit and the fluidic cell circuit; and (c) a second exchanger configured to exchange thermal energy between the fluidic thermodynamic circuit and an external source.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 1, 2022
    Assignees: 1). COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SAFRAN POWER UNITS
    Inventors: Nicolas Tauveron, Benjamin Boillot, Jean-Baptiste Jollys
  • Patent number: 11460458
    Abstract: An article storage apparatus includes a sensor device sensing gases included in air in a chamber where an article is stored; a concentrator concentrating the gases contained in the air; a filtering device filtering the gases contained in the air; and at least one processor. The at least one processor controls the concentrator to concentrate the gases contained in the air, and identifies a condition of the article based on a concentration level of a target gas related to the article measured by the sensor device when the target gas is extracted as gases desorbed from the concentrator pass the filtering device.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyounghoon Lee, Jongsoo Hong, Junhoe Choi, Jeongsu Han
  • Patent number: 11437563
    Abstract: An acoustic wave device includes an acoustic wave generator, a support portion, a protective member, and at least one element embedded in the protective member. The acoustic wave generator is disposed on a surface of a substrate. The support portion is disposed on the substrate along a circumference of the acoustic wave generator. The protective member is coupled to the support portion and disposed to be spaced apart from the acoustic wave generator by an interval.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 6, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Jae Hyun Jung, Seong Hun Na
  • Patent number: 11393762
    Abstract: An apparatus system is provided which comprises: a substrate; a metal pillar formed on the substrate, the metal pillar comprising a first section and a second section, wherein the first section of the metal pillar is formed by depositing metal in a first opening of a first photoresist layer, and wherein the second section of the metal pillar is formed by depositing metal in a second opening of a second photoresist layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Sri Chaitra J. Chavali, Liwei Cheng, Siddharth K. Alur, Sheng Li
  • Patent number: 11387071
    Abstract: Apparatus for a multi-source ion beam etching (IBE) system are provided herein. In some embodiments, a multi-source IBE system includes a multi-source lid comprising a multi-source adaptor and a lower chamber adaptor, a plurality of IBE sources coupled to the multi-source adaptor, a rotary shield assembly coupled to a shield motor mechanism configured to rotate the rotary shield, wherein the shield motor mechanism is coupled to a top portion of the multi-source lid, and wherein the rotary shield includes a body that has one IBE source opening formed through the body, and at least one beam conduit that engages the one IBE source opening in the rotary shield on one end, and engages the bottom portion of the IBE sources on the opposite end of the beam conduit.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 12, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Qiwei Liang, Srinivas D Nemani, Ellie Yieh, Douglas Buchberger, Chentsau Chris Ying
  • Patent number: 11367624
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes forming a recess in the first film using the second film as a mask. The second film includes a first layer having carbon and a second layer having carbon formed on the first layer. The second layer has a second carbon density lower than a first carbon density of the first layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Junichi Hashimoto, Kaori Narumiya, Kosuke Horibe, Soichi Yamazaki, Kei Watanabe, Yusuke Kondo, Mitsuhiro Omura, Takehiro Kondoh, Yuya Matsubara, Junya Fujita, Toshiyuki Sasaki
  • Patent number: 11361968
    Abstract: An apparatus and method of processing a workpiece is disclosed, where a coating is applied to a workpiece and the workpiece is subsequently subjected to an etching process. These processes are performed by one semiconductor processing apparatus while the workpiece is scanned relative to the apparatus. A precursor is applied to the workpiece by the apparatus. The apparatus then uses plasma, heat or ultraviolet radiation to activate the precursor to form a coating. After the coating is applied, the apparatus is configured to perform the etching process. In certain embodiments, the etching process is a directional etching process.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Applied Materials, Inc.
    Inventor: Glen F R Gilchrist
  • Patent number: 11346504
    Abstract: A system for dispensing cryogenic liquid includes a container defining an interior with a partition dividing the interior into primary and reserve chambers. Cryogenic liquid within the primary chamber is separated from cryogenic liquid in the reserve chamber. The partition provides a headspace cornrnurrrcation passage. A primary pressure building circuit has an inlet selectively in liquid communication with the primary chamber and an outlet in fluid communication with the headspaces of the primary and reserve chambers. A reserve pressure building circuit has an inlet selectively in liquid communication with the reserve chamber and an outlet in fluid communication with the headspaces of the primary and reserve chambers. An equalizing circuit is selectively in liquid communication with the primary and reserve chambers. A dispensing line is selectively in liquid communication with the primary chamber.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: May 31, 2022
    Assignee: Chart Inc.
    Inventor: Grant Madison
  • Patent number: 11348987
    Abstract: An OLED display substrate, a method of manufacturing the OLED display substrate, and a display device are provided. The OLED display substrate includes a plurality of aperture regions arranged in an array on a base substrate; and a plurality of storage capacitors on the base substrate, an orthographic projection of each storage capacitor of the plurality of storage capacitors on the base substrate having an overlapping region with an orthographic projection of an aperture region corresponding to the storage capacitor in the plurality of aperture regions on the base substrate.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 31, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinling Zhang, Fei Deng
  • Patent number: 11315759
    Abstract: A plasma processing apparatus includes a processing chamber in which a wafer 1 is processed by using plasma, a radio-frequency power supply that supplies radio-frequency power for generating the plasma, a sample table 2 which is arranged in the processing chamber and in which the wafer 1 is mounted, and a DC power supply 106 which is electrically connected to the sample table 2 and which causes the sample table 2 to generate a suction force. The sample table 2 includes a protruded portion 201a that sucks the wafer 1 by the suction force and a level different portion 201b protruding from a lower portion of the protruded portion 201a. A ring 5 that can be in contact with a lower surface of the wafer 1 is provided outside the protruded portion 201a. A space portion 7 formed by the wafer 1, the protruded portion 201a, and the ring 5 is sealed in a state in which the wafer 1 is sucked to an upper surface of the protruded portion 201a of the sample table 2.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 26, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Takamasa Ichino, Kohei Sato, Kazunori Nakamoto
  • Patent number: 11302634
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Patent number: 11302530
    Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 12, 2022
    Assignees: Cambridge Enterprise Limited, Anvil Semiconductors Limited
    Inventors: David John Wallis, Martin Frentrup, Menno Johannes Kappers, Suman-Lata Sahonta
  • Patent number: 11295933
    Abstract: An apparatus for processing a substrate is provided. The apparatus for processing the substrate includes a housing having a process space, a gas supply unit to supply gas into the process space, a support unit including a chuck to support the substrate in the process space and a lower electrode to surround the chuck when viewed from a top, a temperature adjusting plate provided in the housing, a dielectric plate unit coupled to the temperature adjusting plate, and having a dielectric plate disposed in opposite to the substrate supported by the support unit in the process space, and an upper electrode unit coupled to the temperature adjusting plate, and having an upper electrode disposed in opposition to the lower electrode. The dielectric plate unit includes a first base disposed between the dielectric plate and the temperature adjusting plate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 5, 2022
    Assignee: PSK INC.
    Inventors: Geon Jong Kim, Tae Hwan Youn, Jong Chan Lee
  • Patent number: 11270890
    Abstract: Methods for etching features into carbon material using a metal-doped carbon-containing hard mask to reduce and eliminate redeposition of silicon-containing residues are provided herein. Methods involve depositing a metal-doped carbon-containing hard mask over the carbon material prior to etching the carbon material, patterning the metal-doped carbon-containing hard mask, and using the patterned metal-doped carbon-containing hard mask to etch the carbon material such that the use of a silicon-containing mask during etch of the carbon material is eliminated.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 8, 2022
    Assignee: Lam Research Corporation
    Inventors: Amit Jain, Anne Le Gouil, Yasushi Ishikawa
  • Patent number: 11264487
    Abstract: A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Yee-Chia Yeo
  • Patent number: 11264265
    Abstract: Provided is a lift pin for an epitaxial growth apparatus, which can prevent the back surface of a silicon wafer from being damaged by the lift pin, reduce emission of dust due to the rubbing of the lift pin against the wall surface of a through hole in a susceptor, and prevent peeling of glassy carbon. The lift pin has a straight trunk part to be inserted through the through hole; a head part to be made to abut a silicon wafer; and a cover part covering at least a top of the head part. The straight trunk part and the head part are made of a porous body, the cover part is made of a carbon-based covering material, and at least part of voids of the porous body of the head part is filled with the cover part.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 1, 2022
    Assignee: SUMCO CORPORATION
    Inventor: Masaya Sakurai
  • Patent number: 11249393
    Abstract: A method is described for modifying the mechanical properties of NIL materials. The method includes applying an imprint mask to a nano-imprint lithography (NIL) material layer to create an imprinted NIL material layer, with the NIL material layer comprised of a NIL material. The method further includes detaching the imprinted NIL material layer from the imprint mask, with the modulus level of the NIL material below a flexibility threshold to cause a shape of the imprinted NIL material layer to remain unchanged after detachment. The modulus level of the NIL material of the imprinted NIL material layer is increased beyond a strength threshold to create a first imprint layer, with the imprint layer having a structure that remains unaffected by a subsequent process to form a second imprint layer matching a master mold pattern.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 15, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Austin Lane, Matthew E. Colburn, Giuseppe Calafiore, Nihar Ranjan Mohanty
  • Patent number: 11244833
    Abstract: The present disclosure provides a self-aligned two-time forming method capable of preventing sidewalls from being deformed, comprises sequentially growing a first silicon nitride layer, a first silicon oxide layer, a titanium nitride layer, a second silicon oxide layer, a second silicon nitride layer and a polysilicon layer on a via layer from bottom to top; defining a pattern by using the polysilicon layer as a hard mask, and etching the second silicon nitride layer to an upper surface of the second silicon oxide layer to form a plurality of silicon nitride pattern structures from the second silicon nitride layer; forming sidewalls on sidewalls of the plurality of silicon nitride pattern structures; removing the silicon nitride pattern structures in the sidewalls; etching the silicon nitride layer and the titanium nitride layer by using the sidewalls as a hard mask to form a titanium nitride pattern structure.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: February 8, 2022
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Aimei Lin
  • Patent number: 11239176
    Abstract: A package comprising a carrier, an electronic component mounted on the carrier, and an identifier indicative of an origin of the package and being formed on and/or in the carrier is disclosed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jochen Dangelmaier, Klaus Elian
  • Patent number: 11226567
    Abstract: Methods and associated apparatus for reconstructing a free-form geometry of a substrate, the method including: positioning the substrate on a substrate holder configured to retain the substrate under a retaining force that deforms the substrate from its free-form geometry; measuring a height map of the deformed substrate; and reconstructing the free-form geometry of the deformed substrate based on an expected deformation of the substrate by the retaining force and the measured height map.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 18, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Richard Johannes Franciscus Van Haren, Leon Paul Van Dijk, Ilya Malakhovsky, Ronald Henricus Johannes Otten, Mahdi Sadeghinia
  • Patent number: 11198796
    Abstract: A polishing liquid containing abrasive grains, a hydroxy acid, a polyol, a cationic compound, and a liquid medium, in which a zeta potential of the abrasive grains is positive and a weight average molecular weight of the cationic compound is less than 1000.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 14, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tomohiro Iwano, Takaaki Matsumoto, Tomoyasu Hasegawa
  • Patent number: 11183392
    Abstract: According to an embodiment of the present disclosure, a method of manufacturing semiconductor device includes: forming a first mandrel and a second mandrel over a mask layer; depositing a spacer layer over the first mandrel and the second mandrel; forming a line-end cut pattern over the spacer layer between the first mandrel and the second mandrel; depositing a protection layer over the line-end cut pattern; etching the protection layer and exposing upper portion of the line-end cut pattern; reducing a width of the line-end cut pattern; etching the spacer layer to expose the first mandrel and the second mandrel; and patterning the mask layer using the etched spacer layer and the reduced line-end cut pattern as an etch mask.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Chao-Kuei Yeh, Ying-Hao Wu, Tai-Yen Peng, Chih-Hao Chen, Chih-Sheng Tian
  • Patent number: 11164874
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a dielectric layer on a sidewall of the opening; performing a dry etching process to form a hole in the conductive portion; removing the dielectric layer; and depositing a conductive pattern over the sidewall of the opening and in the hole.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 2, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Chang-Hyeon Nam, Injoon Yeo
  • Patent number: 11152252
    Abstract: An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Sean Teehan, Alex J. Varghese
  • Patent number: 11133195
    Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nelson Felix, Ekmini Anuja De Silva, Praveen Joseph, Ashim Dutta
  • Patent number: 11121092
    Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 14, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Lin Chen, Yunfei Liu, Meng Wang
  • Patent number: 11112625
    Abstract: An optical transmission device has a modulator, a first terminal groove, and relay groove. The modulator has a groove on a waveguide formed on a substrate. EO polymer is placed in the groove in the modulator. The modulator modulates light propagated through the waveguide by changing the phase of the light propagated through the waveguide through change of the refractive index of the EO polymer placed in the groove in the modulator by means of an electric signal. The first terminal groove is formed on the substrate and has a width larger than a width of the groove in the modulator. The relay groove is formed on the substrate and communicates with the groove in the modulator and the first terminal groove. Furthermore, the EO polymer is placed in the relay groove and the first terminal groove.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 7, 2021
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventors: Masaki Sugiyama, Tamotsu Akashi
  • Patent number: 11107729
    Abstract: A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11090866
    Abstract: In a an apparatus and a method for manufacturing a stereoscopic shape using a laser and a powder, the apparatus includes a chamber, a powder supplier, a table, a cotter, a first laser head, a first stage, a second laser head and a second stage. The powder supplier provides a predetermined quantity of powder. The powder is sequentially integrated to be a plurality of powder layers in the table. The cotter moves between the powder supplier and the table, and forms the powder to be a predetermined thickness. The first laser head has a first scanner and a first F theta lens, and irradiates a first laser beam to the powder layer. The first stage transfers the first laser head. The second laser head has a second scanner and a second F theta lens, and irradiates a second laser beam. The second stage transfers the second laser head.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: August 17, 2021
    Assignee: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Hyon-kee Sohn, Dong-sig Shin
  • Patent number: 11081432
    Abstract: The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: August 3, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Koshun Saito, Tsuyoshi Tachi
  • Patent number: 11078380
    Abstract: A method of CMP includes providing a slurry solution including ?1 per-compound oxidizer in a concentration between 0.01 M and 2 M with a pH from 2 to 5 or 8 to 11, and ?1 buffering agent which provides a buffering ratio ?1.5 that compares an amount of a strong acid needed to reduce the pH from 9.0 to 3.0 as compared to an amount of strong acid to change the pH from 9.0 to 3.0 without the buffering agent. The slurry solution is exclusive any hard slurry particles or has only soft slurry particles that have throughout a Vickers hardness <300 Kg/mm2 or Mohs Hardness <4. The slurry solution is dispensed on a hard surface having a Vickers hardness >1,000 kg/mm2 is pressed by a polishing pad with the slurry solution in between while rotating the polishing pad relative to the hard surface.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 3, 2021
    Assignees: Entegris, Inc., University of Florida Research Foundation, Inc.
    Inventors: Rajiv K. Singh, Arul Arjunan, Deepika Singh, Chaitanya Ginde, Puneet N. Jawali
  • Patent number: 11073763
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 11043559
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Hsiu Wang, Yean-Zhaw Chen, Ying-Ting Hsia, Jhao-Ping Jiang, Chun-Chih Cheng
  • Patent number: 11036202
    Abstract: Systems and methods for real time semiconductor manufacturing cluster tool health monitoring are provided via an in-situ sensor. In a method embodiment, an operation procedure for pumping/venting load lock (LL), and LL doors facing vacuum transfer module (VTM) and equipment front end module (EFEM), sensor installation location and operation procedure, and data flow and analysis process are provided. The sensor provides real-time data and monitors airborne particle contamination on EFEM, load lock (LL), and VTM, and plurality of process modules (PMs) simultaneously by correlating door open/close time and vent/pump timing in the loadlock to the particle measurement data. The method further provides an operation for determining that a maintenance procedure is recommended on one of the EFEM, the LL, the VTM, or the plurality of PMs based on the real time measurement data, door state data, and using machine learning algorithms.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 15, 2021
    Assignee: Lam Research Corporation
    Inventors: Hossein Sadeghi, Scott Baldwin
  • Patent number: 11004731
    Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 11, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Yumiko Miyano
  • Patent number: 11004718
    Abstract: Compositions and designs are described for a sectional porous carrier used in processing microelectronics where thin device substrates are affixed by adhesive to the carrier and form an impervious bonded stack that is resistant to thermal and chemical products during processing and is easily handled by a substrate handling vacuum robot, and subsequently allows rapid removal (debonding) in batch operations by directional penetration into sectional porous regions by selective liquids which release the carrier from the device wafer without harm. The invention carrier with porous regions is used for temporary support of thin and fragile device substrates having capabilities of selective penetration of chemical liquids to pass through the porous regions, access and breakdown the bonding adhesive, and allow it to release without damage to the device substrate.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 11, 2021
    Inventors: John Cleaon Moore, Alexander Joseph Brewer, Jared Michael Pettit, Alman XiMin Law