Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.

Abstract: A MOS-gate silicon carbide semiconductor device has an interlayer insulating film that covers a gate electrode and that has a 2-layer structure in which a NSG film and a BPSG film are sequentially stacked. The BPSG film has a boron concentration in a range from 4.5 mol % to 8.0 mol %. The BPSG film has a phosphorus concentration in a range from 1.0 mol % to 3.5 mol %. The NSG film has a thickness in a range from 50 nm to 400 nm. The BPSG film has a thickness in a range from 400 nm to 800 nm. A distance from the gate insulating film to the BPSG film is at most 100 nm at a portion where the gate insulating film and the BPSG film oppose each other across the NSG film.

Abstract: Provided is an insulating coating composition. The composition is highly safe, in which an organic material to form an insulating film is dissolved highly stably. The composition can form an insulating film by coating, where the insulating film has a low relative permittivity, a high insulation resistance, and high wettability and allows an upper layer to be formed thereon by coating. The insulating coating composition according to the present invention contains a cyclic olefin copolymer and a solvent. The cyclic olefin copolymer is a copolymer between a cyclic olefin and a chain olefin. The solvent includes a compound represented by Formula (1) and having a normal boiling point of 100° C. to lower than 300° C. In Formula (1), Ring Z is a ring selected from a 5- or 6-membered saturated or unsaturated cyclic hydrocarbon and a benzene ring; and R1 is selected from a hydrocarbon group and acyl. Ring Z has a substituent or substituents including the R1O group.

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Abstract: In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.

Abstract: A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls.

Abstract: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

Abstract: A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract: A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.

Abstract: Disclosed herein is a method of forming a coating, comprising applying a first coating to a substrate having a plurality of topographical features, planarizing a top surface of the first coating, and drying the coating after planarizing the top surface of the first coating. The first coating may be applied over the plurality of topographical features, and substantially liquid during application. The first coating may optionally be a conformal coating over topographical features of the substrate. The conformal coating may be dried prior to planarizing the top surface of the first coating and a solvent applied to the conformal coating, with the top surface of the conformal coating being substantially planar after application of the solvent. The coating may have a planar surface prior to the drying the first coating and the first coating may be dried without substantial spin-drying by modifying an environment of the first coating.

Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.

Abstract: A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump.

Abstract: The present invention provides; a method for forming a metal oxide film which has both a surface irregularity and a predetermined pattern or either and has few unevenness of surface specific resistance, light transmittance and the like, and such the metal oxide film. The method for forming a metal oxide film having both a surface irregularity and a predetermined pattern or either on a substrate, wherein, the method comprises a first process in which a liquid material containing a metal salt is applied on the substrate to form a metal salt film, a second process in which a surface irregularity or a predetermined pattern is formed to the metal salt film, and a third process in which the metal salt film is converted to a metal oxide film by thermal oxidation treatment or plasma oxidation treatment.

Abstract: A shadow masking device for use in the semiconductor industry includes self-aligning mechanical components that permit shadow masks to be exchanged while maintaining precise alignment with the target substrate. The misregistration between any two of the various layers in the formed structure can be kept to less than 40 microns.

Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy (“MW dielectric layers”). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow.

Abstract: Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed.

Abstract: Porous nano-imprint lithography templates may include pores, channels, or porous layers arranged to allow evacuation of gas trapped between a nano-imprint lithography template and substrate. The pores or channels may be formed by etch or other processes. Gaskets may be formed on an nano-imprint lithography template to restrict flow of polymerizable material during nano-imprint lithography processes.

Abstract: The invention relates to a method enabling to apply cheap manufacturing techniques for producing reliable and robust organic thin film device (EL) comprising the steps of providing (P) a transparent substrate (1) at least partly covered with a first layer stack comprising at least one transparent layer (2), preferably an electrically conductive layer, and a pattern of first and second opaque conductive areas (31, 32) deposited on top of the transparent layer (2), depositing (D) a photoresist layer (4) made of an electrically insulating photoresist resist material on top of the first layer stack at least fully covering the second opaque conductive areas (32), illuminating (IL) the photoresist layer (4) through the transparent substrate (1) with light (5) of a suitable wavelength to make the photoresist material soluble in the areas (43) of the photoresist layer (4) having no opaque conductive areas (31, 32) underneath, removing (R) the soluble areas (43) of the photoresist layer (4), heating (B) the areas (42)

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract: A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Abstract: The present invention provides a production method of a semiconductor device, involving formation of a flattening layer and easy process for layers formed on a semiconductor layer, and also provides a semiconductor device preferably produced by such a production method. The present invention further provides an exposure apparatus preferably used in such a production method.

Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.

Abstract: In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.

Abstract: In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.

Abstract: It is disclosed an over-coating agent for forming fine patterns which is applied to cover a substrate having thereon photoresist patterns and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed substantially completely to form or define fine trace patterns, further characterized by containing either a water-soluble polymer and an amide group-containing monomer or a water-soluble polymer which contains at least (meth)acrylamide as a monomeric component. Also disclosed is a method of forming fine-line patterns using any one of said over-coating agents. According to the invention, the thermal shrinkage of the over-coating agent for forming fine patterns in the heat treatment can be extensively increased, and one can obtain fine-line patterns which exhibit good profiles while satisfying the characteristics required of semiconductor devices.

Abstract: It is disclosed a method of forming fine patterns comprising: covering a substrate having photoresist patterns thereon made of a photoresist composition which is sensitive to high energy light rays with wavelength of 200 nm or shorter or electron beam radiation, with an over-coating agent for forming fine patterns, applying heat treatment to cause thermal shrinkage of the over-coating agent so that the spacing between adjacent photoresist patterns is lessened by the resulting thermal shrinking action, and removing the over-coating agent substantially completely. The present invention provides a method of forming fine patterns whereby fine patterns having pattern width or diameter of 100 nm or shorter and being excellent in uniformity (in-plane uniformity), etc. can be formed by ultrafine processing using high energy light rays with wavelength of 200 nm or shorter or electron beams.

Abstract: Optimizing the regrowth over epitaxial layers during manufacture of a distributed feedback laser. In one example embodiment, a method for depositing an InP regrowth layer on an epitaxial base portion of a distributed feedback laser includes growing a first portion of the regrowth layer at an initial substrate temperature of approximately 580 degrees Celsius to a thickness between approximately 300 Angstroms and approximately 900 Angstroms, increasing the substrate temperature from the initial substrate temperature to an increased substrate temperature of approximately 660 degrees Celsius, growing a second portion of the regrowth layer at the increased substrate temperature, doping a first part of an uppermost layer of the regrowth layer at a concentration of approximately 8.00*10^17/cm3 at the increased substrate temperature, and doping a second part of the uppermost layer of the regrowth layer at a concentration between approximately 1.90*10^18/cm3 and approximately 2.

Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy (“MW dielectric layers”). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow.

Abstract: A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a reflowed photoresist pattern surrounding the metal line pattern, forming a metal-insulator-metal (MIM) layer over the semiconductor substrate provided with the reflowed photoresist pattern, and removing the MIM layer arranged over the photoresist pattern and the photoresist pattern.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A method and system for treating a dielectric film on a plurality of substrates includes disposing the plurality of substrates in a batch processing system, the dielectric film on the plurality of substrates having a dielectric constant value less than the dielectric constant of SiO2. The plurality of substrates are heated, and a treating compound comprising a CxHy containing compound, wherein x and y represent integers greater than or equal to unity is introduced to the process system. A plasma is formed and at least one surface of the dielectric film on said plurality of substrates is exposed to the plasma.

Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.

Abstract: Provided are a tape, apparatus, and method that relate generally to a single layer adhesive which functions as a dicing tape and also as a die attach adhesive for dicing thinned wafers and subsequent die attach operations of the diced chips in semiconductor device fabrication. The tape, apparatus, and method include a backing with a surface modification that includes a pattern.

Abstract: Provided are methods of fabricating a semiconductor device including a phase change layer. Methods may include forming a dielectric layer on a substrate, forming an opening in the dielectric layer and depositing, on the substrate having the opening, a phase change layer that contains an element that lowers a process temperature of a thermal treatment process to a temperature that is lower than a melting point of the phase change layer. Methods may include migrating a portion of the phase change layer from outside the opening, into the opening by the thermal treatment process that includes the process temperature that is lower than the melting point of the phase change layer.

Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.