Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 11177162
    Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Koichi Motoyama, Christopher J. Penny, Lawrence A. Clevenger
  • Patent number: 11145543
    Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Patent number: 11133205
    Abstract: Apparatus and methods to process one or more substrate are described. A processing chamber comprises a support assembly, a chamber lid, and a controller. The chamber lid has a front surface facing the support assembly, a first sensor on the front surface and a second sensor on the front surface, the first sensor positioned at a first distance from the central rotational axis, and the second sensor positioned at a second distance from the central rotational axis greater than the first distance. The controller is configured to determine if a substrate is within or outside of the substrate support region of the support assembly.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sanggyum Kim, Prasanth Narayanan, Subramanian Tamilmani, Mandyam Sriram
  • Patent number: 11131023
    Abstract: A film deposition apparatus includes a process chamber and a turntable provided in the process chamber. The turntable includes a substrate receiving region to receive a substrate thereon and provided along a circumferential direction of the turntable. A source gas supply unit extending along a radial direction of the turntable is provided above the turntable with a first distance from the turntable such that the source gas supply unit covers an entire length of the substrate receiving region in the radial direction. An axial-side supplementary gas supply unit is provided in the vicinity of the source gas supply unit and above the turntable with a second distance from the turntable. The second distance is longer than the first distance. The axial-side supplementary gas supply unit covers a predetermined region of the substrate receiving region on the axial side in the radial direction of the turntable.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 28, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Shigehiro Miura, Jun Sato
  • Patent number: 11090691
    Abstract: A cleaning method for cleaning a frame unit including an affixed object, a tape affixed to an undersurface of the affixed object, and an annular frame to which an outer peripheral portion of the tape is affixed, the cleaning method including: an affixed object cleaning step of cleaning the affixed object by jetting a cleaning liquid from a cleaning nozzle while moving the cleaning nozzle in a reciprocating manner along a path extending from above one end of an outer peripheral edge of the affixed object to above another end of the outer peripheral edge of the affixed object; and a frame cleaning step of cleaning the frame by jetting the cleaning liquid from the cleaning nozzle to the frame.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 17, 2021
    Assignee: DISCO CORPORATION
    Inventors: Yukito Akutagawa, Toshio Tsuchiya, Kentaro Shiraga
  • Patent number: 11094830
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 17, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11078598
    Abstract: A silicon carbide single crystal is grown by a method comprising: a single crystal growth step of growing a silicon carbide single crystal so as to not close a gap between a side surface of the silicon carbide single crystal growing on a silicon carbide seed crystal, and an inner-side surface of a guide member and a crystal deposited on the inner-side surface of the guide member; a crystal growth termination step of terminating crystal growth by temperature lowering; and a gap enlargement step, performed between the single crystal growth step and the crystal growth termination step, of enlarging the gap by maintaining a difference, Pin?Pout, between partial pressure Pin of Si2C in a source gas in the vicinity of an inlet of the gap and partial pressure Pout of Si2C in a source gas in the vicinity of an outlet of the gap at 0.18 torr or less.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 3, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yohei Fujikawa, Hidetaka Takaba
  • Patent number: 11063123
    Abstract: At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 13, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin'ichi Nakamata, Masanobu Iwaya, Keiji Okumura
  • Patent number: 11049716
    Abstract: Provided herein are methods of filling gaps using high density plasma chemical vapor deposition (HDP CVD). According to various implementations, carbon-containing films such as amorphous carbon and amorphous carbide films are deposited by HDP CVD into gaps on substrates to fill the gaps. The methods may involve using high hydrogen-content process gasses during HDP CVD deposition to provide bottom-up fill. Also provided are related apparatus.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 29, 2021
    Assignee: Lam Research Corporation
    Inventors: Wei Tang, Jason Daejin Park, Bart J. van Schravendijk, Shu Tsai Wang, Kaihan Abidi Ashtiani
  • Patent number: 11047044
    Abstract: A film forming apparatus includes: a substrate holding member for vertically holding target substrates at predetermined intervals in multiple stages; a process vessel for accommodating the substrate holding member; a processing gas introduction member each having gas discharge holes which discharge a processing gas for film formation in a direction parallel to each target substrate and introduce the processing gas into the process vessel; an exhaust mechanism for exhausting the interior of the process vessel; and a plurality of gas flow adjustment members installed to face the target substrates, respectively. Each of the gas flow adjustment members adjusts a gas flow of the processing gas discharged horizontally above each of the target substrates from the gas discharge holes of the processing gas introduction member, to be directed from above the respective target substrate located below the respective gas flow adjustment member toward the surface of the respective target substrate.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 29, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Takezawa, Kuniyasu Sakashita, Shigeru Nakajima
  • Patent number: 11043363
    Abstract: A plasma processing method is performed by a plasma processing apparatus that includes a process chamber, a conductive first component that is disposed in the process chamber and at least a surface of which is covered with a conductive silicon material, and a second component that is disposed in the process chamber and is at a ground potential or a floating potential with respect to an electric potential of plasma. The method includes forming an oxide layer on the surface of the first component by converting an oxygen-containing gas into plasm, and treating a surface of the second component by converting a halogen-containing gas into plasm.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 22, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Hirotaka Mikami
  • Patent number: 11043390
    Abstract: The invention relates to the chemical etching of a semiconductor material, including: deposition at least one mask (PLP) on a first surface zone of a semiconductor material (SC); and chemically etching (S31) a second surface zone of the semiconductor material (SC) that is not covered by the mask (PLP). In particular, the aforementioned mask is produced in a material including polyphosphazene, which material protects the underlying semiconductor especially well.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 22, 2021
    Assignee: Centre National De La Recherche Scientifique
    Inventors: Arnaud Etcheberry, Anne-Marie Goncalves, Jean-Luc Pelouard, Mathieu Fregnaux, Anais Loubat
  • Patent number: 11041243
    Abstract: The invention relates to coating precursor nozzle (15) for subjecting a surface of a substrate (5) to a coating precursor. The nozzle (15) having a nozzle output face (10a), first and second nozzle side edges (31, 32), and first and second nozzle end edges (33, 34). The coating precursor nozzle (15) comprising a precursor supply channel (16), a first discharge channel (17a), a first cross purge gas channel (18a), a second cross purge gas channel (18b), a first edge purge gas channel (19a) and at least one first auxiliary purge gas channel (20). The invention further relates to a nozzle head (1).
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 22, 2021
    Assignee: BENEQ OY
    Inventor: Pekka T. Soininen
  • Patent number: 11031474
    Abstract: A semiconductor device is provided with: a substrate; a first region provided above the substrate; a second region provided away from the first region in a first direction; a third region provided between the first region and the second region, the third region facing an electrode portion; a fourth region provided between the first region and the third region; and a fifth region provided between the second region and the third region. The fourth and fifth regions include carbon (C). Carbon concentrations in the first and second regions are lower than carbon concentrations in the fourth and fifth regions.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiyuki Kondo
  • Patent number: 11020776
    Abstract: A substrate cleaning method includes a processing liquid supplying step which supplies a processing liquid that contains a solute and a volatile solvent to an upper surface of a substrate, a film forming step in which the solvent is at least partially volatilized from the processing liquid and solidified or hardened to form a particle holding layer on the upper surface of the substrate, and a removal step in which a peeling liquid is supplied to the upper surface of the substrate to peel and remove the particle holding layer. A solute composition in the solute is insoluble in the peeling liquid before being heated to a temperature equal/higher than a quality-changing temperature to become soluble in the peeling liquid. During film forming, the processing liquid is heated to a temperature below the quality-changing temperature, to form the particle holding layer, without changing the quality of the solute composition.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 1, 2021
    Inventor: Yukifumi Yoshida
  • Patent number: 11024737
    Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan
  • Patent number: 11001924
    Abstract: Provided is a processing container formed of a reaction tube and a manifold that supports the reaction tube from below, and adapted to process a substrate inside, a nozzle adapted to supply a processing gas to the substrate, and a connecting portion adapted to erect the nozzle inside the processing container. The connecting portion includes (1) a fixing portion formed of a cylindrical portion inserted into an introduction portion provided at the manifold, and a flange plate formed at an end portion of the cylindrical portion, and (2) a detachable portion formed of an elbow engaged with the flange plate, and an installation portion in which the nozzle is installed.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 11, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Hidenari Yoshida
  • Patent number: 10998857
    Abstract: A resonator including a lower electrode, an upper electrode, and a piezoelectric film that is formed between the lower electrode and the upper electrode. A MEMS device is provided that includes an upper lid that faces the upper electrode, and a lower lid that faces the lower electrode and that seals the resonator together with the upper lid. A CMOS device is mounted on a surface of the upper lid or the lower lid opposite a surface that faces the resonator. The CMOS device includes a CMOS layer and a protective layer that is disposed on a surface of the CMOS layer opposite a surface that faces the resonator. The upper or lower lid to which the CMOS device is joined includes a through-electrode that electrically connects the CMOS device to the resonator.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 4, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keiichi Umeda, Tadayuki Okawa, Taku Kamoto
  • Patent number: 10987653
    Abstract: A composite comprises a carbonaceous and a metallic nanotube conjugated with a carbonaceous support. The composite may be used to remove contaminants from water.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 27, 2021
    Assignee: AUBURN UNIVERSITY
    Inventors: Dongye Zhao, Wen Liu
  • Patent number: 10957800
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10943806
    Abstract: A substrate processing technique includes: a first heating device configured to heat a substrate to a first processing temperature; a first process chamber provided with the first heating device; a second heating device configured to heat the substrate to a second processing temperature utilizing microwaves, the second processing temperature being higher than the first processing temperature; a second process chamber provided with the second heating device; a substrate placement portion configured to load and unload the substrate with respect to the first process chamber and the second process chamber by placing and rotating the substrate; and a controller configured to respectively control the first heating device, the second heating device, and the substrate placement portion.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 9, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kazuyuki Toyoda, Kazuhiro Yuasa, Tetsuo Yamamoto
  • Patent number: 10937664
    Abstract: Methods and systems for surface modification are described. In an embodiment, a method of etching includes providing a substrate having a device structure, portions of which are identified for modification. Such a method may also include passivating target surfaces of the device structure by exposing the device structure to a gas-phase composition at a processing pressure equal to or greater than 100 mTorr to form a protection layer on the target surfaces. Other embodiments of a method may include providing a substrate having a device structure, portions of which identified for removal. Such methods may further include passivating target surfaces of the device structure by exposing the device structure to a gas-phase composition, wherein the ratio of the radical content to the ion content exceeds 10-to-1.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Cedric Thomas, Andrew Nolan, Alok Ranjan
  • Patent number: 10930527
    Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
  • Patent number: 10930503
    Abstract: Processing methods comprising selectively replacing a first pillar material with a second pillar material in a self-aligned process are described. The first pillar material may be grown orthogonally to the substrate surface and replaced with a second pillar material to leave a substantially similar shape and alignment as the first pillar material.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Ziqing Duan, Abhijit Basu Mallick
  • Patent number: 10916418
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel
  • Patent number: 10889009
    Abstract: The present invention relates to a transfer head gripping and transferring micro LEDs from a first substrate to a second substrate. More particularly, the present invention relates to a transfer head gripping and transferring micro LEDs in a batch manner without any error even when there is a height difference of the micro LEDs.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 12, 2021
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10847392
    Abstract: Described herein is a technique capable of forming a film with uniform characteristics from an upper portion to a lower portion of a deep concave structure whose aspect ratio is high. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) placing a substrate comprising a deep concave structure constituted by at least an upper portion and a lower portion on a substrate support provided in a process chamber; (b) supplying a process gas into the process chamber to form a layer on an inner surface of the deep concave structure; and (c) discharging by-products generated in an inner space of the deep concave structure in (b) by setting a pressure of a process space defined by the process chamber to be lower than a pressure of the inner space of the deep concave structure.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 24, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Tsukasa Kamakura
  • Patent number: 10845638
    Abstract: The application provides a color film substrate, a flexible liquid crystal display panel and a preparation method. The color film substrate includes a flexible substrate, a photoresist layer, an alignment layer and black matrix walls. By disposing the three-dimensional black matrix walls with liquid crystal-holding chambers on the color film substrate, liquid crystals can be fixed in the holding chambers for avoiding the uneven cell gap caused by the displacement of the liquid crystals. Thus, the application solves the problem that an existing flexible liquid crystal display panel has severe displacement of the liquid crystals under stress.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 24, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jianlong Huang, Wei Tang
  • Patent number: 10840115
    Abstract: The present invention relates to a micro LED transfer head improving efficiency of transferring micro LEDs.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 17, 2020
    Assignee: POINT ENGINEERING CO., LTD
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10829866
    Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mihir Tungare, Peter Kim, Jianwei Wan, Chankyung Choi
  • Patent number: 10816901
    Abstract: A coater with automatic cleaning function and a coater automatic cleaning method. The coater (100,200,300,400,500,600,700,800) includes a coater chamber (101,201,301,401,501,601,701,801) capable of being filled up with cleaning solution, a substrate chuck (102,202,302,402,502,602,702,802) holding and positioning a substrate (103,203,303,403,503,603,703,803), and at least one shroud (108,208,308,408,508) capable of moving up for preventing photoresist from splashing out of the coater chamber (101,201,301,401,501,601,701,801), or moving down and immersing into the cleaning solution for cleaning.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 27, 2020
    Assignee: ACM Research (Shanghai) Inc.
    Inventors: Hui Wang, Fuping Chen, Wenjun Wang, Hongchao Yang, Voha Nuch, Fufa Chen, Jian Wang, Xiaoyan Zhang, Shu Yang
  • Patent number: 10808318
    Abstract: There is provided a technique that includes: a process chamber accommodating a substrate support supporting substrates in multiple stages to process the substrates; a supply buffer part adjacent the process chamber; a first gas supply part installed in the supply buffer part; a second gas supply part installed in the supply buffer part; an inner wall installed between the supply buffer part and the process chamber, on which a plurality of slits are formed to correspond to the substrates; and a maintenance port disposed at a lower end of the inner wall, wherein the first gas supply part includes a first gas nozzle having a supply hole that supplies first gas into the supply buffer part.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 20, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takeo Hanashima, Tsukasa Kamakura, Takafumi Sasaki, Hidenari Yoshida
  • Patent number: 10796900
    Abstract: Described herein is a technique capable of improving electrical characteristics of a semiconductor device. According to the technique, there is provided a method of manufacturing a semiconductor device including: (a) generating oxygen and hydrogen active species; and (b) forming an oxide layer by supplying the oxygen and hydrogen active species to a substrate with a concave structure to subject a film on an inner surface of the concave structure to oxidation, wherein the oxide layer is formed in (b) such that a thickness of the oxide layer is greater on the inner surface than at an upper end portion of the concave structure by setting a ratio of a flow rate of the hydrogen active species to a total flow rate to a predetermined ratio greater than a first ratio at which a rate of forming the oxide layer is maximized at the upper end portion of the concave structure.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yuichiro Takeshima, Masanori Nakayama, Katsunori Funaki, Yasutoshi Tsubota, Hiroto Igawa
  • Patent number: 10796910
    Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Ko, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10790409
    Abstract: A nitride semiconductor light-emitting element includes at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. A multilayer body is provided between the n-type nitride semiconductor layer and the light-emitting layer, having at least one stack of first and second semiconductor layers. The second semiconductor layer has a greater band-gap energy than the first semiconductor layer. The first and second semiconductor layers each have a thickness of more than 10 nm and 30 nm or less. In applications in which luminous efficiency at room temperature is a high priority, the first semiconductor layer has a thickness of more than 10 nm and 30 nm or less, the second semiconductor layer has a thickness of more than 10 nm and 40 nm or less, and the light-emitting layer has V-shaped recesses in cross-sectional view.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiko Tani, Tetsuya Hanamoto, Masanori Watanabe, Akihiro Kurisu, Katsuji Iguchi, Hiroyuki Kashihara, Tomoya Inoue, Toshiaki Asai, Hirotaka Watanabe
  • Patent number: 10777408
    Abstract: A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a flexible substrate and a buffer stack overlying the substrate. The buffer stack comprises at least one epitaxial buffer layer. An epitaxial doped layer comprised predominantly of silicon overlies the at least one epitaxial buffer layer. Mobility of the device is greater than 100 cm2/Vs and carrier concentration of the epitaxial doped layer is less than 1016 cm?3.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: September 15, 2020
    Assignee: University of Houston System
    Inventors: Venkat Selvamanickam, Pavel Dutta, Ying Gao
  • Patent number: 10738381
    Abstract: Disclosed are a substrate holder and a semiconductor manufacturing apparatus including the substrate holder. The substrate holder provides a reaction region by making face-sealing contact with a reactor wall. The substrate holder has an elastic behavior when pressure is applied thereto while the substrate holder makes face-sealing contact with the reactor wall. The semiconductor manufacturing apparatus includes the substrate holder and a gas supply unit configured to supply gas to the reaction region provided by the reactor wall and the substrate holder.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 11, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Hyun Soo Jang, Jeong Ho Lee, Woo Chan Kim, Sung Hoon Jun, Jong Won Shon
  • Patent number: 10741426
    Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
  • Patent number: 10720324
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a film on a substrate by causing a first precursor and a second precursor to intermittently react with each other by repeating a cycle a plurality of times, the cycle alternately performing supplying the first precursor, which satisfies an octet rule and has a first pyrolysis temperature, to the substrate and supplying the second precursor, which does not satisfy the octet rule and has a second pyrolysis temperature lower than the first pyrolysis temperature, to the substrate. In the act of forming the film, a supply amount of the first precursor is set larger than a supply amount of the second precursor.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 21, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kimihiko Nakatani, Hiroshi Ashihara, Hajime Karasawa, Kazuhiro Harada
  • Patent number: 10711372
    Abstract: A silicon carbide epitaxial wafer manufacturing method includes: a stabilization step of nitriding, oxidizing or oxynitriding and stabilizing silicon carbide attached to an inner wall surface of a growth furnace; after the stabilization step, a bringing step of bringing a substrate in the growth furnace; and after the bringing step, a growth step of epitaxially growing a silicon carbide epitaxial layer on the substrate by supplying a process gas into the growth furnace to manufacture a silicon carbide epitaxial wafer.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihito Ohno, Kenichi Hamano, Takashi Kanazawa
  • Patent number: 10699923
    Abstract: The present invention includes a transfer system for flipping and checking electronic devices. A first rotary device has a plurality of transfer heads configured to pick electronic devices from a wafer table and place the electronic devices on a transfer head of a second rotary device. Check stations can be positioned around the first and second rotary devices and configured to inspect or check the electronic devices during the flipping process. The transfer system can further include an imaging device to inspect the accuracy of picking and placing of the electronic devices during the flipping process. The wafer table and the first rotary device are inclined to increase the operation space. The system accurately picks, flips and transfers chips at a high operation speed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 30, 2020
    Assignee: MIT SEMICONDUCTOR PTE LTD
    Inventors: Siong Huat Neo, Kim Mone Kwong, Kok Yeow Lim, Zhi Qiang Mao
  • Patent number: 10685814
    Abstract: A system for processing substrates having an atmospheric front end and a vacuum main frame, primary processing chambers attached to the main frame, a loadlock positioned between the front end and the main frame, and at least one secondary processing chamber attached to the loadlock.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 16, 2020
    Assignee: ADVANCED MICRO-FABRICATION EQUIPMENT INC. CHINA
    Inventors: Heng Tao, Tuqiang Ni, Qian Wang
  • Patent number: 10658204
    Abstract: A substrate processing system to treat a substrate includes a spin chuck configured to hold and rotate a substrate. A heating assembly is configured to heat an opposite surface of the substrate and includes a main heater assembly and a nozzle stack cap. The main heater assembly includes a first plurality of light emitting diodes (LEDs) arranged on a first printed circuit board (PCB) in a first plane that is spaced from and parallel to a second plane including the substrate. The nozzle stack cap assembly includes at least one nozzle to dispense liquid onto a center of a first surface of the substrate. A radiant heat source is arranged closer to the substrate than the first plane and is configured to heat the center of the first surface of the substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 19, 2020
    Assignee: LAM RESEARCH AG
    Inventors: Bridget Hill, Michael Puggl, Gerhard Mueller, Henry Roger Osner, Karl-Heinz Hohenwarter, Ulrich Tschinderle, Daniel Brien
  • Patent number: 10640871
    Abstract: A heat treatment system includes a heating unit that heats an inside of a processing chamber in which a plurality of workpieces are accommodated; a heat treatment condition storing unit that stores a heat treatment condition; a heat treatment change model storing unit that stores a heat treatment change model; a heat treatment performing unit that performs the heat treatment condition; a heat treatment result receiving unit that receives a result of heat treatment performed; and an optimum temperature calculating unit that calculate a target heat treatment result for an in-plane shape of the workpiece based on a target heat treatment result and information about a shape of the target heat treatment result, and calculate an optimum temperature that results in the target heat treatment result, based on the calculated target heat treatment result and the heat treatment change model.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 5, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuichi Takenaga, Hiroichi Ota, Shingo Sekisawa
  • Patent number: 10636788
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
  • Patent number: 10600644
    Abstract: Processes for fabricating multi- and monolayer silicene on catalyst metal surfaces by means of plasma-enhanced chemical vapor deposition (PECVD). Silicene is grown by means of PECVD from a starting mixture of H2 and SiH4 having an H2:SiH4 ratio of 100 to 400 on an Ag(111) substrate having a substrate temperature between 20° C. and 290° C., with the deposition being performed for about 10-25 minutes at an RF power between 10 W and 500 W and under a chamber pressure between about 100 mTorr and 1300 mTorr. In most cases, the substrate will be in the form of an Ag(111) film sputtered on a fused silica substrate. A multi-layer silicene film can be formed by extending the deposition time past 25 minutes.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 24, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Xiao Liu, Battogtokh Jugdersuren
  • Patent number: 10593842
    Abstract: Provided are display device and method for fabricating the same. According to an aspect of the present disclosure, there is provided a display device comprising: a first substrate; at least one wavelength conversion layer disposed on the first substrate; a capping layer disposed on the wavelength conversion layer and comprising a porous layer; and a first polarizing layer disposed on the capping layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 17, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Gu Kim, Taek Joon Lee, Hye Lim Jang, Baek Kyun Jeon, Jin Soo Jung
  • Patent number: 10529543
    Abstract: The present disclosure describes an exemplary etch process in a reactor that includes a shower head and an electrostatic chuck configured to receive a radio frequency (RF) power. The shower head includes a top plate and a bottom plate with one or more gas channels that receive incoming gases. The method can include (i) rotating the top plate or the bottom plate of the shower head to a first position to allow a gas to flow through the shower head; (ii) performing a surface modification cycle that includes: applying a negative direct current (DC) bias voltage to the shower head, applying an RF power signal to the wafer chuck; and (iii) performing an etching cycle that includes: removing the negative DC bias voltage from the shower head and lowering the RF power signal applied to the wafer chuck.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin, Yu Lun Ke
  • Patent number: 10519543
    Abstract: There is provided a technique that includes: a reaction chamber that processes a substrate on a substrate support; a transfer chamber; a gate that opens and closes an opening and is formed in the transfer chamber; a transfer device; a clean unit supplying a clean atmosphere to the transfer chamber; an inert gas supplier supplying an inert gas to the transfer chamber; and a controller controlling the inert gas supplier such that, after the loading of the substrate from a substrate container to the substrate support by the transfer device is completed and the gate is closed, the inert gas supplier supplies the inert gas during a time period until the gate is opened again and does not supply the inert gas in another time period, and control the transfer chamber to be kept at a positive pressure by an air atmosphere.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 31, 2019
    Assignee: Kokusai Electric Corporation
    Inventor: Akinari Hayashi
  • Patent number: 10520833
    Abstract: Semiconductor systems, apparatuses and methods are provided. In one embodiment, an extreme ultraviolet lithography system includes a substrate stage configured to secure a substrate at a first vertical level, wherein the substrate is deposited with a resist layer thereon; at least one electrode positioned at a second vertical level above the first vertical level; and a power source configured to apply an electric field across the at least one electrode and the substrate stage, including across a thickness of the resist layer when the substrate is secured on the substrate stage.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin