Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 11530482
    Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: December 20, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shailendra Srivastava, Sai Susmita Addepalli, Nikhil Sudhindrarao Jorapur, Daemian Raj Benjamin Raj, Amit Kumar Bansal, Juan Carlos Rocha-Alvarez, Gregory Eugene Chichkanoff, Xinhai Han, Masaki Ogata, Kristopher Enslow, Wenjiao Wang
  • Patent number: 11530483
    Abstract: Provided is a substrate processing system for improving productivity of processes. In this regard, the substrate processing system includes: a first chamber providing a space where at least one substrate is accommodated; a second chamber configured to transfer at least one substrate to the first chamber; and a temperature control unit configured to change a temperature of a gas in the second chamber.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 20, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: YoonKi Min, YoungHoon Kim, HakJoo Lee, SeungJu Chun
  • Patent number: 11515396
    Abstract: Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 ?. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Manzar Siddik
  • Patent number: 11495501
    Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 11488804
    Abstract: A shower head assembly for a plasma processing apparatus in which a substrate is accommodatable on a substrate stage within a chamber, a plasma processing apparatus, and a plasma processing method, the shower head assembly including a shower plate including a plurality of injection holes through which a gas is sprayable out toward the substrate; and a compensation plate on a lower surface of the shower plate and facing the substrate, the compensation plate including a first compensating portion having first gas passages of a first length and a second compensating portion having second gas passages of a second length that is greater than the first length, wherein the first gas passage and the second gas passage are respectively in fluid communication with the injection holes.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngwon Shin, Heechul Lee, Joonsung Lee, Hyunjae Jung, Hyungchul Cho
  • Patent number: 11483903
    Abstract: An induction heating system includes a power inverter, an induction circuit, and a control circuit. The power inverter includes one or more transistors configured to receive a direct current (DC) input and produce an alternating current (AC) output. The induction circuit includes at least one working coil configured to receive the AC output and produce a first magnetic field, wherein the first magnetic field interacts with a ferrous material to generate heat in the ferrous material. The control circuit includes a processor and memory. The memory having instructions stored thereon that, when executed by the processor, cause the control circuit to receive an input, from a user, indicating a temperature set point, measure an inductance of the induction circuit, determine a resonant frequency of the induction circuit based on the inductance, and control the one or more transistors of the power inverter based on the resonant frequency and the temperature set point.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 25, 2022
    Assignee: HATCO CORPORATION
    Inventors: Nick Bassill, Fei Shang, Ishan Shah
  • Patent number: 11476089
    Abstract: A control method of a plasma processing apparatus including a first electrode that places a workpiece thereon includes supplying a bias power to the first electrode, and supplying a source power having a frequency higher than that of the bias power into a plasma processing space. The source power has a first state and a second state. The control method further includes a first control process of alternately applying the first state and the second state of the source power in synchronization with a signal synchronized with a cycle of a radio frequency of the bias power, or a phase within one cycle of a reference electrical state that represents any one of a voltage, current, and electromagnetic field measured in a power feeding system of the bias power.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 18, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Chishio Koshimizu, Taichi Hirano, Toru Hayasaka, Shinji Kubota, Koji Maruyama, Takashi Dokan
  • Patent number: 11430816
    Abstract: The present disclosure provides a method for preparing an interlayer insulating layer and a method for manufacturing a thin film transistor, and a thin film transistor, belongs to the field of display technology, and can solve the problem of poor resistance to breakdown of the interlayer insulating layer in the related art. The method for preparing an interlayer insulating layer includes the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 30, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming Wang, Ce Zhao, Wei Song
  • Patent number: 11421323
    Abstract: A stage for mounting a workpiece and an edge ring is provided, the stage including a first flow path and a second flow path along each of which a fluid flows, within the stage; a bifurcation at which an inlet port of the first flow path and an inlet port of the second flow path are coupled; a junction at which an outlet port of the first flow path and an outlet port of the second flow path are coupled; and a member provided at least one of the bifurcation and the junction, the member having at least one opening that communicates with the first flow path and the second flow path.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 23, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Daisuke Hayashi, Shinya Ishikawa
  • Patent number: 11410878
    Abstract: A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsu Yen, Yu Chuan Hsu, Chen-Hui Yang
  • Patent number: 11384420
    Abstract: An adhesion promoting layer is formed on a metallic substrate by generating a non-thermal plasma in air at atmospheric pressure, and exposing a surface of the metallic substrate to the plasma. The plasma oxidizes the metallic substrate to form metal oxide from metal atoms of the metallic substrate. The metal oxide is formed as a metal oxide layer disposed directly on an underlying bulk metallic layer of the metallic substrate. Alternatively, the plasma nitridizes the metallic substrate to form metal nitride from metal atoms of the metallic substrate. The metal nitride is formed as a metal nitride layer disposed directly on an underlying bulk metallic layer of the metallic substrate.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 12, 2022
    Assignee: Atmospheric Plasma Solutions, Inc.
    Inventor: Peter Joseph Yancey
  • Patent number: 11367611
    Abstract: There is provided a film forming method of embedding a film in a groove formed in a front surface of a substrate, which includes: depositing an in-conformal film in the groove formed in the front surface of the substrate while forming a V-like cross-sectional shape in the groove; and embedding a conformal film in the groove by depositing the conformal film.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: June 21, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuji Nishino, Jun Sato
  • Patent number: 11338939
    Abstract: A method of producing a shim for use in an aircraft airframe (200) comprising: providing a plurality of component parts (202, 204) of the aircraft airframe (200); measuring a surface of each of the component parts (202, 204) and creating a digital models of the component part (202, 204) therefrom; digitally assembling together the digital models of the component parts (202, 204) thereby to produce a digital model (600) of at least part of the aircraft airframe (200); using that digital model (600), creating a digital model of a shim (604), the digital model of the shim (604) filling a gap between at least two digital models of component parts (202, 204) in the digital model (600) of at least part of the aircraft airframe (200); and producing a physical shim using the digital model of the shim (604).
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 24, 2022
    Assignee: BAE Systems plc
    Inventors: Jonathan Michael Carberry, Alistair James Fletcher
  • Patent number: 11335873
    Abstract: Disclosed are quantum dot solid-state film, method for preparing same, and quantum dot light-emitting diode. Method comprises: providing quantum dot solution, preparing quantum dot material solid-state film on substrate; before being immersed in surface modifier solution to obtain quantum dot material solid-state film modified by a surface modifier; providing a metal nanoparticle seed solution, using solution method to deposit nanoparticle on quantum dot material solid-state film modified by surface modifier to obtain a quantum dot material solid-state film with the surface having adsorbed a layer of metal nanoparticle seed; before being immersed in a metal nano wire precursor solution, nanoparticle to perform a metal nano wire growth, finally obtaining a quantum dot solid-state film. The quantum dot solid-state film obtained using method of invention can effectively and rapidly transmit electrical charges, improving overall performance of device.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 17, 2022
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventors: Luling Cheng, Yixing Yang
  • Patent number: 11309186
    Abstract: The present disclosure provides a semiconductor device with an air gap for reducing capacitive coupling in a pattern-dense region and a method for preparing the semiconductor device. The semiconductor device includes a first metal plug and a second metal plug disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jar-Ming Ho
  • Patent number: 11302616
    Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: April 12, 2022
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Guilian Gao
  • Patent number: 11217457
    Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungjin Kim, Byung-Hyun Lee, Yoonyoung Choi, Tae-Kyu Kim, Heesook Cheon, Bo-Wo Choi, Hyun-Sil Hong
  • Patent number: 11193207
    Abstract: Treatment chamber (C) for a chemical vapor deposition (CVD) reactor, comprising, within a body (B) defining an enclosure (E) under partial vacuum, a system (3) for injecting reactive species with a view to being deposited on a substrate (8) placed on a support element (5), and a thermal control system (2) for regulating the temperature of the injection system (3) or keeping it substantially constant, this thermal control system (2) having an interface zone (ZI) with the injection system (3). The treatment chamber (C) further comprises, in the interface zone (ZI), at least one thermal transfer zone (ZT) that is (i) insulated from the enclosure under partial vacuum (E) by an insulating barrier to the pressure and to the diffusion of contaminating species and (ii) filled with a thermal interface material (10). Application for carrying out CVD depositions, especially pulsed CVD depositions.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 7, 2021
    Inventors: Patrice Nal, Christophe Borean
  • Patent number: 11177162
    Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Koichi Motoyama, Christopher J. Penny, Lawrence A. Clevenger
  • Patent number: 11145543
    Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Patent number: 11131023
    Abstract: A film deposition apparatus includes a process chamber and a turntable provided in the process chamber. The turntable includes a substrate receiving region to receive a substrate thereon and provided along a circumferential direction of the turntable. A source gas supply unit extending along a radial direction of the turntable is provided above the turntable with a first distance from the turntable such that the source gas supply unit covers an entire length of the substrate receiving region in the radial direction. An axial-side supplementary gas supply unit is provided in the vicinity of the source gas supply unit and above the turntable with a second distance from the turntable. The second distance is longer than the first distance. The axial-side supplementary gas supply unit covers a predetermined region of the substrate receiving region on the axial side in the radial direction of the turntable.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 28, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Shigehiro Miura, Jun Sato
  • Patent number: 11133205
    Abstract: Apparatus and methods to process one or more substrate are described. A processing chamber comprises a support assembly, a chamber lid, and a controller. The chamber lid has a front surface facing the support assembly, a first sensor on the front surface and a second sensor on the front surface, the first sensor positioned at a first distance from the central rotational axis, and the second sensor positioned at a second distance from the central rotational axis greater than the first distance. The controller is configured to determine if a substrate is within or outside of the substrate support region of the support assembly.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sanggyum Kim, Prasanth Narayanan, Subramanian Tamilmani, Mandyam Sriram
  • Patent number: 11094830
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 17, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11090691
    Abstract: A cleaning method for cleaning a frame unit including an affixed object, a tape affixed to an undersurface of the affixed object, and an annular frame to which an outer peripheral portion of the tape is affixed, the cleaning method including: an affixed object cleaning step of cleaning the affixed object by jetting a cleaning liquid from a cleaning nozzle while moving the cleaning nozzle in a reciprocating manner along a path extending from above one end of an outer peripheral edge of the affixed object to above another end of the outer peripheral edge of the affixed object; and a frame cleaning step of cleaning the frame by jetting the cleaning liquid from the cleaning nozzle to the frame.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 17, 2021
    Assignee: DISCO CORPORATION
    Inventors: Yukito Akutagawa, Toshio Tsuchiya, Kentaro Shiraga
  • Patent number: 11078598
    Abstract: A silicon carbide single crystal is grown by a method comprising: a single crystal growth step of growing a silicon carbide single crystal so as to not close a gap between a side surface of the silicon carbide single crystal growing on a silicon carbide seed crystal, and an inner-side surface of a guide member and a crystal deposited on the inner-side surface of the guide member; a crystal growth termination step of terminating crystal growth by temperature lowering; and a gap enlargement step, performed between the single crystal growth step and the crystal growth termination step, of enlarging the gap by maintaining a difference, Pin?Pout, between partial pressure Pin of Si2C in a source gas in the vicinity of an inlet of the gap and partial pressure Pout of Si2C in a source gas in the vicinity of an outlet of the gap at 0.18 torr or less.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 3, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yohei Fujikawa, Hidetaka Takaba
  • Patent number: 11063123
    Abstract: At an upper surface of a gate electrode, a recess occurs due to etching back of poly-silicon for forming the gate electrode. At an upper surface of an interlayer insulating film, a recess occurs in a portion that opposes in a depth direction, the recess of the upper surface of the gate electrode. A barrier metal includes sequentially stacked first to fourth metal films. The first metal film is a titanium nitride film that covers the surface of the interlayer insulating film and has an opening that exposes the recess of the upper surface of the interlayer insulating film. The second metal film is a titanium film that covers the first metal film and the source electrode, and is in contact with the interlayer insulating film, in the opening of the first metal film. The third and fourth metal films are a titanium nitride film and a titanium film, respectively.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 13, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin'ichi Nakamata, Masanobu Iwaya, Keiji Okumura
  • Patent number: 11047044
    Abstract: A film forming apparatus includes: a substrate holding member for vertically holding target substrates at predetermined intervals in multiple stages; a process vessel for accommodating the substrate holding member; a processing gas introduction member each having gas discharge holes which discharge a processing gas for film formation in a direction parallel to each target substrate and introduce the processing gas into the process vessel; an exhaust mechanism for exhausting the interior of the process vessel; and a plurality of gas flow adjustment members installed to face the target substrates, respectively. Each of the gas flow adjustment members adjusts a gas flow of the processing gas discharged horizontally above each of the target substrates from the gas discharge holes of the processing gas introduction member, to be directed from above the respective target substrate located below the respective gas flow adjustment member toward the surface of the respective target substrate.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 29, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Takezawa, Kuniyasu Sakashita, Shigeru Nakajima
  • Patent number: 11049716
    Abstract: Provided herein are methods of filling gaps using high density plasma chemical vapor deposition (HDP CVD). According to various implementations, carbon-containing films such as amorphous carbon and amorphous carbide films are deposited by HDP CVD into gaps on substrates to fill the gaps. The methods may involve using high hydrogen-content process gasses during HDP CVD deposition to provide bottom-up fill. Also provided are related apparatus.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 29, 2021
    Assignee: Lam Research Corporation
    Inventors: Wei Tang, Jason Daejin Park, Bart J. van Schravendijk, Shu Tsai Wang, Kaihan Abidi Ashtiani
  • Patent number: 11043390
    Abstract: The invention relates to the chemical etching of a semiconductor material, including: deposition at least one mask (PLP) on a first surface zone of a semiconductor material (SC); and chemically etching (S31) a second surface zone of the semiconductor material (SC) that is not covered by the mask (PLP). In particular, the aforementioned mask is produced in a material including polyphosphazene, which material protects the underlying semiconductor especially well.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 22, 2021
    Assignee: Centre National De La Recherche Scientifique
    Inventors: Arnaud Etcheberry, Anne-Marie Goncalves, Jean-Luc Pelouard, Mathieu Fregnaux, Anais Loubat
  • Patent number: 11041243
    Abstract: The invention relates to coating precursor nozzle (15) for subjecting a surface of a substrate (5) to a coating precursor. The nozzle (15) having a nozzle output face (10a), first and second nozzle side edges (31, 32), and first and second nozzle end edges (33, 34). The coating precursor nozzle (15) comprising a precursor supply channel (16), a first discharge channel (17a), a first cross purge gas channel (18a), a second cross purge gas channel (18b), a first edge purge gas channel (19a) and at least one first auxiliary purge gas channel (20). The invention further relates to a nozzle head (1).
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 22, 2021
    Assignee: BENEQ OY
    Inventor: Pekka T. Soininen
  • Patent number: 11043363
    Abstract: A plasma processing method is performed by a plasma processing apparatus that includes a process chamber, a conductive first component that is disposed in the process chamber and at least a surface of which is covered with a conductive silicon material, and a second component that is disposed in the process chamber and is at a ground potential or a floating potential with respect to an electric potential of plasma. The method includes forming an oxide layer on the surface of the first component by converting an oxygen-containing gas into plasm, and treating a surface of the second component by converting a halogen-containing gas into plasm.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 22, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Hirotaka Mikami
  • Patent number: 11031474
    Abstract: A semiconductor device is provided with: a substrate; a first region provided above the substrate; a second region provided away from the first region in a first direction; a third region provided between the first region and the second region, the third region facing an electrode portion; a fourth region provided between the first region and the third region; and a fifth region provided between the second region and the third region. The fourth and fifth regions include carbon (C). Carbon concentrations in the first and second regions are lower than carbon concentrations in the fourth and fifth regions.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshiyuki Kondo
  • Patent number: 11020776
    Abstract: A substrate cleaning method includes a processing liquid supplying step which supplies a processing liquid that contains a solute and a volatile solvent to an upper surface of a substrate, a film forming step in which the solvent is at least partially volatilized from the processing liquid and solidified or hardened to form a particle holding layer on the upper surface of the substrate, and a removal step in which a peeling liquid is supplied to the upper surface of the substrate to peel and remove the particle holding layer. A solute composition in the solute is insoluble in the peeling liquid before being heated to a temperature equal/higher than a quality-changing temperature to become soluble in the peeling liquid. During film forming, the processing liquid is heated to a temperature below the quality-changing temperature, to form the particle holding layer, without changing the quality of the solute composition.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 1, 2021
    Inventor: Yukifumi Yoshida
  • Patent number: 11024737
    Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan
  • Patent number: 11001924
    Abstract: Provided is a processing container formed of a reaction tube and a manifold that supports the reaction tube from below, and adapted to process a substrate inside, a nozzle adapted to supply a processing gas to the substrate, and a connecting portion adapted to erect the nozzle inside the processing container. The connecting portion includes (1) a fixing portion formed of a cylindrical portion inserted into an introduction portion provided at the manifold, and a flange plate formed at an end portion of the cylindrical portion, and (2) a detachable portion formed of an elbow engaged with the flange plate, and an installation portion in which the nozzle is installed.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 11, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Hidenari Yoshida
  • Patent number: 10998857
    Abstract: A resonator including a lower electrode, an upper electrode, and a piezoelectric film that is formed between the lower electrode and the upper electrode. A MEMS device is provided that includes an upper lid that faces the upper electrode, and a lower lid that faces the lower electrode and that seals the resonator together with the upper lid. A CMOS device is mounted on a surface of the upper lid or the lower lid opposite a surface that faces the resonator. The CMOS device includes a CMOS layer and a protective layer that is disposed on a surface of the CMOS layer opposite a surface that faces the resonator. The upper or lower lid to which the CMOS device is joined includes a through-electrode that electrically connects the CMOS device to the resonator.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 4, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keiichi Umeda, Tadayuki Okawa, Taku Kamoto
  • Patent number: 10987653
    Abstract: A composite comprises a carbonaceous and a metallic nanotube conjugated with a carbonaceous support. The composite may be used to remove contaminants from water.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 27, 2021
    Assignee: AUBURN UNIVERSITY
    Inventors: Dongye Zhao, Wen Liu
  • Patent number: 10957800
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10943806
    Abstract: A substrate processing technique includes: a first heating device configured to heat a substrate to a first processing temperature; a first process chamber provided with the first heating device; a second heating device configured to heat the substrate to a second processing temperature utilizing microwaves, the second processing temperature being higher than the first processing temperature; a second process chamber provided with the second heating device; a substrate placement portion configured to load and unload the substrate with respect to the first process chamber and the second process chamber by placing and rotating the substrate; and a controller configured to respectively control the first heating device, the second heating device, and the substrate placement portion.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 9, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kazuyuki Toyoda, Kazuhiro Yuasa, Tetsuo Yamamoto
  • Patent number: 10937664
    Abstract: Methods and systems for surface modification are described. In an embodiment, a method of etching includes providing a substrate having a device structure, portions of which are identified for modification. Such a method may also include passivating target surfaces of the device structure by exposing the device structure to a gas-phase composition at a processing pressure equal to or greater than 100 mTorr to form a protection layer on the target surfaces. Other embodiments of a method may include providing a substrate having a device structure, portions of which identified for removal. Such methods may further include passivating target surfaces of the device structure by exposing the device structure to a gas-phase composition, wherein the ratio of the radical content to the ion content exceeds 10-to-1.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 2, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Cedric Thomas, Andrew Nolan, Alok Ranjan
  • Patent number: 10930527
    Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
  • Patent number: 10930503
    Abstract: Processing methods comprising selectively replacing a first pillar material with a second pillar material in a self-aligned process are described. The first pillar material may be grown orthogonally to the substrate surface and replaced with a second pillar material to leave a substantially similar shape and alignment as the first pillar material.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Ziqing Duan, Abhijit Basu Mallick
  • Patent number: 10916418
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel
  • Patent number: 10889009
    Abstract: The present invention relates to a transfer head gripping and transferring micro LEDs from a first substrate to a second substrate. More particularly, the present invention relates to a transfer head gripping and transferring micro LEDs in a batch manner without any error even when there is a height difference of the micro LEDs.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 12, 2021
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10847392
    Abstract: Described herein is a technique capable of forming a film with uniform characteristics from an upper portion to a lower portion of a deep concave structure whose aspect ratio is high. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) placing a substrate comprising a deep concave structure constituted by at least an upper portion and a lower portion on a substrate support provided in a process chamber; (b) supplying a process gas into the process chamber to form a layer on an inner surface of the deep concave structure; and (c) discharging by-products generated in an inner space of the deep concave structure in (b) by setting a pressure of a process space defined by the process chamber to be lower than a pressure of the inner space of the deep concave structure.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 24, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Tsukasa Kamakura
  • Patent number: 10845638
    Abstract: The application provides a color film substrate, a flexible liquid crystal display panel and a preparation method. The color film substrate includes a flexible substrate, a photoresist layer, an alignment layer and black matrix walls. By disposing the three-dimensional black matrix walls with liquid crystal-holding chambers on the color film substrate, liquid crystals can be fixed in the holding chambers for avoiding the uneven cell gap caused by the displacement of the liquid crystals. Thus, the application solves the problem that an existing flexible liquid crystal display panel has severe displacement of the liquid crystals under stress.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 24, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jianlong Huang, Wei Tang
  • Patent number: 10840115
    Abstract: The present invention relates to a micro LED transfer head improving efficiency of transferring micro LEDs.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 17, 2020
    Assignee: POINT ENGINEERING CO., LTD
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10829866
    Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mihir Tungare, Peter Kim, Jianwei Wan, Chankyung Choi
  • Patent number: 10816901
    Abstract: A coater with automatic cleaning function and a coater automatic cleaning method. The coater (100,200,300,400,500,600,700,800) includes a coater chamber (101,201,301,401,501,601,701,801) capable of being filled up with cleaning solution, a substrate chuck (102,202,302,402,502,602,702,802) holding and positioning a substrate (103,203,303,403,503,603,703,803), and at least one shroud (108,208,308,408,508) capable of moving up for preventing photoresist from splashing out of the coater chamber (101,201,301,401,501,601,701,801), or moving down and immersing into the cleaning solution for cleaning.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 27, 2020
    Assignee: ACM Research (Shanghai) Inc.
    Inventors: Hui Wang, Fuping Chen, Wenjun Wang, Hongchao Yang, Voha Nuch, Fufa Chen, Jian Wang, Xiaoyan Zhang, Shu Yang
  • Patent number: 10808318
    Abstract: There is provided a technique that includes: a process chamber accommodating a substrate support supporting substrates in multiple stages to process the substrates; a supply buffer part adjacent the process chamber; a first gas supply part installed in the supply buffer part; a second gas supply part installed in the supply buffer part; an inner wall installed between the supply buffer part and the process chamber, on which a plurality of slits are formed to correspond to the substrates; and a maintenance port disposed at a lower end of the inner wall, wherein the first gas supply part includes a first gas nozzle having a supply hole that supplies first gas into the supply buffer part.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 20, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takeo Hanashima, Tsukasa Kamakura, Takafumi Sasaki, Hidenari Yoshida