Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 11905163
    Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided by the embodiments of the present disclosure. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; and a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, and the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, and an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 20, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaochen Ma, Guangcai Yuan, Ce Ning, Xin Gu, Xiao Zhang, Chao Li
  • Patent number: 11908682
    Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) forming a first oxide layer by modifying a surface of a substrate at a first temperature with a plasma of a first oxygen-containing gas; and (b) forming a second oxide layer thicker than the first oxide layer by heating the substrate to a second temperature higher than the first temperature and modifying the surface of the substrate, on which the first oxide layer is formed, with a plasma of a second oxygen-containing gas.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 20, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Hiroto Igawa, Masanori Nakayama, Katsunori Funaki, Tatsushi Ueda, Yasutoshi Tsubota, Eiko Takami, Yuichiro Takeshima, Yuki Yamakado
  • Patent number: 11901437
    Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
    Type: Grant
    Filed: May 15, 2022
    Date of Patent: February 13, 2024
    Assignee: Marlin Semiconductor Limited
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 11903302
    Abstract: Systems and methods for depositing materials on a substrate via OVJP are provided. A float table and grippers are used to move and position the substrate relative to one or more OVJP print bars to reduce the chance of damaging or compromising the substrate or prior depositions.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: February 13, 2024
    Assignee: Universal Display Corporation
    Inventors: Kent Khuong Nguyen, Sriram Krishnaswami, Daniel Toet, Jeff Hawthorne, William E. Quinn
  • Patent number: 11884689
    Abstract: A method and composition for producing a porous low k dielectric film via chemical vapor deposition is provided. In one aspect, the method comprises the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising a alkoxysilacyclic or acyloxysilacyclic compound with or without a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 3.2 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 30, 2024
    Inventors: Robert Gordon Ridgeway, Raymond Nicholas Vrtis, Xinjian Lei, Jennifer Lynn Anne Achtyl, William Robert Entley
  • Patent number: 11865636
    Abstract: The present disclosure relates to a system for laser processing of a ceramic electrolyte material. The system may include a controller, a laser responsive to the controller for generating a beam, and a beam forming subsystem. The beam forming subsystem controls a parameter of the beam generated by the laser. The beam forming subsystem further controls the beam to provide a laser fluence sufficient to produce densification of the ceramic electrolyte material.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 9, 2024
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Jianchao Ye, John Roehling, Jae Hyuck Yoo
  • Patent number: 11856682
    Abstract: The present invention relates to a method for measuring the ion nonextensive parameter of plasma includes the following steps: describe the plasma with nonextensive statistical mechanics, obtain the equation describing the relationship between the geodesic acoustic mode frequency and the ion acoustic speed of plasma; collect the measurement data of the geodesic acoustic mode frequencies and plasma temperature in the device where the plasma is to be measured; the obtained equation describing the relationship between the geodesic acoustic mode frequency and the ion acoustic speed of plasma is used to linearly fit the collected measured data of the geodesic acoustic mode frequency and the plasma temperature in the device where the plasma is to be measured to obtain the slope value; based on the derived equation and the obtained slope values, and combining with the safety factor of the device where the plasma is to be measured, the ion nonextensive parameter is solved numerically.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: December 26, 2023
    Assignee: NANCHANG UNIVERSITY
    Inventors: Huibin Qiu, Zuozhi Hu, Donghua Xiao, Shengfa Wu, Chengjie Zhong, Jiangcun Chen, Chaozhe Hu, Xiaobin Li, Junjie Wu, Junhui Liu, Yizhen Bao, Xiaoyang Zhang, Runrui Dai, Lihuan Liu, Jianing Xu, Xu Tu, Juecong Zhang, Peng Guo, Shuyu Long, Huang Weng, Chenyu Tong, Sanqiu Liu
  • Patent number: 11842885
    Abstract: A plasma processing apparatus or a plasma processing method that processes a wafer to be processed, which is placed on a surface of a sample stage arranged in a processing chamber inside a vacuum container, using a plasma formed in the processing chamber, the apparatus or method including processing the wafer by adjusting a first high-frequency power to be supplied to a first electrode arranged inside the sample stage and a second high-frequency power to be supplied, via a resonant circuit, to a second electrode which is arranged in an inner side of a ring-shaped member made of a dielectric arranged on an outer peripheral side of a surface of the sample stage on which the wafer is placed, during the processing.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: December 12, 2023
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Tooru Aramaki, Kenetsu Yokogawa, Masaru Izawa
  • Patent number: 11837681
    Abstract: An avalanche photodiode with a diffused junction and the method for its fabrication are disclosed. The method comprising forming, on a substrate, a first high-doped region and a low-doped region; performing selective area growth (SAG) with in-situ etchant on the low-doped region to grow a SAG structure; and diffusing through the SAG structure to form a second high-doped region in the low-doped region.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 5, 2023
    Assignee: NATIONAL RESEARCH COUNCIL OF CANADA
    Inventors: Oliver Pitts, Omid Salehzadeh Einabad
  • Patent number: 11837648
    Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 11835861
    Abstract: A resist material dispensing system includes a resist supply and a resist filter connected to the resist supply downstream from the resist supply. The resist material dispensing system includes a resist tank structure connected to the resist filter downstream from the resist filter and a resist pump device connected to the resist tank structure downstream from the resist tank structure. The resist tank structure is vertically arranged so that a resist material flows in a continuous downward flow from where the resist material enters the resist tank structure until the resist material exits the resist tank structure.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen Yi Hsu, Shang-Sheng Li, Yung-Yao Lee
  • Patent number: 11827980
    Abstract: Aspects of the present disclosure relate generally to isolator devices, components thereof, and methods associated therewith for substrate processing chambers. In one implementation, a substrate processing chamber includes an isolator ring disposed between a pedestal and a pumping liner. The isolator ring includes a first surface that faces the pedestal, the first surface being disposed at a gap from an outer circumferential surface of the pedestal. The isolator ring also includes a second surface that faces the pumping liner and a protrusion that protrudes from the first surface of the isolator ring and towards the outer circumferential surface of the pedestal. The protrusion defines a necked portion of the gap between the pedestal and the isolator ring.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: November 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Nitin Pathak, Amit Kumar Bansal, Tuan Anh Nguyen, Thomas Rubio, Badri N. Ramamurthi, Juan Carlos Rocha-Alvarez
  • Patent number: 11830824
    Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
  • Patent number: 11827976
    Abstract: A method includes arranging a substrate in a processing chamber, and exposing the substrate to a gas mixture including a first metal precursor gas and a second metal precursor gas to deposit a first metal precursor and a second metal precursor onto the substrate at the same time. The method further includes purging the processing chamber, supplying a reactant common to both the first metal precursor and the second metal precursor to form a layer of an alloy on the substrate, and purging the processing chamber.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 28, 2023
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ilanit Fisher, Raashina Humayun, Michal Danek, Patrick Van Cleemput, Shruti Thombare
  • Patent number: 11827562
    Abstract: The present disclosure relates to glass articles, a method of making the glass articles, and uses of the glass articles. The glass article has a UV-transmittance of more than 90% at 350 nm and at 500 nm and a total amount of Si2, B2O3 and Al2O3 of at least 75 mol %. The article is preferably used in the fields of biotechnology, MEMS, CIS, MEMS-like pressure sensor, display, micro array, electronic devices, microfluidics, semiconductor, high precision equipment, camera imaging, display technologies, sensor/semicon, electronic devices, home appliance, diagnostic product, and/or medical device.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: November 28, 2023
    Assignee: SCHOTT GLASS TECHNOLOGIES (SUZHOU) CO. LTD
    Inventors: Huiyan Fan, Junming Xue, Pengxiang Qian, Matthias Jotz, Fredrik Prince
  • Patent number: 11832533
    Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 28, 2023
    Assignee: Lam Research Corporation
    Inventors: James Samuel Sims, Andrew John McKerrow, Meihua Shen, Thorsten Lill, Shane Tang, Kathryn Merced Kelchner, John Hoang, Alexander Dulkin, Danna Qian, Vikrant Rai
  • Patent number: 11825589
    Abstract: A plasma processing apparatus includes a cooling plate having a fixing surface to which an upper electrode is fixed, the cooling plate having, on the fixing surface, an electrostatic chuck configured to attract the upper electrode by an attraction force generated by an applied voltage; a power supply configured to apply the voltage to the electrostatic chuck; and a power supply controller configured to control the power supply such that an absolute value of the voltage applied to the electrostatic chuck is increased based on a degree of consumption of the upper electrode.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 21, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yohei Uchida, Tetsuji Sato, Shojiro Yahata, Taira Takase
  • Patent number: 11810764
    Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a plurality of recesses extending about and radially outward of the plurality of apertures.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 7, 2023
    Inventors: Fang Ruan, Prashant Kumar Kulshreshtha, Rajaram Narayanan, Diwakar Kedlaya
  • Patent number: 11802342
    Abstract: The present disclosure provides a new wet atomic layer etch (ALE) process for etching ruthenium. More specifically, the present disclosure provides various embodiments of methods that utilize new etch chemistries for etching ruthenium in a wet ALE process. Unlike conventional etch processes for ruthenium, the wet ALE process described herein for etching ruthenium is metal-free, cost-effective and improves surface roughness during etching.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: October 31, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Paul Abel
  • Patent number: 11795543
    Abstract: According to one embodiment, a silicon-containing product forming apparatus includes a reaction chamber, an emission path, a process liquid tank, a supplier, and a flow path switcher. The emission path emits an emission material from the reaction chamber. The supplier includes a supply line configured to supply a process liquid to the emission path from the process liquid tank, and a byproduct generated by reaction is treated in the emission path by the supplied process liquid. The flow path switcher switches the communication state of the emission path with each of the reaction chamber and the supply line of the supplier.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: October 24, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, Kioxia Corporation
    Inventors: Kenya Uchida, Hiroyuki Fukui, Ikuo Uematsu
  • Patent number: 11795545
    Abstract: Susceptor assemblies, reactors and systems including the assemblies, and methods of using the assemblies, reactors, and systems are disclosed. Exemplary susceptor assemblies include two or more sections that can be moved relative to each other to allow rapid changes in a substrate temperature. The movement of the two or more sections can additionally or alternatively be used to manipulate conductance of gas flow through a reactor.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: October 24, 2023
    Assignee: ASM IP Holding B.V.
    Inventor: John Kevin Shugrue
  • Patent number: 11791180
    Abstract: A substrate transfer system includes an atmospheric substrate transfer module, a vacuum substrate transfer module, and a load lock module disposed on a side surface of the atmospheric substrate transfer module and disposed on an upper surface or a lower surface of the vacuum substrate transfer module. The load lock module includes a container having a first substrate transfer opening and a second substrate transfer opening, a first gate configured to open or close the first substrate transfer opening, a second gate configured to open or close the second substrate transfer opening, and a substrate actuator configured to vertically move a substrate through the second substrate transfer opening between a first position in the container and a second position in the vacuum substrate transfer module.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: October 17, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Norihiko Amikura, Masahiro Dogome, Masatomo Kita
  • Patent number: 11776807
    Abstract: Methods for controlling the formation of oxygen containing thin films, such as silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN) thin films, on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor that comprises oxygen and a second reactant that does not include oxygen. In some embodiments the plasma power can be selected from a range to achieve a desired step coverage or wet etch rate ratio (WERR) for films deposited on three dimensional features.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: October 3, 2023
    Assignee: ASM IP Holding, B.V.
    Inventors: Lingyun Jia, Viljami J. Pore, Marko Tuominen, Sun Ja Kim, Oreste Madia
  • Patent number: 11769816
    Abstract: Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 ?. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Manzar Siddik
  • Patent number: 11760695
    Abstract: A method of depositing silicon carbide on a preform to form a ceramic matrix composite comprises placing the preform into a reaction vessel, removing air from the reaction vessel and backfilling the reaction vessel with an inert gas to an operating pressure. The reaction vessel and the preform are heated to an operating temperature. A carrier gas and precursor materials are heated to a preheat temperature outside of the reaction vessel. The carrier gas and the precursor materials are introduced to the reaction vessel in a specified ratio. Off gasses, the precursor materials that are unspent, and the carrier gas are removed from the reaction vessel to maintain the specified ratio of the precursor materials in the reaction vessel.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: September 19, 2023
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Weiming Lu, Jun Nable
  • Patent number: 11756828
    Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 12, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Keith Tatseun Wong, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 11743973
    Abstract: Provided is a placing table configured to place a workpiece thereon. The placing table includes: an electrostatic chuck configured to attract the workpiece; a support member configured to support a focus ring; and a metal base having a first region configured to support the electrostatic chuck and a second region configured to support the support member, the second region surrounding the first region. The support member includes: an intermediate layer formed of a ceramic sintered compact and supported on the second region via an adhesive; a thermally sprayed ceramic layer formed on the intermediate layer by a thermal spraying method; and a heater electrode provided within the thermally sprayed ceramic layer. The heater electrode is formed by the thermal spraying method.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 29, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Dai Kitagawa
  • Patent number: 11742181
    Abstract: A control method of a plasma processing apparatus including a first electrode that places a workpiece thereon includes supplying a bias power to the first electrode, and supplying a source power having a frequency higher than that of the bias power into a plasma processing space. The source power has a first state and a second state. The control method further includes a first control process of alternately applying the first state and the second state of the source power in synchronization with a signal synchronized with a cycle of a radio frequency of the bias power, or a phase within one cycle of a reference electrical state that represents any one of a voltage, current, and electromagnetic field measured in a power feeding system of the bias power.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: August 29, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Chishio Koshimizu, Taichi Hirano, Toru Hayasaka, Shinji Kubota, Koji Maruyama, Takashi Dokan
  • Patent number: 11742182
    Abstract: A control method of a plasma processing apparatus including a first electrode that places a workpiece thereon includes supplying a bias power to the first electrode, and supplying a source power having a frequency higher than that of the bias power into a plasma processing space. The source power has a first state and a second state. The control method further includes a first control process of alternately applying the first state and the second state of the source power in synchronization with a signal synchronized with a cycle of a radio frequency of the bias power, or a phase within one cycle of a reference electrical state that represents any one of a voltage, current, and electromagnetic field measured in a power feeding system of the bias power.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: August 29, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Chishio Koshimizu, Taichi Hirano, Toru Hayasaka, Shinji Kubota, Koji Maruyama, Takashi Dokan
  • Patent number: 11728555
    Abstract: Disclosed herein is an apparatus that includes a memory, a processor, and a rectangular waveguide coupled to the memory and the processor so that the memory and the processor communicate with each other via the rectangular waveguide.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Yoshihito Koya
  • Patent number: 11728202
    Abstract: The present disclosure relates to an element pickup device, a method for manufacturing the same and a method for using the same. The element pickup device includes: a first substrate and a second substrate oppositely disposed; a spacing part located between the first substrate and the second substrate, wherein the spacing part is spaced apart from each other to define a flow channel for liquid; and an element pickup part including an opening located in the second substrate and in communication with the flow channel.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: August 15, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingwei Liu, Zhanfeng Cao, Muxin Di, Ke Wang, Zhiwei Liang, Renquan Gu
  • Patent number: 11728136
    Abstract: A system and method for generating a radio frequency (RF) waveform are described. The method includes defining a train of on-off pulses separated by an off state having no on-off pulses. The method further includes applying a multi-level pulse waveform that adjusts a magnitude of each of the on-off pulses to generate an RF waveform. The method includes sending the RF waveform to an electrode.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: August 15, 2023
    Assignee: Lam Research Corporation
    Inventors: Maolin Long, Yuhou Wang, Ying Wu, Alex Paterson
  • Patent number: 11728453
    Abstract: A stacked monolithic multijunction solar cell, which includes a first subcell having a p-n junction with an emitter layer and a base layer, the thickness of the emitter layer being less than the thickness of the base layer at least by a factor of ten, and the first subcell comprising a substrate having a semiconductor material from the groups III and V or a substrate from the group IV, and which further includes a second subcell arranged on the first subcell and a third subcell arranged on the second subcell, the two subcells each including an emitter layer and a base layer, and a tunnel diode and a back side field layer each being formed between the subcells, the thickness of the emitter layer being greater than the thickness of the base layer in each case between the second subcell and in the third subcell.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: August 15, 2023
    Assignee: AZUR SPACE Solar Power GmbH
    Inventors: Daniel Fuhrmann, Rosalinda Van Leest, Gregor Keller, Matthias Meusel
  • Patent number: 11721545
    Abstract: Embodiments of the present disclosure generally relate to methods of depositing carbon film layers greater than 3,000 ? in thickness over a substrate and surface of a lid of a chamber using dual frequency, top, sidewall and bottom sources. The method includes introducing a gas to a processing volume of a chamber. A first radiofrequency (RF) power is provided having a first frequency of about 40 MHz or greater to a lid of the chamber. A second RF power is provided having a second frequency to a bias electrode disposed in a substrate support within the processing volume. The second frequency is about 10 MHz to about 40 MHz. An additional third RF power is provided having lower frequency of about 400 kHz to about 2 MHz to the bias electrode.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Anup Kumar Singh, Rick Kustra, Vinayak Vishwanath Hassan, Bhaskar Kumar, Krishna Nittala, Pramit Manna, Kaushik Comandoor Alayavalli, Ganesh Balasubramanian
  • Patent number: 11708636
    Abstract: Embodiments of the present disclosure provide a reaction gas supply system and a control method. The reaction gas supply system includes a plurality of precursor containers and a plurality of supply regulator devices. The precursor container is connected to at least one of the reaction chambers. The plurality of precursor containers include at least a pair of precursor containers of an arbitrary combination. A supply regulator device is arranged between each pair of precursor containers. The supply regulator device is configured to connect the corresponding pair of precursor containers. With the reaction gas supply system and the control method of the present disclosure, the reaction gas may be ensured to be supplied stably, the utilization rate of the precursor may be increased, and the production efficiency and the product quality may be increased.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 25, 2023
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Chun Wang, Bo Zheng, Zhenguo Ma, Jing Wang, Xin Wu, Xiaojuan Wang, Jing Shi
  • Patent number: 11694892
    Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: July 4, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Gido van Der Star, Toshiya Suzuki
  • Patent number: 11692283
    Abstract: An apparatus for growing semiconductor wafers, in particular of silicon carbide, wherein a chamber houses a collection container and a support or susceptor arranged over the container. The support is formed by a frame surrounding an opening accommodating a plurality of arms and a seat. The frame has a first a second surface, opposite to each other, with the first surface of the frame facing the support. The arms are formed by cantilever bars extending from the frame into the opening, having a maximum height smaller than the frame, and having at the top a resting edge. The resting edges of the arms define a resting surface that is at a lower level than the second surface of the frame. The seat has a bottom formed by the resting surface.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 4, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Ruggero Anzalone, Nicolo′ Frazzetto, Francesco La Via
  • Patent number: 11682544
    Abstract: Semiconductor processing systems according to embodiments of the present technology may include a chamber body having sidewalls and a base. The chamber body may define an internal volume. The systems may include a substrate support assembly having a shaft and a platen coupled with the shaft along a first surface of the platen. The semiconductor processing systems may include a cover plate positioned on the platen of the substrate support assembly along a second surface of the platen opposite the first surface. The cover plate may include a flange extending about an exterior region of the cover plate. The flange may be in direct contact with the platen. The cover plate may include an upper wall vertically offset from the flange. An interior volume may be defined between the upper wall and the platen of the substrate support assembly.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 20, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Venkata Sharat Chandra Parimi, Satish Radhakrishnan, Diwakar Kedlaya, Fang Ruan, Amit Bansal
  • Patent number: 11670503
    Abstract: Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: June 6, 2023
    Assignee: Lam Research Corporation
    Inventors: Jun Qian, Hu Kang, Adrien LaVoie, Seiji Matsuyama, Purushottam Kumar
  • Patent number: 11654409
    Abstract: A method of synthesizing aerogels and cross-linked aerogels are described that incorporate freeze-drying in lieu of super-critical solvent drying. Advantages over supercritical drying include a reduction in hazard risks posed by drying at supercritical conditions as well as the ability to up-scale the process to accommodate large pieces of material without introducing risk. In addition, inexpensive and more sophisticated mold technologies, which are not impervious to super-critical conditions, can be used to produce aerogel materials according to the freeze-drying method of the invention. This introduces a level of freedom never before available for the production of aerogel components.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 23, 2023
    Assignee: Virginia Commonwealth University
    Inventors: Massimo Bertino, Lauren White, Dalton Echard, Tyler Selden
  • Patent number: 11651952
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel
  • Patent number: 11651941
    Abstract: The present inventive concept relates to a gas distribution apparatus of a substrate processing apparatus including: a first gas distribution module distributing a processing gas to a first gas distribution space; and a second gas distribution module distributing a processing gas to a second gas distribution space which differs from the first gas distribution space, a substrate processing apparatus, and a substrate processing method.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 16, 2023
    Inventors: Min Ho Cheon, Jong Sik Kim, Chul-Joo Hwang
  • Patent number: 11621184
    Abstract: A laser marking device includes a laser emission unit configured to emit a laser beam to a first surface of an object to be processed, and a pressing unit configured to press a second surface that is opposite to the first surface of the object to be processed to make the first surface of the object to be flat. The pressing unit includes a first pressing portion configured to press an edge area of the second surface in a contact manner, and at least one second pressing portion configured to press a middle area of the second surface in a non-contact manner to maintain a separation distance from the second surface within a certain distance.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 4, 2023
    Assignee: EO TECHNICS CO., LTD.
    Inventors: Sung Beom Jung, Jea Ho Moon, Soo Young Kim, Doo Seok Lee
  • Patent number: 11613065
    Abstract: An imprint method provided herein includes the steps of: adding a soluble material to a master mold; solidifying the soluble material to form a soluble mold having a mold pattern; adhering a dissociable tape to the soluble mold to separate the soluble mold from the master mold; placing the soluble mold onto a polymer layer of a workpiece for imprint; applying a high temperature and a pressure to the soluble mold to allow the polymer layer having an imprint pattern corresponding to the mold pattern and solidification, and to dissociate the tape; and providing a solvent to dissolve the soluble mold to obtain an imprint workpiece having the imprint pattern.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: March 28, 2023
    Assignee: EVER RADIANT INCORPORATION
    Inventor: Sung-Wen Tsai
  • Patent number: 11615988
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 28, 2023
    Assignee: Tessera, LLC
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 11600508
    Abstract: Herein disclosed are a micro-component transfer head, a micro-component transfer device, and a micro-component display. Said micro-component transfer head comprises a carrying surface that corresponds to a micro-component extraction area. Said extraction area conforms with a first geometric object, which comprises at least an acute angle. A second geometric object comprises at least a right angle and is constituted of n copies of the first geometric object, n being an integer greater than 1. The shape of the first geometric object differs from that of the second.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 7, 2023
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yu-Chu Li, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen
  • Patent number: 11587773
    Abstract: A substrate pedestal includes a thermally conductive substrate support including a mesh, a thermally conductive shaft including a plurality of conductive rods therein, each conductive rod having a first end and a second end, and a sensor. The first end of each conductive rod is electrically coupled to the mesh, and the sensor is disposed between the first and second ends of each conductive rod and configured to detect current flow through each conductive rod.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 21, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Viren Kalsekar, Vinay K. Prabhakar, Venkata Sharat Chandra Parimi
  • Patent number: 11581438
    Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: February 14, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
  • Patent number: 11581170
    Abstract: A plasma processing apparatus includes: a first electrode on which a substrate is placed; a plasma generation source that generates plasma; a bias power supply that supplies bias power to the first electrode; a source power supply that supplies source power to the plasma generation source; and a controller. The controller performs a control such that a first state and a second state of the source power are alternately applied in synchronization with a high frequency cycle of the bias power, or a phase within one cycle of a reference electrical state indicating any one of a voltage, a current and an electromagnetic field measured in a power feed system of the bias power, and performs a control to turn OFF the source power at least at a negative side peak of the phase within one cycle of the reference electrical state.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 14, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shinji Kubota, Yuji Aota, Chishio Koshimizu
  • Patent number: 11530483
    Abstract: Provided is a substrate processing system for improving productivity of processes. In this regard, the substrate processing system includes: a first chamber providing a space where at least one substrate is accommodated; a second chamber configured to transfer at least one substrate to the first chamber; and a temperature control unit configured to change a temperature of a gas in the second chamber.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 20, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: YoonKi Min, YoungHoon Kim, HakJoo Lee, SeungJu Chun