Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 10847392
    Abstract: Described herein is a technique capable of forming a film with uniform characteristics from an upper portion to a lower portion of a deep concave structure whose aspect ratio is high. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) placing a substrate comprising a deep concave structure constituted by at least an upper portion and a lower portion on a substrate support provided in a process chamber; (b) supplying a process gas into the process chamber to form a layer on an inner surface of the deep concave structure; and (c) discharging by-products generated in an inner space of the deep concave structure in (b) by setting a pressure of a process space defined by the process chamber to be lower than a pressure of the inner space of the deep concave structure.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: November 24, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventor: Tsukasa Kamakura
  • Patent number: 10845638
    Abstract: The application provides a color film substrate, a flexible liquid crystal display panel and a preparation method. The color film substrate includes a flexible substrate, a photoresist layer, an alignment layer and black matrix walls. By disposing the three-dimensional black matrix walls with liquid crystal-holding chambers on the color film substrate, liquid crystals can be fixed in the holding chambers for avoiding the uneven cell gap caused by the displacement of the liquid crystals. Thus, the application solves the problem that an existing flexible liquid crystal display panel has severe displacement of the liquid crystals under stress.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: November 24, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jianlong Huang, Wei Tang
  • Patent number: 10840115
    Abstract: The present invention relates to a micro LED transfer head improving efficiency of transferring micro LEDs.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 17, 2020
    Assignee: POINT ENGINEERING CO., LTD
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10829866
    Abstract: In an embodiment, a wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket being defined by a base and a substantially circular perimeter including an inner face and an outer face. The substantially circular perimeter includes a notch in the inner face.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mihir Tungare, Peter Kim, Jianwei Wan, Chankyung Choi
  • Patent number: 10816901
    Abstract: A coater with automatic cleaning function and a coater automatic cleaning method. The coater (100,200,300,400,500,600,700,800) includes a coater chamber (101,201,301,401,501,601,701,801) capable of being filled up with cleaning solution, a substrate chuck (102,202,302,402,502,602,702,802) holding and positioning a substrate (103,203,303,403,503,603,703,803), and at least one shroud (108,208,308,408,508) capable of moving up for preventing photoresist from splashing out of the coater chamber (101,201,301,401,501,601,701,801), or moving down and immersing into the cleaning solution for cleaning.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 27, 2020
    Assignee: ACM Research (Shanghai) Inc.
    Inventors: Hui Wang, Fuping Chen, Wenjun Wang, Hongchao Yang, Voha Nuch, Fufa Chen, Jian Wang, Xiaoyan Zhang, Shu Yang
  • Patent number: 10808318
    Abstract: There is provided a technique that includes: a process chamber accommodating a substrate support supporting substrates in multiple stages to process the substrates; a supply buffer part adjacent the process chamber; a first gas supply part installed in the supply buffer part; a second gas supply part installed in the supply buffer part; an inner wall installed between the supply buffer part and the process chamber, on which a plurality of slits are formed to correspond to the substrates; and a maintenance port disposed at a lower end of the inner wall, wherein the first gas supply part includes a first gas nozzle having a supply hole that supplies first gas into the supply buffer part.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 20, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takeo Hanashima, Tsukasa Kamakura, Takafumi Sasaki, Hidenari Yoshida
  • Patent number: 10796900
    Abstract: Described herein is a technique capable of improving electrical characteristics of a semiconductor device. According to the technique, there is provided a method of manufacturing a semiconductor device including: (a) generating oxygen and hydrogen active species; and (b) forming an oxide layer by supplying the oxygen and hydrogen active species to a substrate with a concave structure to subject a film on an inner surface of the concave structure to oxidation, wherein the oxide layer is formed in (b) such that a thickness of the oxide layer is greater on the inner surface than at an upper end portion of the concave structure by setting a ratio of a flow rate of the hydrogen active species to a total flow rate to a predetermined ratio greater than a first ratio at which a rate of forming the oxide layer is maximized at the upper end portion of the concave structure.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yuichiro Takeshima, Masanori Nakayama, Katsunori Funaki, Yasutoshi Tsubota, Hiroto Igawa
  • Patent number: 10796910
    Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Ko, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10790409
    Abstract: A nitride semiconductor light-emitting element includes at least an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer. A multilayer body is provided between the n-type nitride semiconductor layer and the light-emitting layer, having at least one stack of first and second semiconductor layers. The second semiconductor layer has a greater band-gap energy than the first semiconductor layer. The first and second semiconductor layers each have a thickness of more than 10 nm and 30 nm or less. In applications in which luminous efficiency at room temperature is a high priority, the first semiconductor layer has a thickness of more than 10 nm and 30 nm or less, the second semiconductor layer has a thickness of more than 10 nm and 40 nm or less, and the light-emitting layer has V-shaped recesses in cross-sectional view.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiko Tani, Tetsuya Hanamoto, Masanori Watanabe, Akihiro Kurisu, Katsuji Iguchi, Hiroyuki Kashihara, Tomoya Inoue, Toshiaki Asai, Hirotaka Watanabe
  • Patent number: 10777408
    Abstract: A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a flexible substrate and a buffer stack overlying the substrate. The buffer stack comprises at least one epitaxial buffer layer. An epitaxial doped layer comprised predominantly of silicon overlies the at least one epitaxial buffer layer. Mobility of the device is greater than 100 cm2/Vs and carrier concentration of the epitaxial doped layer is less than 1016 cm?3.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: September 15, 2020
    Assignee: University of Houston System
    Inventors: Venkat Selvamanickam, Pavel Dutta, Ying Gao
  • Patent number: 10738381
    Abstract: Disclosed are a substrate holder and a semiconductor manufacturing apparatus including the substrate holder. The substrate holder provides a reaction region by making face-sealing contact with a reactor wall. The substrate holder has an elastic behavior when pressure is applied thereto while the substrate holder makes face-sealing contact with the reactor wall. The semiconductor manufacturing apparatus includes the substrate holder and a gas supply unit configured to supply gas to the reaction region provided by the reactor wall and the substrate holder.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 11, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Hyun Soo Jang, Jeong Ho Lee, Woo Chan Kim, Sung Hoon Jun, Jong Won Shon
  • Patent number: 10741426
    Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
  • Patent number: 10720324
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a film on a substrate by causing a first precursor and a second precursor to intermittently react with each other by repeating a cycle a plurality of times, the cycle alternately performing supplying the first precursor, which satisfies an octet rule and has a first pyrolysis temperature, to the substrate and supplying the second precursor, which does not satisfy the octet rule and has a second pyrolysis temperature lower than the first pyrolysis temperature, to the substrate. In the act of forming the film, a supply amount of the first precursor is set larger than a supply amount of the second precursor.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 21, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kimihiko Nakatani, Hiroshi Ashihara, Hajime Karasawa, Kazuhiro Harada
  • Patent number: 10711372
    Abstract: A silicon carbide epitaxial wafer manufacturing method includes: a stabilization step of nitriding, oxidizing or oxynitriding and stabilizing silicon carbide attached to an inner wall surface of a growth furnace; after the stabilization step, a bringing step of bringing a substrate in the growth furnace; and after the bringing step, a growth step of epitaxially growing a silicon carbide epitaxial layer on the substrate by supplying a process gas into the growth furnace to manufacture a silicon carbide epitaxial wafer.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 14, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihito Ohno, Kenichi Hamano, Takashi Kanazawa
  • Patent number: 10699923
    Abstract: The present invention includes a transfer system for flipping and checking electronic devices. A first rotary device has a plurality of transfer heads configured to pick electronic devices from a wafer table and place the electronic devices on a transfer head of a second rotary device. Check stations can be positioned around the first and second rotary devices and configured to inspect or check the electronic devices during the flipping process. The transfer system can further include an imaging device to inspect the accuracy of picking and placing of the electronic devices during the flipping process. The wafer table and the first rotary device are inclined to increase the operation space. The system accurately picks, flips and transfers chips at a high operation speed.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 30, 2020
    Assignee: MIT SEMICONDUCTOR PTE LTD
    Inventors: Siong Huat Neo, Kim Mone Kwong, Kok Yeow Lim, Zhi Qiang Mao
  • Patent number: 10685814
    Abstract: A system for processing substrates having an atmospheric front end and a vacuum main frame, primary processing chambers attached to the main frame, a loadlock positioned between the front end and the main frame, and at least one secondary processing chamber attached to the loadlock.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 16, 2020
    Assignee: ADVANCED MICRO-FABRICATION EQUIPMENT INC. CHINA
    Inventors: Heng Tao, Tuqiang Ni, Qian Wang
  • Patent number: 10658204
    Abstract: A substrate processing system to treat a substrate includes a spin chuck configured to hold and rotate a substrate. A heating assembly is configured to heat an opposite surface of the substrate and includes a main heater assembly and a nozzle stack cap. The main heater assembly includes a first plurality of light emitting diodes (LEDs) arranged on a first printed circuit board (PCB) in a first plane that is spaced from and parallel to a second plane including the substrate. The nozzle stack cap assembly includes at least one nozzle to dispense liquid onto a center of a first surface of the substrate. A radiant heat source is arranged closer to the substrate than the first plane and is configured to heat the center of the first surface of the substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 19, 2020
    Assignee: LAM RESEARCH AG
    Inventors: Bridget Hill, Michael Puggl, Gerhard Mueller, Henry Roger Osner, Karl-Heinz Hohenwarter, Ulrich Tschinderle, Daniel Brien
  • Patent number: 10640871
    Abstract: A heat treatment system includes a heating unit that heats an inside of a processing chamber in which a plurality of workpieces are accommodated; a heat treatment condition storing unit that stores a heat treatment condition; a heat treatment change model storing unit that stores a heat treatment change model; a heat treatment performing unit that performs the heat treatment condition; a heat treatment result receiving unit that receives a result of heat treatment performed; and an optimum temperature calculating unit that calculate a target heat treatment result for an in-plane shape of the workpiece based on a target heat treatment result and information about a shape of the target heat treatment result, and calculate an optimum temperature that results in the target heat treatment result, based on the calculated target heat treatment result and the heat treatment change model.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 5, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuichi Takenaga, Hiroichi Ota, Shingo Sekisawa
  • Patent number: 10636788
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
  • Patent number: 10600644
    Abstract: Processes for fabricating multi- and monolayer silicene on catalyst metal surfaces by means of plasma-enhanced chemical vapor deposition (PECVD). Silicene is grown by means of PECVD from a starting mixture of H2 and SiH4 having an H2:SiH4 ratio of 100 to 400 on an Ag(111) substrate having a substrate temperature between 20° C. and 290° C., with the deposition being performed for about 10-25 minutes at an RF power between 10 W and 500 W and under a chamber pressure between about 100 mTorr and 1300 mTorr. In most cases, the substrate will be in the form of an Ag(111) film sputtered on a fused silica substrate. A multi-layer silicene film can be formed by extending the deposition time past 25 minutes.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 24, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Xiao Liu, Battogtokh Jugdersuren
  • Patent number: 10593842
    Abstract: Provided are display device and method for fabricating the same. According to an aspect of the present disclosure, there is provided a display device comprising: a first substrate; at least one wavelength conversion layer disposed on the first substrate; a capping layer disposed on the wavelength conversion layer and comprising a porous layer; and a first polarizing layer disposed on the capping layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 17, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Gu Kim, Taek Joon Lee, Hye Lim Jang, Baek Kyun Jeon, Jin Soo Jung
  • Patent number: 10529543
    Abstract: The present disclosure describes an exemplary etch process in a reactor that includes a shower head and an electrostatic chuck configured to receive a radio frequency (RF) power. The shower head includes a top plate and a bottom plate with one or more gas channels that receive incoming gases. The method can include (i) rotating the top plate or the bottom plate of the shower head to a first position to allow a gas to flow through the shower head; (ii) performing a surface modification cycle that includes: applying a negative direct current (DC) bias voltage to the shower head, applying an RF power signal to the wafer chuck; and (iii) performing an etching cycle that includes: removing the negative DC bias voltage from the shower head and lowering the RF power signal applied to the wafer chuck.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin, Yu Lun Ke
  • Patent number: 10519543
    Abstract: There is provided a technique that includes: a reaction chamber that processes a substrate on a substrate support; a transfer chamber; a gate that opens and closes an opening and is formed in the transfer chamber; a transfer device; a clean unit supplying a clean atmosphere to the transfer chamber; an inert gas supplier supplying an inert gas to the transfer chamber; and a controller controlling the inert gas supplier such that, after the loading of the substrate from a substrate container to the substrate support by the transfer device is completed and the gate is closed, the inert gas supplier supplies the inert gas during a time period until the gate is opened again and does not supply the inert gas in another time period, and control the transfer chamber to be kept at a positive pressure by an air atmosphere.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 31, 2019
    Assignee: Kokusai Electric Corporation
    Inventor: Akinari Hayashi
  • Patent number: 10520833
    Abstract: Semiconductor systems, apparatuses and methods are provided. In one embodiment, an extreme ultraviolet lithography system includes a substrate stage configured to secure a substrate at a first vertical level, wherein the substrate is deposited with a resist layer thereon; at least one electrode positioned at a second vertical level above the first vertical level; and a power source configured to apply an electric field across the at least one electrode and the substrate stage, including across a thickness of the resist layer when the substrate is secured on the substrate stage.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10475671
    Abstract: Disclosed is a substrate processing apparatus including: a holding unit configured to hold a substrate; a processing liquid supply unit configured to supply a first processing liquid and a second processing liquid to the substrate; a first cup configured to recover the first processing liquid; a second cup disposed adjacent to the first cup and configured to recover the second processing liquid; a recovery portion defined by a peripheral wall portion that is erected on a bottom portion of the first cup; and a cleaning liquid supply unit configured to supply a cleaning liquid to the recovery portion. The peripheral wall portion is cleaned by causing the cleaning liquid supplied by the cleaning liquid supply unit to overflow from the peripheral wall portion to the second cup side.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 12, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Jiro Higashijima, Nobuhiro Ogata, Yusuke Hashimoto
  • Patent number: 10438837
    Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm?2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bradley David Sucher, Bernard John Fischer, Abbas Ali
  • Patent number: 10423067
    Abstract: Disclosed is a method of generating a physical unclonable function (PUF) by causing unpredictable partial process failure for a semiconductor process. In a designing process, a second mask pattern may be printed by distorting a size and/or shape of at least one mask window included in a designed first mask pattern, without violating semiconductor design rules. A PUF may be generated using a photomask including the printed second mask pattern for photolithography.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: September 24, 2019
    Assignee: ICTK Holdings Co., Ltd.
    Inventors: Byong Deok Choi, Dong Kyue Kim, Kwang Hyun Jee
  • Patent number: 10319624
    Abstract: Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 11, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Yihong Chen, Kelvin Chan, Abhijit Basu Mallick, Srinivas Gandikota, Pramit Manna
  • Patent number: 10312055
    Abstract: A method of forming a film on a substrate by PEALD includes deposition cycles, each including (i) feeding a precursor in a pulse to a reaction space to adsorb a precursor on a surface of a substrate; (ii) after step (i), applying RF power to a second electrode to generate in the reaction space a plasma to which the precursor-adsorbed surface is exposed, thereby forming a sublayer on the surface; and (iii) applying a bias voltage to the second electrode while applying RF power in step (ii), which bias voltage is negative with reference to a potential on a surface of the first electrode, wherein the cycle is repeated to deposit multiple sublayers until a film constituted by the sublayers has a desired thickness.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: June 4, 2019
    Assignee: ASM IP Holding B.V.
    Inventor: Toshiya Suzuki
  • Patent number: 10297439
    Abstract: A film forming method of depositing a thin film of a reaction product generated by a reaction between a raw material gas and a reactive gas on a substrate by alternately supplying the raw material gas and the reactive gas to the substrate accommodated in a processing container. The film forming method includes: storing the raw material gas in a reservoir; adsorbing the raw material gas on the substrate by supplying the raw material gas stored in the reservoir to the substrate; and reacting the raw material gas and the reactive gas with each other by supplying the reactive gas to the substrate on which the raw material gas is adsorbed to generate the reaction product; wherein the storing, the adsorbing, and the reacting are repeated a plurality of times, while a condition for the storing is changed at least once.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Yuya Takamura
  • Patent number: 10290505
    Abstract: Compositions useful for the passivation of germanium-containing materials on a microelectronic device having same thereon.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 14, 2019
    Assignee: Entegris, Inc.
    Inventors: Steven Bilodeau, Emanuel I. Cooper, Hsing-Chen Wu, Min-Chieh Yang
  • Patent number: 10229958
    Abstract: Devices including organic and inorganic LEDs are provided. Techniques for fabricating the devices include fabricating an inorganic LED on a parent substrate and transferring the LED to a host substrate via a non-destructive ELO process. Scaling techniques are also provided, in which an elastomeric substrate is deformed to achieve a desired display size.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: March 12, 2019
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Kyusang Lee
  • Patent number: 10214815
    Abstract: Methods and apparatus relating to aluminum nitride baffles are provided herein. In some embodiments, a baffle for use in semiconductor process chambers may include a body comprising aluminum nitride and a metal oxide binding agent, wherein a ratio of aluminum nitride to metal oxide on a surface of the body is greater than or equal to the ratio within the body. In some embodiments, the body may have a center stem and an outer annulus coupled to and extending radially outwards from a lower portion of the center stem. In some embodiments, a method of fabricating a baffle may include sintering aluminum, nitrogen, and a metal oxide binding agent to form a body of the baffle, the body having excess metal oxide binding agent disposed on a surface thereof; and removing a bulk of the excess metal oxide binding agent from a surface of the body.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 26, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Muhammad M. Rasheed, Dmitry Lubomirsky
  • Patent number: 10199213
    Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Suvi P. Haukka, Fu Tang, Michael E. Givens, Jan Willem Maes, Qi Xie
  • Patent number: 10163753
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10145013
    Abstract: A wafer carrier for use in a chemical vapor deposition (CVD) system includes a plurality of wafer retention pockets, each having a peripheral wall surface surrounding a floor surface and defining a periphery of that wafer retention pocket. Each wafer retention pocket has a periphery with a shape defined by at least a first arc having a first radius of curvature situated around a first arc center and a second arc having a second radius of curvature situated around a second arc center. The second arc is different from the first arc, either by its radius of curvature, arc center, or both.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 4, 2018
    Assignee: Veeco Instruments Inc.
    Inventors: Sandeep Krishnan, Lukas Urban
  • Patent number: 10084092
    Abstract: A method of forming a semiconductor device includes providing a substrate structure having a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure includes a semiconductor layer and a hard mask layer on top of the semiconductor layer. The method also includes forming a spacer layer on sidewalls of the fin structure. Next, using the hard mask layer and the spacer layer as a mask, the semiconductor substrate is etched to form recesses on both sides of the fin structure that extend partially to underneath the bottom of the fin structure. The method further includes forming a filler material to fill at least the recesses, thereby forming the first filler layer. The first filler layer may be oxidized to form a porous oxide layer and the remaining portion of the substrate under the fin structures may be oxidized to form an oxide layer.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 25, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10074535
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor containing a predetermined element to the substrate in a process chamber, removing the precursor from the process chamber, supplying a first reactant containing nitrogen, carbon and hydrogen to the substrate, removing the first reactant from the process chamber, supplying a second reactant containing oxygen to the substrate, and removing the second reactant from the process chamber. A time period of the act of removing the precursor is set to be longer than a time period of the act of removing the first reactant, or a time period of the act of removing the second reactant is set to be longer than the time period of the act of removing the first reactant.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: September 11, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tatsuru Matsuoka, Yoshiro Hirose, Yoshitomo Hashimoto
  • Patent number: 10056573
    Abstract: The present disclosure provides an organic light-emitting diode (OLED) display panel and a manufacturing method thereof and a display. The OLED display panel includes a glass back plate, a glass cover plate and the frit and multiple metal blocks located between the glass back plate and the glass cover plate. Each metal block is coated with an inorganic protective layer. There is a hole region between two adjacent metal blocks. The frit is in contact with the glass back plate via the hole regions. At least one of the metal blocks has a surface that can reflect incident laser light to the hole regions.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 21, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Ang Xiao
  • Patent number: 10049848
    Abstract: Technologies are described for methods for fabricating a film component. The methods may comprise sputtering a first film onto a substrate. The first film may include a semiconductor compound material. The semiconductor compound material may include a semi-metal material and one or more alkali material. The methods may further comprise evaporating a second film onto the first film. The second film may include the one or more alkali materials. The one or more alkali materials may catalyze crystallization of the semiconductor compound material in the first film substantially throughout the first film to form the film component in the first layer.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 14, 2018
    Assignees: Brookhaven Science Associates, LLC, The Regents of the University of California
    Inventors: John Smedley, Klaus Attenkofer, Susanne Schubert, Mengjia Gaowei, John Walsh
  • Patent number: 10026919
    Abstract: An organic light-emitting device includes a first electrode, a first light-emitting layer, a first low work function layer, a second low work function layer, a conductive etching-resistant layer, a first hole-injection layer, a second light-emitting layer, and a second electrode. The first light-emitting layer is disposed over the first electrode. The first low work function layer is disposed over the first light-emitting layer. The second low work function layer is disposed over the first low work function layer, and a work function of the second low work function layer is greater than a work function of the first low work function layer. The conductive etching-resistant layer is disposed over the second low work function layer. The first hole-injection layer is disposed over the conductive etching-resistant layer. The second light-emitting layer is disposed over the first hole-injection layer. The second electrode is disposed over the second light-emitting layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 17, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Hsiao-Wen Zan, Hao-Wen Chang, Cheng-Hang Hsu
  • Patent number: 10014361
    Abstract: Disclosed is an organic light emitting display device which includes an auxiliary line connected to a first power line and an auxiliary electrode connected to a second power line, thereby lowering a line resistance of each of the first and second power lines. The organic light emitting display device includes a substrate, a thin film transistor (TFT) disposed on the substrate, a first power line disposed in a first layer including the source electrode and the drain electrode of the TFT, a second power line disposed over the first layer, an auxiliary line disposed in a second layer including the second power line, an anode electrode disposed on the second power line and the auxiliary line and electrically connected to the drain electrode, an organic layer disposed on the anode electrode, and a cathode electrode covering the organic layer and electrically connected to the second power line.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 3, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Jeong Hyeon Choi, Jae Hee Park, Joon Soo Han
  • Patent number: 10014368
    Abstract: An IGBT region includes a collector layer, a first drift layer, a first body layer, an emitter layer, and a trench gate reaching the first drift layer through the first body layer from a front surface side of a semiconductor substrate. A diode region includes a cathode layer, a second drift layer, and a second body layer. A lifetime control region which includes a peak of a crystal defect density is provided in the first drift layer and the second drift layer that are located between a depth of a lower end of the trench gate and surfaces of the first drift layer and the second drift layer. A silicon nitride film is further provided above the trench gate on the front surface side of the semiconductor substrate.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: July 3, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya Iwasaki, Satoru Kameyama
  • Patent number: 9978830
    Abstract: An IGBT region includes a collector layer, a first drift layer, a first body layer, an emitter layer, and a trench gate reaching the first drift layer through the first body layer from a front surface side of a semiconductor substrate. A diode region includes a cathode layer, a second drift layer, and a second body layer. A lifetime control region which includes a peak of a crystal defect density is provided in the first drift layer and the second drift layer that are located between a depth of a lower end of the trench gate and surfaces of the first drift layer and the second drift layer. A silicon nitride film is further provided above the trench gate on the front surface side of the semiconductor substrate.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: May 22, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya Iwasaki, Satoru Kameyama
  • Patent number: 9972486
    Abstract: There is provided a method for forming a nitride film on a substrate to be processed by a thermal ALD which repeats: supplying a film forming raw material gas to the substrate to be processed while heating the substrate to be processed to a predetermined temperature; and supplying a nitriding gas to the substrate to be processed, the nitride film forming method comprises supplying a chlorine-containing gas to the substrate to be processed after the supplying the film forming raw material gas.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 15, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Murakami, Takahiro Miyahara, Daisuke Suzuki
  • Patent number: 9947510
    Abstract: In the exemplary embodiment, a method for supplying a gas is provided. This method includes supplying a processing gas to each of a central gas inlet portion and a peripheral gas inlet portion through a first branch line and a second branch line; closing a valve at a downstream side in a gas line for an additional gas, and filling the additional gas in a tube between the valve and an upstream flow rate controller; opening the valve after filling the additional gas, and supplying a high frequency power to one of an upper electrode and a lower electrode from a high frequency power supply after opening the valve.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 17, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tomoyuki Mizutani, Hiroshi Tsujimoto
  • Patent number: 9941244
    Abstract: In accordance with a method embodiment includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
  • Patent number: 9874517
    Abstract: A processing apparatus includes: a light emission unit configured to emit light to a surface of a particle dispersed liquid applied to a base material, the particle dispersed liquid having particles dispersed in a solvent; a reflected light amount monitoring unit configured to detect an amount of the light reflected, and monitor a temporal variation of the detected value; and a condition adjustment unit configured to adjust a condition for a particle securing process, the particle securing process being performed to remove the solvent and secure the particles onto the base material, wherein, when the temporal variation falls within a predetermined range after the value has reached an extreme value, securing of the particles is determined to have been completed.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: January 23, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Keita Saito, Midori Shimomura, Dai Suwama, Sayaka Morita
  • Patent number: 9873943
    Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a processing chamber; a wafer stage configured in the processing chamber, the wafer stage is operable to secure and rotate a plurality of wafers around an axis; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: RE47093
    Abstract: An imprint pattern forming method includes contacting a template with a pattern in a front surface with an imprint material formed in a substrate to fill the imprint material into the pattern, curing the imprint material filled in the pattern to form an imprint material pattern, and after forming the imprint material pattern, separating the template from the imprint material pattern while applying pressure to the back surface of the template.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: October 23, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Tokue, Ikuo Yoneda, Ryoichi Inanami