Coating Of Substrate Containing Semiconductor Region Or Of Semiconductor Substrate Patents (Class 438/758)
  • Patent number: 12258499
    Abstract: The present invention is a method for peeling an adherend from a pressure-sensitive adhesive layer by irradiating a laminate in which the pressure-sensitive adhesive layer and the adherend are laminated with light, the peeling method includes a step of irradiating the pressure-sensitive adhesive layer with the light having a pulse width of 1 second or less and a light irradiation amount of 1,000 mJ/cm2 or more, and the pressure-sensitive adhesive layer satisfies predetermined conditions in terms of a minimum transmittance in a near-infrared region of a wavelength of 800 nm to 2,500 nm and a maximum transmittance in a visible light region of a wavelength of 380 nm to 780 nm.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: March 25, 2025
    Assignee: NITTO DENKO CORPORATION
    Inventor: Yosuke Shimizu
  • Patent number: 12253805
    Abstract: An overlay metrology target may include grating-over-grating structures formed from a lower grating structure with a first coarse pitch in a first sample layer and an upper grating structure with a second coarse pitch in a second sample layer, where the upper and lower grating structures overlap on the sample. At least one of the upper grating structure or the lower grating structure may include features with a fine pitch smaller than a wavelength of an illumination beam and arranged to rotate first-order diffraction of the illumination beam associated with at least one of the first or second coarse pitches with respect to at least one of specular reflection from a top surface of the sample or zero-order diffraction from the one or more grating structures. Overlay between the first and second layers of the sample is determinable from an image of the grating structures based on the first-order diffraction.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: March 18, 2025
    Assignee: KLA Corporation
    Inventors: Vladimir Levinski, Daria Negri, Amnon Manassen
  • Patent number: 12247290
    Abstract: Provided is a flow rate control method, including: supplying fluid from a valve to a first sensor; measuring, by the first sensor, a first temperature of the fluid, and heating the fluid; measuring, by a second sensor, a second temperature of the heated fluid, and determining, by a controller, a first flow rate of the fluid based on comparison between the first temperature and the second temperature; supplying the fluid to a chamber and supplying an ignition voltage to the chamber through a radio frequency (RF) power source; measuring, by a third sensor, the ignition voltage; comparing, by the controller, the ignition voltage and a reference voltage to determine a second flow rate of the fluid; and controlling a supply of the fluid from the valve based on at least one of the first flow rate and or the second flow rate.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: March 11, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suncheul Kim, Donghyun Lee, Uihyoung Lee, Donghoon Han
  • Patent number: 12249507
    Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 12249485
    Abstract: There is provided a plasma vessel in which a process gas is plasma-excited; a substrate process chamber which is in communication with the plasma vessel; a gas supply system supplying the process gas; and a coil installed to wind around an outer periphery of the plasma vessel and supplied with high-frequency power, wherein the coil is installed such that: a distance from an inner periphery of the coil to an inner periphery of the plasma vessel at a predetermined position on the coil is different from a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at another position on the coil; and a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at a position at which an amplitude of a standing wave of a voltage applied to the coil is maximized is maximized.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: March 11, 2025
    Assignee: Kokusai Electric Corporation
    Inventors: Takeshi Yasui, Katsunori Funaki, Masaki Murobayashi, Koichiro Harada
  • Patent number: 12241157
    Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ting Tsai, Hung-Chih Wang, Hong-Ming Lo, Shao-Shuo Wu, Su-Yu Yeh
  • Patent number: 12243871
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Patent number: 12237216
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 25, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Shihsheng Chang, Ying Trickett, Eric Chih-Fang Liu, Yun Han, Henan Zhang, Cory Wajda, Robert D. Clark, Gerrit J. Leusink, Gyanaranjan Pattanaik, Hiroaki Niimi
  • Patent number: 12237171
    Abstract: Methods and systems for depositing vanadium nitride layers onto a surface of the substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium nitride layer onto a surface of the substrate. The cyclical deposition process can include providing a vanadium halide precursor to the reaction chamber and separately providing a nitrogen reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: February 25, 2025
    Assignee: ASM IP Holding B.V.
    Inventors: Giuseppe Alessio Verni, Qi Xie, Henri Jussila, Charles Dezelah, Jiyeon Kim, Eric James Shero, Paul Ma
  • Patent number: 12209311
    Abstract: The present invention provides a high-throughput vapor deposition apparatus and a vapor deposition method. A rotary workbench (2) is located in a reaction chamber (1); a gas introduction device (3) is located in the reaction chamber (1) and above the rotary workbench (2); a plurality of through holes (31) is provided on the gas introduction device (3); a gas isolation structure (4) divides an upper chamber (11) into an isolation gas chamber (111) and a reaction gas chamber (112) which are isolated from each other; an isolation gas is introduced into the isolation gas chamber (111) via an isolation gas introduction channel (5), and a reaction gas is introduced into the reaction gas chamber (112) via a reaction gas introduction channel (6), for carrying out thin film deposition on an area of a substrate corresponding to the reaction gas chamber (112).
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: January 28, 2025
    Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Weimin Li, Wenjie Yu, Lei Zhu, Yiying Wang
  • Patent number: 12209312
    Abstract: A system to process a semiconductor substrate includes a substrate support assembly configured to support the semiconductor substrate. The substrate support assembly includes M resistive heaters respectively arranged in M zones in a layer of the substrate support assembly, where M is an integer greater than 1. The layer is adjacent to the semiconductor substrate. The substrate support assembly includes N temperature sensors arranged at N locations in the layer, where N is an integer greater than 1 and less than or equal to M. The system further includes a controller configured to control one or more of the M resistive heaters based on a temperature sensed by one of the N temperature sensors and average temperatures of one or more of the M zones.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: January 28, 2025
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ramesh Chandrasekharan, Michael Philip Roberts, Aaron Bingham, Ashish Saurabh, Adrien Lavoie, Pulkit Agarwal, Ravi Kumar
  • Patent number: 12205919
    Abstract: A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: January 21, 2025
    Assignee: Infineon Technologies AG
    Inventors: Chuan Cheah, Josef Hoeglauer, Tobias Polster
  • Patent number: 12202136
    Abstract: An automatic lubrication robot includes a robot, a grease hose, and a delivery unit. The robot includes a lifting and lowering unit that moves linearly and an arm coupled to the lifting and lowering unit, and the robot is arranged in a clean room to perform an operation. Grease for lubricating the robot passes through the grease hose. In response to the linear movement of the lifting and lowering unit, the delivery unit delivers the grease to the robot via the grease hose.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: January 21, 2025
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Takeshi Shibata, Ryota Ono
  • Patent number: 12195851
    Abstract: Methods of depositing thin films for an electronic device, for example a semiconductor device include applying a first pulsed plasma with or without a reactant and a second continuous plasma with a reactant.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 14, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Cong Trinh, Maribel Maldonado-Garcia, Mihaela A. Balseanu, Alexander V. Garachtchenko, Tsutomu Tanaka
  • Patent number: 12191226
    Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1 and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: January 7, 2025
    Assignees: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ming-Tzong Yang, Hsien-Hsin Lin, Wen-Kai Wan, Chia-Che Chung, Chee-Wee Liu
  • Patent number: 12170221
    Abstract: The present inventive concept relates to a substrate processing apparatus including a supporting part for supporting a substrate; a disk supporting a plurality of the supporting parts; a lid disposed on the disk; and a first protrusion portion coupled to the disk to protrude in an upward direction from the disk to the lid in a center region disposed inward from the supporting parts and a gap region disposed between the supporting parts.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 17, 2024
    Assignee: JUSUNG ENGINEERING CO., LTD.
    Inventors: Won Woo Jung, Young-Rok Kim, Yoo Seong Kim, Jong Sik Kim, Chul Joo Hwang
  • Patent number: 12165842
    Abstract: A control method of a plasma processing apparatus including a first electrode that places a workpiece thereon includes supplying a bias power to the first electrode, and supplying a source power having a frequency higher than that of the bias power into a plasma processing space. The source power has a first state and a second state. The control method further includes a first control process of alternately applying the first state and the second state of the source power in synchronization with a signal synchronized with a cycle of a radio frequency of the bias power, or a phase within one cycle of a reference electrical state that represents any one of a voltage, current, and electromagnetic field measured in a power feeding system of the bias power.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 10, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Chishio Koshimizu, Taichi Hirano, Toru Hayasaka, Shinji Kubota, Koji Maruyama, Takashi Dokan
  • Patent number: 12154800
    Abstract: Even a radiation thermometer using a quantum infrared sensor appropriately measures the temperature of a substrate irradiated with a flash of light. A heat treatment apparatus includes a quantum infrared sensor configured to measure a temperature of the first substrate and a temperature of the second substrate. The heat treatment apparatus further includes a temperature correction unit configured to correct, using a correction coefficient calculated based on the reference temperature and the shift temperature, a temperature of the second substrate on which second heat treatment having irradiation with the flash of light is performed, the temperature being measured by the quantum infrared sensor.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 26, 2024
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takahiro Kitazawa, Yukio Ono, Oma Nakajima
  • Patent number: 12154769
    Abstract: A window device for diagnosis of plasma OES (Optical Emission Spectroscopy), is disclosed and includes a housing including a first chamber and a second chamber horizontally adjacent to each other; a connection opening defined in one face of the housing and between the first and second chambers, the connection opening faces toward an opening through which light of plasma from a plasma chamber is exposed to the connection opening; an observation window opening defined in an opposite face of the housing opposite to the connection opening, the observation window opening is coaxial with the connection opening, the light of the plasma transmits through the observation window opening, and is incident to a light receiver of an OES sensor; an observation window positioned inside the observation window opening and in the housing; a winder and a rewinder installed in the first and second chambers, respectively; and a transparent film.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 26, 2024
    Assignee: KOREA INSTITUTE OF FUSION ENERGY
    Inventors: Kang Il Lee, Yong Sup Choi, Young Woo Kim, Jong Sik Kim
  • Patent number: 12144120
    Abstract: A mold includes a mold base material and a rugged structure located at a main surface of the mold base material. The rugged structure includes a plurality of linearly shaped projected portions for forming wiring, and a circularly shaped projected portion for forming a pad portion, in which a light-shielding layer is provided at a top portion flat surface of the circularly shaped projected portion for forming the pad portion.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 12, 2024
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Ryohei Kasai, Tadashi Furukawa, Ryo Furugen, Teppei Sotoda, Tetsushi Hosoda, Ayako Furuse
  • Patent number: 12135769
    Abstract: The present disclosure describes an integration platform providing a secure collaboration platform that simplifies and optimizes interactions between multiple users by facilitating secure cross-platform communications among users of the platform. Additionally, the present platform can provide a designated collaboration workspace for interactions within the platform.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 5, 2024
    Assignee: Glicq, Inc.
    Inventors: Matan Barak, Oren Barak
  • Patent number: 12130553
    Abstract: A resist material dispensing system includes a resist supply and a resist filter connected to the resist supply downstream from the resist supply. The resist material dispensing system includes a resist tank structure connected to the resist filter downstream from the resist filter and a resist pump device connected to the resist tank structure downstream from the resist tank structure. The resist tank structure is vertically arranged so that a resist material flows in a continuous downward flow from where the resist material enters the resist tank structure until the resist material exits the resist tank structure.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Yi Hsu, Shang-Sheng Li, Yung-Yao Lee
  • Patent number: 12119244
    Abstract: According to the present disclosure, a semiconductor manufacturing apparatus includes a rotation stage that rotates a wafer, a nozzle that supplies a chemical solution to the wafer and a nozzle movement section that moves the nozzle on a scan trajectory, wherein the nozzle movement section moves the nozzle along a first trajectory and a second trajectory on the scan trajectory, the first trajectory is a trajectory to turn around at a first turnaround point on one side and a second turnaround point on the other side with respect to a portion closest to a rotation axis of the rotation stage in the scan trajectory, and the second trajectory is a trajectory to turn around at a third turnaround point and a fourth turnaround point provided on the same side as the third turnaround point with respect to the portion closest to the rotation axis in the scan trajectory.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: October 15, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroshi Tanaka
  • Patent number: 12094708
    Abstract: There is provided a technique that includes: forming a film containing a main element, carbon and nitrogen on a pattern formed on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) forming a first layer containing the main element by supplying a precursor, which contains the main element constituting the film to be formed, to the substrate having the pattern; and (b) forming a second layer containing the main element, carbon and nitrogen by supplying a first reactant, which contains carbon and nitrogen, to the substrate so that a substance obtained by decomposing a portion of the first reactant is adsorbed on the first layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2024
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Masaya Nagato
  • Patent number: 12091753
    Abstract: A substrate processing apparatus includes a processing module including a first sidewall and a second sidewall that are spaced apart in a first horizontal direction, and a transferring module that is configured to transfer a substrate to the processing module and that is disposed adjacent to the first sidewall. The processing module includes a first processing container and a second processing container that are adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction. A maintenance opening common for performing maintenance on the first processing container and the second processing container is provided in the second sidewall. The maintenance opening is provided to include an intermediate position between the first processing container and the second processing container in the second horizontal direction.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: September 17, 2024
    Assignee: Tokyo Electron Limited
    Inventor: Manabu Honma
  • Patent number: 12080550
    Abstract: There is provided a technique that includes: forming a film so as to be embedded in a recess formed on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a pseudo-catalyst to the substrate in a process chamber; (b) exhausting the pseudo-catalyst remaining in the process chamber; (c) supplying a precursor to the substrate in the process chamber; and (d) exhausting the precursor remaining in the process chamber, wherein in (a), the pseudo-catalyst is adsorbed on the surface of the substrate under a condition that chemical adsorption of the pseudo-catalyst on the surface of the substrate is unsaturated.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: September 3, 2024
    Assignee: Kokusai Electric Corporation
    Inventor: Kimihiko Nakatani
  • Patent number: 12080526
    Abstract: The present disclosure relates to a substrate processing apparatus capable of improving efficiency in a substrate processing process by adjusting a flow rate and residence time of gas and a plasma density according to process conditions. The substrate processing apparatus according to the embodiment of the present disclosure is advantageous in that it can enhance efficiency in the substrate processing process by decreasing the flow rate and increasing residence time of gas and the plasma density in the process of supplying the gas through the shape forming of the gas injection module including the first and second injection plates.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: September 3, 2024
    Assignee: JUSUNG ENGINEERING CO., LTD.
    Inventors: Woong Kyo Oh, Young Woon Kim, Kwang Su Yoo, Do Hyung Kim, Yun Gyu Ha
  • Patent number: 12077854
    Abstract: A chemical vapor deposition furnace for depositing silicon nitride films is disclosed. The furnace includes a process chamber elongated in a substantially vertical direction and a wafer boat for supporting a plurality of wafers in the process chamber. A process gas injector inside the process chamber is provided with vertically spaced gas injection holes to provide gas introduced at a feed end in an interior of the process gas injector to the process chamber. A valve system connected to the feed end of the process gas injector is being constructed and arranged to connect a source of a silicon precursor and a nitrogen precursor to the feed end for depositing silicon nitride layers. The valve system may connect the feed end of the process gas injector to a cleaning gas system to provide a cleaning gas to remove silicon nitride from the process gas injector and/or the process chamber.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: September 3, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Dieter Pierreux, Theodorus G. M. Oosterlaken, Herbert Terhorst, Lucian Jdira, Bert Jongbloed
  • Patent number: 12078924
    Abstract: A layout correction method is provided. The layout correction method includes: providing an initial layout; expanding the initial layout to obtain an expanded layout; correcting the expanded layout to obtain a corrected layout; and obtaining a target layout based on the corrected layout.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Tingting Xu
  • Patent number: 12074027
    Abstract: A method includes providing a layered structure on a substrate, the layered structure including a bottom layer formed over the substrate and a photoresist layer formed over the bottom layer, exposing the photoresist layer to a radiation source, developing the photoresist layer, patterning the bottom layer and removing portions of the substrate through openings in the patterned bottom layer. In some embodiments, a middle layer is provided between the bottom layer and the photoresist layer. The material of the bottom layer includes at least one cross-linking agent that has been functionalized to decrease its affinity to other materials in the bottom layer.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Hong Huang, Wei-Han Lai, Ching-Yu Chang
  • Patent number: 12068154
    Abstract: Methods and systems for forming a forming a nitrogen-containing carbon film and structures formed using the methods or systems are disclosed. Exemplary methods include providing a precursor with carbon-terminated carbon-nitrogen bonds. The methods can further include providing a reactant to the reaction chamber.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: August 20, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Hirotsugu Sugiura, Yoshiyuki Kikuchi
  • Patent number: 12046489
    Abstract: A processing apparatus for a thermal treatment of a workpiece is presented. The processing apparatus includes a processing chamber, a workpiece support disposed within the processing chamber, a gas delivery system configured to flow one or more process gases into the processing chamber from the a first side of the processing chamber, one or more radiative heating sources disposed on the second side of the processing chamber, one or more dielectric windows disposed between the workpiece support and the one or more radiative heating sources, a rotation system configured to rotate the one or more radiative heating sources, and a workpiece temperature measurement system configured at a temperature measurement wavelength range to obtain a measurement indicative of a temperature of a back side of the workpiece.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 23, 2024
    Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.
    Inventors: Rolf Bremensdorfer, Dieter Hezler
  • Patent number: 12018375
    Abstract: There is provided a film forming method of forming a carbon-containing film by a microwave plasma from a microwave source, the film forming method including: a dummy step of performing a dummy process by generating plasma of a first carbon-containing gas within a processing container; a placement step of placing a substrate on a stage within the processing container; and a film forming step of forming the carbon-containing film on the substrate using plasma of a second carbon-containing gas.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 25, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ryota Ifuku, Takashi Matsumoto, Masahito Sugiura, Makoto Wada
  • Patent number: 12014925
    Abstract: Exemplary deposition methods may include delivering a ruthenium-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. At least one of the ruthenium-containing precursor or the hydrogen-containing precursor may include carbon. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a ruthenium-and-carbon material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: June 18, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Bhaskar Jyoti Bhuyan, Mark J. Saly, Abhijit Basu Mallick
  • Patent number: 11993849
    Abstract: According to one embodiment, there is provided a carbon hard mask laminated on an etching target film, in which the concentration ratio of a methylene group CH2 and a methyl group CH3 contained in the carbon hard mask satisfies the expression CH2/(CH2+CH3)?0.5.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 28, 2024
    Assignees: TOKYO ELECTRON LIMITED, National University Corporation Tokai National Higher Education and Research System
    Inventors: Masaru Hori, Makoto Sekine, Hirotsugu Sugiura, Tsuyoshi Moriya, Satoshi Tanaka, Yoshinori Morisada
  • Patent number: 11982015
    Abstract: Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 14, 2024
    Assignee: SILTRONIC AG
    Inventors: Joerg Haberecht, Stephan Heinrich, Reinhard Schauer, Rene Stein
  • Patent number: 11965262
    Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 23, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Yong Min Yoo, Jong Won Shon, Seung Woo Choi, Dong Seok Kang
  • Patent number: 11967534
    Abstract: A technique capable of coping with change in the environment for each of the substrate placing surfaces is provided. According to one aspect thereof, there is provided a method of manufacturing a semiconductor device, including: (a) supplying a gas to a process vessel through branch pipes while substrates are placed on substrate placing surfaces arranged in the process vessel, respectively; (b) detecting at least one among: information of a component corresponding to each of the substrate placing surfaces; and an amount of the gas supplied to each of the branch pipes; (c) determining a state level of each of the substrate placing surfaces based on the detected information; and (d) selecting a substrate placing surface among the substrate placing surfaces to which a substrate subsequently loaded into the process vessel is to be transferred next according to the state level of each of the substrate placing surfaces.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 23, 2024
    Assignee: Kokusai Electric Corporation
    Inventor: Tsukasa Kamakura
  • Patent number: 11961718
    Abstract: A plasma processing method of processing a substrate with plasma in a plasma processing apparatus. The plasma processing apparatus includes: a chamber configured to accommodate a substrate; an upper electrode structure forming an upper portion of the chamber and including a temperature-controlled plate, an electrode plate disposed below the temperature-controlled plate, and an electrostatic attractor, the electrostatic attractor including a contact surface, an attraction surface, a first electrode, and a second electrode; a power supply configured to apply a voltage to the first and second electrodes; and a temperature obtaining portion configured to acquire a temperature distribution of the electrode plate.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 16, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shojiro Yahata, Tetsuji Sato
  • Patent number: 11955359
    Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Young Oh, Seung Hwan Kim, Jong Ho Park, Yong Kwan Lee, Jong Ho Lee
  • Patent number: 11955370
    Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
  • Patent number: 11955430
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hsuan Lin, Hsi Chung Chen, Ji-Ling Wu, Chih-Teng Liao
  • Patent number: 11942310
    Abstract: In an active gas generation apparatus of the present invention, an auxiliary conductive film provided on a first electrode dielectric film is provided to overlap part of an active gas flow path in plan view, and the auxiliary conductive film is set to the ground potential. An active gas auxiliary member provided on a second electrode dielectric film is provided to fill part of the active gas flow path between a discharge space and a gas ejection hole in a dielectric space between the first and second electrode dielectric films in order to limit to an active gas flow gap.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: March 26, 2024
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Ren Arita, Kensuke Watanabe
  • Patent number: 11939678
    Abstract: A method of making a semiconductor manufacturing apparatus member includes a step of preparing an aluminum base having an alumite layer having a porous columnar structure at an upper surface thereof. The alumite layer is an anodic oxidation film, and a Young's modulus of the alumite layer is between 90 GPa and 120 GPa. The method also includes a step of forming a particle-resistant layer on the alumite layer by aerosol deposition, in which an aerosol containing fine particles of a brittle material dispersed in a gas is ejected from a nozzle to impact against a surface of the alumite layer, wherein the particle-resistant layer includes a polycrystalline ceramic; and wherein, when the resulting semiconductor manufacturing apparatus member is exposed to a plasma in a reference plasma resistance test, the particle-resistant layer has an arithmetic average height Sa of 0.060 or less after the reference plasma test is completed.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: March 26, 2024
    Assignee: TOTO LTD.
    Inventors: Yasutaka Nitta, Takuma Wada
  • Patent number: 11934097
    Abstract: The present invention provides an imprinting method, which includes the steps of: adding a soluble material to a master mold; solidifying the soluble material to form a soluble mold having a mold pattern; adhering a taking device to the soluble mold to separate the soluble mold from the master mold; placing the soluble mold on a polymer layer of a workpiece for imprint; applying a high temperature and a pressure to the soluble mold to allow the polymer layer having an imprint pattern corresponding to the mold pattern and being solidified, and to remove the taking device from the soluble mold; and providing a solvent to dissolve the soluble mold to obtain an imprint workpiece having the imprint pattern.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: March 19, 2024
    Assignee: EVER RADIANT INCORPORATION
    Inventor: Sung-Wen Tsai
  • Patent number: 11929389
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
  • Patent number: 11908682
    Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) forming a first oxide layer by modifying a surface of a substrate at a first temperature with a plasma of a first oxygen-containing gas; and (b) forming a second oxide layer thicker than the first oxide layer by heating the substrate to a second temperature higher than the first temperature and modifying the surface of the substrate, on which the first oxide layer is formed, with a plasma of a second oxygen-containing gas.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 20, 2024
    Assignee: Kokusai Electric Corporation
    Inventors: Hiroto Igawa, Masanori Nakayama, Katsunori Funaki, Tatsushi Ueda, Yasutoshi Tsubota, Eiko Takami, Yuichiro Takeshima, Yuki Yamakado
  • Patent number: 11905163
    Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided by the embodiments of the present disclosure. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; and a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, and the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, and an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 20, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaochen Ma, Guangcai Yuan, Ce Ning, Xin Gu, Xiao Zhang, Chao Li
  • Patent number: 11901437
    Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
    Type: Grant
    Filed: May 15, 2022
    Date of Patent: February 13, 2024
    Assignee: Marlin Semiconductor Limited
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: RE49963
    Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: May 7, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Hwan Kim, Gigwan Park, Junggun You, DongSuk Shin, Jin-Wook Kim