Utilizing Reflow (e.g., Planarization, Etc.) Patents (Class 438/760)
  • Patent number: 5747375
    Abstract: A method of manufacturing a semiconductor integrated circuit device employs a new reflowing process of an insulating film having contact holes and openings therethrough. A good step coverage of a wiring electrode at the contact holes of the insulating film can be obtained with reduced thermal cycles in the manufacturing of integrated circuit devices, and also with a reduced heat treatment temperature of the reflowing process. The process includes a step of depositing a silicon nitride film on the insulating film and on the contact holes by chemical vapor deposition at a temperature between 700.degree. C. and 800.degree. C. so as to deform edges of the contact holes in the insulating film to be rounded and smooth.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: May 5, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Kaneko, Toshiyuki Ohkoda
  • Patent number: 5716673
    Abstract: A process for spreading and flowing in a flowable dielectric during manufacture of an integrated circuit resulting in greater planarity and better gap filling ability. The process involves spinning the integrated circuit while controlling evaporation of the solvent from the flowable dielectric to increase the amount of flow in time and decrease spin velocity during flow in to improve planarity in gap filling ability. The process includes supporting the integrated circuit in a chamber; dispensing the flowable dielectric in a solvent on the integrated circuit in the chamber; covering the integrated circuit to provide a controllable environment within the chamber after the step of dispensing; spinning the integrated circuit while controlling the controllable environment to spread and flow in the flowable dielectric; uncovering the integrated circuit within the chamber; spinning the integrated circuit to spin off flowable dielectric; and curing the flowable the flowable dielectric.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: February 10, 1998
    Assignee: Macronix InternationalCo., Ltd.
    Inventors: Daniel L. W. Yen, Been Yih Jin, Ming Hong Wang
  • Patent number: 5656556
    Abstract: An improved method for forming a planar borophosphosilicate glass (BPSG) insulating layer having a reduced thermal budget was achieved. The method involves forming a multilayer BPSG comprised of four layers with different boron and phosphorus concentrations in each layer. The first layer deposited has the conventional doping range, and therefore would require higher reflow temperatures for leveling. By the method of this invention, a second low-doped BPSG buffer layer is deposited and then a heavily doped third BPSG layer is deposited having a lower reflow temperature, and therefore is planarized at a lower temperature. A low-doped fourth cap BPSG layer is used over the third BPSG layer to minimize moisture absorption and unstable crystal formation prior to the reflow anneal.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: August 12, 1997
    Assignee: Vanguard International Semiconductor
    Inventor: Fu-Liang Yang
  • Patent number: 5656523
    Abstract: A process used during the formation of a semiconductor device comprises the formation of a stack having a substrate, a layer of oxide, a polycrystalline silicon layer, and a photoresist mask. An etch is performed to pattern the polycrystalline silicon layer, then the photoresist is flowed to cover the edges of the polycrystalline silicon. Finally, a doping step is performed using the flowed photoresist as a doping barrier, thus allowing for a distance between the poly and an implanted region in the substrate.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: August 12, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Michael S. Wilhoit
  • Patent number: 5656555
    Abstract: A modified hydrogen silsesquioxane (HSQ) precursor is disclosed, along with methods for depositing such a precursor on a semiconductor substrate and a semiconductor device having a dielectric thin film deposited from such a precursor. The method comprises coating a semiconductor substrate 10, which typically comprises conductors 12, with a film of a modified HSQ film precursor. The HSQ film precursor comprises a hydrogen silsesquioxane resin and a modifying agent, preferably selected from the group consisting of alkyl alkoxysilanes, fluorinated alkyl alkoxysilanes, and combinations thereof. The method further comprises curing film 14, wherein the inclusion of the modifying agent inhibits oxidation and/or water absorption by the film during and/or after curing. It is believed that the modifying agent modifies film surface 16 to produce this effect.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: August 12, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Chih-Chen Cho
  • Patent number: 5633211
    Abstract: The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: May 27, 1997
    Assignee: Matsushita Electric Industrial Co., Ld.
    Inventors: Shinichi Imai, Yuka Terai, Masanori Fukumoto, Kousaku Yano, Hiroyuki Umimoto, Shinji Odanaka, Yasuo Mizuno
  • Patent number: 5631174
    Abstract: A method for forming spacers having a prograde profile includes providing a semiconductor substrate having raised structures thereon having top and lateral surfaces. A layer of spacer material is then deposited conformably over the raised objects and the semiconductor substrate. A layer of compatible material having a lower viscosity at high temperature than the spacer material is then deposited conformably over the layer of spacer material. The layer of compatible material is then reflowed. The portions of the layer of spacer material and the layer of compatible material laterally enclosing the raised structures constitute spacers. The layer of compatible material is reflowed sufficiently to result in spacers having a prograde profile, i.e., to result in laterally outward facing surfaces of the spacers that slope laterally outward from the top surfaces of the raised objects downward.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: May 20, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer