Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: A cleaning method that can prevent abnormal wear of an O-ring. A cleaning gas containing at least oxygen gas is supplied to the interior of a chamber in which a substrate is accommodated, and radio-frequency voltage is applied to the interior of the chamber to produce oxygen radicals from the cleaning gas. When the amount of deposit produced in the chamber in plasma processing is larger than a predetermined amount, the amount of fluorine radicals in the chamber is increased, and when the amount of the deposit is smaller than the predetermined amount, the amount of fluorine radicals in the chamber is decreased.

Abstract: A method of preparing a thin film on a substrate is described. The method comprises forming an ultra-thin hermetic film over a portion of a substrate using a gas cluster ion beam (GCIB), wherein the ultra-thin hermetic film has a thickness less than approximately 5 nm. The method further comprises providing a substrate in a reduced-pressure environment, and generating a GCIB in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are selected to achieve a thickness of the thin film less than about 5 nanometers (nm). The GCIB is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate according to the beam dose. By doing so, the thin film is formed on the at least a portion of the substrate to achieve the thickness desired.

Abstract: A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

Abstract: A method of forming a semiconductor structure includes providing a first dielectric layer with an opening above a substrate. An exposed surface portion of the first dielectric layer in the opening is transformed. A protective dielectric layer is formed along the transformed portion of the first dielectric layer. The opening is filled with a conductive material. The transformed portion of the first dielectric layer is removed to form an air gap between the protective dielectric layer and a remaining portion of the first dielectric layer.

Abstract: A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon.

Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

Abstract: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole.

Abstract: A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method is disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. The cap is attached to the device chip using single phase metal alloy to achieve sealed cavity over the circuit element. The single phase metal alloy allows the cap to be diffusion bonded to the device chip at a higher diffusivity thus allowing diffusion at a lower temperature, lower pressure, shorter period, or a combination of these.

Abstract: Methods of forming a capping layer over a metal wire structure of a semiconductor device are disclosed. In one embodiment, the method includes providing a partially fabricated semiconductor device having exposed surfaces of the metal (e.g., copper) wire structure and a dielectric around the metal wire structure. The exposed surface of the metal wire structure is then activated by forming a seed layer thereon. The capping layer is then formed over the exposed surface of the metal wire structure by performing a selective atomic layer deposition (ALD) of a capping layer material onto the metal wire structure. As an alternative, the dielectric may be masked off to further assist the selectivity of the ALD. The invention also includes a semiconductor structure including the metal wire structure having an atomic layer deposition capping layer over an upper surface thereof.

Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.

Abstract: A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.

Abstract: A silicon nitride film, for example, is deposited by introducing into a plasma region of a chamber a silicon containing gas, molecular nitrogen and sufficient hydrogen to dissociate the nitrogen to allow the silicon and nitrogen to react to form a silicon nitride film on a surface adjacent the plasma region. The thus deposited film may then be subjected to an activation anneal.

Abstract: A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.

Abstract: This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.

Abstract: A method for forming a contact hole of a semiconductor device, wherein a polymer residual on a bottom surface of the contact hole is treated with plasma of mixture gas containing oxygen to convert the polymer residual into a pure silicon oxide film free of carbon and fluorine for easy removal in a subsequent washing process is disclosed. The method comprises (a) sequentially forming a capping layer and a planarized interlayer insulating film on a semiconductor substrate having a predetermined lower structure; (b) selectively etching the interlayer insulating film to expose a predetermined region of the capping layer; (c) removing the exposed capping layer; (d) subjecting the resulting structure to a plasma treatment using a mixture gas containing oxygen; and (e) performing a cleaning process.

Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern and a protection pattern formed on the conductive film pattern, forming a first insulation film to fill a space between adjacent conductive structures, successively etching the first insulation film and the protection patterns until each of the protection patterns has an exposed level upper surface, forming a second insulation film on the resultant structure, and selectively etching portions of the second insulation film and the first insulation film using a photolithography process to form the self-aligned contact hole exposing a portion of the semiconductor substrate between adjacent conductive structures.

Abstract: A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.

Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.

Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.

Abstract: A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process. The capping layer of the present invention has improved adhesion and a reduced dielectric constant with comparable current leakage compared to capping layers of the prior art.

Abstract: The proposed invention is related to a method for forming a gate with metal silicide. In short, the proposed method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a polysilicon layer on the first dielectric layer; forming a metal silicide layer on the polysilicon layer; forming a second dielectric layer on the metal silicide layer; etching the second dielectric layer, the metal silicide layer, the polysilicon layer and the first dielectric layer to form a gate; performing a thermal nitridation process to form a metal nitride layer on the sidewall of the metal silicide layer; and performing a thermal oxidation process to eliminate edge defects.

Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions.

Abstract: A structure and method of fabricating an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

Abstract: This invention provides a method and apparatus for depositing a silicon oxide film over an antireflective layer to reduce footing experienced in the a subsequently applied photoresist layer without substantially altering the optical qualities of the antireflective layer. The invention thereby provides more accurate etching of underlying layers during patterning operations. The invention is also capable of providing more accurate patterning of thin films by reducing inaccuracies caused by excessive etching of photoresist during patterning. Additionally, the film of the present invention may be patterned and used as a mask in the patterning of underlying layers.

Abstract: Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then, an immersion plating process is used to replace the atoms of the sacrificial layer with atoms of a desired metal, such as platinum, thereby creating a metal cap isolated within the via. The advantages of planarization to isolate material within recessed via are thus obtained without having to planarize or otherwise etch the desired metal. The cap layer can be further reacted to form a barrier compound prior to forming a capacitor over the plug. Advantageously, the plug structure resists oxidation during fabrication of overlying capacitors that incorporate high dielectric constant materials.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt silicide from the layer of cobalt and the silicon. Further, a layer of cobalt or nickel may be formed over a titanium film on a surface including silicon. The titanium film is formed in an atmosphere including at least one of nitrogen and oxygen and a thermal treatment is performed for reversal and silicidation of the titanium film and the layer of cobalt or nickel to form cobalt silicide or cobalt nickel. The methods may be used for silicidation of a contact area, in forming a polycide line, or in use for other metal silicidation applications.

Abstract: A method for manufacturing a micromechanical component, in particular, a surface-micromechanical yaw sensor, includes the following steps: providing a substrate having a front side and a back side; forming a micromechanical pattern on the front side; applying a protective layer on the micromechanical pattern on the front side; forming a micromechanical pattern on the back side, a resting on the micromechanical pattern on the front side taking place at least temporarily; removing the protective layer on the front side; and optionally further processing the micromechanical pattern on the front side and/or the micromechanical pattern on the back side.

Abstract: The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus utilizing the same memory by generating the data cell region with a process that is different from the process used to generate the system region to control the data cells.

Abstract: Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on the semiconductor substrate, and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.

Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). A second disposable gate structure (28) of the second, complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A capping layer (60) may be formed over the first and second regions (16, 18) including the first and second disposable gate structures (26, 28). A portion (62, 64) of the first and second disposable gate structures (26, 28) may be exposed through the capping layer (60). A second disposable gate cap (66) may be formed over the exposed portion (64) of the second disposable gate structure (28) and at least part of the first disposable gate structure (26) removed.

Abstract: An electrically conductive apparatus includes, a) an electrically non-conducting substrate, the substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; b) a capping layer of first electrically conductive material coating the elevated surface only portions of the step wall, the capping layer having outer top and outer side portions; and c) a conductive trace of second electrically conductive material which is different from the first electrically conductive material; the conductive trace overlying the substrate, portions of the step wall not covered by the capping layer, and the outer side portions of the capping layer. Methods are disclosed for producing such a construction, for forming an electrically conductive projection outwardly extending from a substrate, and for providing an electrical interconnection between adjacent different elevation areas on a substrate.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: A method for use in patterning a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed on the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.

Abstract: A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passivation film), covering the silicon substrate and serving as an uppermost layer, is formed on an upper portion of the silicon substrate. Thereafter, annealing is performed to discharge water in the BPSG film to an outer portion of an LSI. The annealing is performed under a condition satisfying the following equation of t≧7.86×10−11×L2×exp (9115/T) where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature). Thereby, an amount of electronic trap in a gate oxide film of the transistor can be reduced.

Abstract: A method of depositing a dielectric film on a substrate in a process chamber of an inductively coupled plasma-enhanced chemical vapor deposition reactor. Gap filling between electrically conductive lines on a semiconductor substrate and depositing a cap layer are achieved. Films having significantly improved physical characteristics including reduced film stress are produced by heating the substrate holder on which the substrate is positioned in the process chamber.