Abstract: An organic layer forming apparatus includes a donor film supply part configured to supply a donor film. The donor film includes a base substrate, a transfer layer disposed on the base substrate, and a protective film disposed on the transfer layer. The apparatus also includes a protective film withdrawal part configured to remove the protective film from the donor film, a transfer printing process part configured to transfer the transfer layer of the donor film onto a transfer substrate to form a first organic layer, a first deposition part configured to form a second organic layer on the transfer layer through a first deposition process, a second deposition part configured to form a third organic layer on the transfer layer through a second deposition process, and a donor film withdrawal part configured to withdraw the donor film.

Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Abstract: A semiconductor processing apparatus includes a reaction chamber, a loading chamber, a movable support, a drive mechanism, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable support is configured to hold a workpiece. The drive mechanism is configured to move a workpiece held on the support towards the opening of the baseplate into a processing position. The control system is configured to create a positive pressure gradient between the reaction chamber and the loading chamber while the workpiece support is in motion. Purge gases flow from the reaction chamber into the loading chamber while the workpiece support is in motion. The control system is configured to create a negative pressure gradient between the reaction chamber and the loading chamber while the workpiece is being processed.

Abstract: Methods for processing substrates in twin chamber processing systems having first and second process chambers and shared processing resources are provided herein. In some embodiments, a method may include providing a substrate to the first process chamber of the twin chamber processing system, wherein the first process chamber has a first processing volume that is independent from a second processing volume of the second process chamber; providing one or more processing resources from the shared processing resources to only the first processing volume of the first process chamber; and performing a process on the substrate in the first process chamber.

Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.

Abstract: Methods of forming contacts for back-contact solar cells are described. In one embodiment, a method includes forming a thin dielectric layer on a substrate, forming a polysilicon layer on the thin dielectric layer, forming and patterning a solid-state p-type dopant source on the polysilicon layer, forming an n-type dopant source layer over exposed regions of the polysilicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped polysilicon regions among a plurality of p-type doped polysilicon regions.

Abstract: A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring.

Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The bands or chains are driven synchronously at ultra-low tension by a pin drive roller or sprocket at either the inlet or outlet end of the furnace, with appropriate tensioning systems disposed in the return path. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces.

Abstract: An underlying film forming section forming an underlying film on a semiconductor substrate is provided to an apparatus of fabricating a semiconductor device. The apparatus is further provided with a cooling section cooling the semiconductor substrate and a plasma nitriding section introducing active nitrogen into the underlying film while keeping the temperature of the semiconductor substrate cooled by the cooling section at 100° C. or below. The semiconductor substrate is cooled by using liquid nitrogen or liquid helium, and by cooling a stage on which the semiconductor substrate is placed.

Abstract: An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: A liquid film applicator means can apply a photosensitive lyophobic film 18 to a substrate 16. An exposure unit 10 is placed on the back side of the substrate and forms the lyophobic film applied on the substrate into a pattern in alignment with gate electrodes 13. A dropping unit 55 drops a test liquid to a surface of the substrate having a pattern of the lyophobic film formed by the exposure means. A measuring means 58 detects the droplet dropped by the dropping unit. A determining means determines whether the pattern of the lyophobic film formed by the exposure means is proper or not based on the droplet detected by the detecting means.

Abstract: In a crystallization process of an amorphous semiconductor film, a first polycrystalline semiconductor film, in which amorphous regions are dotted within the continuous crystal region, is obtained by performing heat treatment after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. At this point, the amorphous regions are kept within a predetermined range. A laser beam having a wave length region, which can give more energy to the amorphous region than to the crystal region, is irradiated to the first polycrystalline semiconductor film, it is possible to crystallize the amorphous region without destroying the crystal region. If a TFT is manufactured based on a second polycrystalline semiconductor film, which is obtained through the above-mentioned crystallization processes, the TFT with high electric characteristics and less fluctuation can be obtained.

Abstract: Method for producing a metal silicon (oxy)nitride by introducing a carbon-free silicon source (for example, (SiH3)3N), a metal precursor with the general formula MXn (for example, Hf(NEt2)4), and an oxidizing agent (for example, O2) into a CVD chamber and reacting same at the surface of a substrate. MsiN, MSIo and/or MSiON films may be obtained. These films are useful are useful as high k dielectrics films.

Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.

Abstract: A mounting zone and a reflow zone are arranged in parallel between a loader and an unloader, and mounting and reflow processes are performed simultaneously.

Abstract: A serial thermal processing arrangement for treating a wafer of semiconductor material, the steps including: loading the wafer into a chamber at an initial station and purging the chamber with nitrogen gas; introducing formic acid vapor and nitrogen and heating the wafer at ambient; introducing a vacuum and heat onto the wafer; introducing formic acid vapor and nitrogen, heating the wafer at ambient; introducing nitrogen gas, and cooling the wafer at ambient; and lastly, unloading the wafer from its chamber.

Abstract: For a surface processing apparatus using a plasma, a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas. A mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of a vacuum chamber. In addition, the removal of the mask material is performed under low pressure, and in the subsequent step to a step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.

Abstract: A method for configuring a plasma cluster tool is disclosed. The method includes generating a key file from option specifications, the key file encapsulating configuration restrictions specifically imposed on the plasma cluster tool. The method also includes generating at least one system-wide configuration file and at least one component-level configuration file using the key file. The method additionally includes generating run-time executable objects from a database of option definition files, the at least one system-wide configuration file and the at least one component-level configuration file. Furthermore, the method includes employing the run-time executable objects to configure the plasma cluster tool.

Abstract: A substrate transfer controlling apparatus can easily maximize throughput of a substrate processing apparatus such as a semiconductor fabrication apparatus, and can satisfy a demand for immediacy of actions of a transfer device. The substrate transfer controlling apparatus includes an input device for inputting times required for actions of transfer devices and times required to process substrates in processing devices, and a schedule calculator for calculating execution times of actions of the transfer devices for allowing a time when a final one of the substrates to be processed is fully processed and returned from the substrate processing apparatus to be earliest, based on a predetermined conditional formula including, as parameters, the inputted times. The substrate transfer controlling apparatus further includes an action commander for instructing corresponding transfer devices to perform actions at calculated execution times of the actions of the transfer devices.

Abstract: In order to achieve an isolation trench formation process according to the present invention in which the structure of a silicon nitride film liner can be easily controlled and to allow both of reduction of the device feature length and reduction in stress occurring in an isolation trench, the silicon nitride film liner is first deposited on the inner wall of the trench formed on a silicon substrate. The upper surface of a first embedded insulator film for filling the inside of the trench is recessed downward so as to expose an upper end portion of the silicon nitride film liner. Next, the exposed portion of the silicon nitride film liner is converted into non-silicon-nitride type insulator film, such as a silicon oxide film. A second embedded insulator film is then deposited on the upper portion of the first embedded insulator film, and the deposited surface is then planarized.

Abstract: A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and forming the layer of photoresist 28 over the layer of pre-wet solvent 52. Also, a layer of photoresist 28 formed by this method.

Abstract: A method for making a semiconductor light emitting device comprises the steps of: (a) forming a plurality of buttresses on a first supporting substrate such that the buttresses are separated by a plurality of intercommunicated spaces thereamong; (b) forming a base layer on top end portions of the buttresses in such a manner that the top end portions of the buttresses are enclosed in the base layer; (c) forming a multi-layered light-emitting structure on the base layer; (d) attaching a second supporting substrate to the light-emitting structure; and (e) separating the first supporting substrate from the light-emitting structure by destroying the buttresses.

Abstract: A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a specific process variation, by using a transistor of which a channel width and a gate length are set to an unbalanced state, and outputs the predetermined value.

Abstract: An apparatus for thermally processing a microelectronic workpiece is provided. The apparatus comprises a rotatable carousel assembly configured to support at least one workpiece. A driver is coupled to the carousel assembly and rotates the carousel assembly, moving the workpiece between a loading station, a heating station and a cooling station. The loading, heating and cooling stations are radially positioned and approximately equally spaced about a center axis of the carousel assembly. The heating station includes a heating element and an actuator for moving the heating element into thermal engagement with the workpiece in the heating station. The cooling station includes a cooling element and an actuator for moving the cooling element into thermal engagement with the workpiece in the cooling station. A process fluid distribution manifold for delivering process fluid to the workpieces at each station extends through a central opening in the carousel assembly.

Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.

Abstract: A vapor deposition shadow mask system includes a number of series connected vacuum vessels each having a material deposition source and shadow mask positioned therein. A substrate is translated along a path that has a longitudinal axis that extends through the vacuum vessels. Centers of shadow masks in first and second vacuum vessels are offset laterally on opposite sides of the longitudinal axis. The system is operative for depositing material on a second area of the substrate via the material deposition source and shadow mask in the second vacuum vessel in a manner that overlaps a portion of the material deposited on a first, adjacent area of the substrate via the material deposition source and shadow mask in the first vacuum vessel.

Abstract: A multi-chamber system for providing a process of a high degree of cleanliness in fabricating semiconductor devices such as semiconductor integrated circuits. The system comprises a plurality of vacuum apparatus (e.g., a film formation apparatus, an etching apparatus, a thermal processing apparatus, and a preliminary chamber) for fabrication of semiconductor devices. At least one of these vacuum apparatuses is a laser.

Abstract: This disclosure discusses the forming of gate dielectrics in semi conductor devices, and more specifically to forming thin high-k dielectric films on silicon substrates typically using chemical vapor deposition or atomic layer deposition processes. The current invention forms a high-k dielectric film in a single film-forming step using a vapor phase silicon precursor in conjunction with a liquid phase metal precursor, a nitrogen source and an oxygen source for the deposition of a metal silicon oxy nitride (MSiON) film of desired stochiometry. The vapor phase silicon precursor is not coordinated to a metal allowing independent control over feeding of the metal source and the silicon source. Thus, the M/Si ratio can be easily varied over a wide range.

Abstract: A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.

Abstract: A method of making a microelectronic device comprising: making a device B comprising providing a structure having a first bond pad, depositing a first electrically conductive material having a first reflow temperature over the first bond pad, and depositing a second electrically conductive material having a second reflow temperature over the first electrically conductive material, and wherein the second reflow temperature is less than the first reflow temperature, and heating the device to a temperature sufficient to reflow the second electrically conductive material but not the first electrically conductive material so that the second electrically conductive material encapsulates the first electrically conductive material to provide a first bump for making electrical connection to device B.

Abstract: A method and apparatus for processing a wafer is described. According to the present invention a wafer is placed on a substrate support. A liquid is then fed through a conduit having an output opening over the wafer. A gas is dissolved in the liquid prior to the liquid reaching the output over the wafer by flowing a gas into the conduit through a venturi opening formed in the conduit. The liquid with dissolved gas is then fed through the opening and onto the wafer where it can be used to etch, clean, or rinse a wafer.

Abstract: A method and apparatus is provided for measuring multiple locations on a wafer for controlling a subsequent semiconductor processing step to achieve greater dimensional uniformity across that wafer. The method and apparatus maps a dimension of a feature at multiple locations to create a dimension map, transforms the dimension map into a processing parameter map, and uses the processing parameter map to tailor the subsequent processing step to that specific wafer. The wafer can also be measured after the processing to compare an actual outcome with the targeted outcome, and the difference can be used to refine the transformation from a dimension map to a processing parameter map for a subsequent wafer.

Abstract: A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.

Abstract: A wafer cluster tool is described which operates in a regular, periodic fashion. Embodiments of the invention have a periodicity of one sending period. The invention enables the determination of pick-up times for process chambers in the cluster tool, and embodiments of the invention allow the creation and maintenance of an updated timetable. The timetable indicates times when each of the process chambers is to be serviced. These values are updated as the process chambers receive new wafers. Robots in the cluster tool may pre-position themselves in front of modules, or process chambers, to be served. Robot pre-positioning eliminates the wait time of individual modules beyond queue times which have been pre-determined for the modules. This renders the path of the individual robots pre-deterministic, and enables the cluster tool to utilize single gripper robots.

Abstract: A technique is disclosed that allows alignment of substrates on a run-to-run basis by using the position data of one or more previously aligned substrates to determine a setpoint of a pre-alignment process for one or more subsequent substrates. The setpoint may also be determined on the basis of a predefined characteristic of the substrates to be aligned.

Abstract: There is provided a method of manufacturing a substrate which has a partial insulating layer under a semiconductor layer. After the first substrate (10c) is formed, it is bonded to the second substrate (20), thereby forming a bonded substrate stack (30). Then, the bonded substrate stack (30) is split at a separation layer (15). In the step of forming the first substrate (10c), a partial insulating layer (12a) is formed on the substrate, a single-crystal Si layer (13) is grown in the partial insulating layer (12a), and a polysilicon layer (14) is grown on the partial insulating layer (12a). After that, ions are implanted into the substrate, thereby forming the separation layer (15) inside the substrate.

Abstract: An electronic device is formed from electronic elements deposited on a substrate. The electronic elements are deposited on the substrate by advancing the substrate through a plurality of deposition vacuum vessels, with each deposition vacuum vessel having at least one material deposition source and a shadowmask positioned therein. The material from at least one material deposition source positioned in each deposition vacuum vessel is deposited on the substrate through the shadowmask positioned in the deposition vacuum vessel to form on the substrate a circuit comprised of an array of electronic elements. The circuit is formed solely by the successive deposition of materials on the substrate.

Abstract: A system and method for processing a workpiece, includes workpiece processors. A robot is moveable within an enclosure to load and unload workpieces into and out of the processors. A processor includes an upper rotor having a central air flow opening. The upper rotor is magnetically driven into engagement with a lower rotor to form a workpiece processing chamber. A moveable drain mechanism aligns different drain paths with the processing chamber so that different processing fluids may be removed from the processing chamber via different drain paths. A moveable nozzle positioned in the air flow opening distributes processing fluid to the workpiece. The processing fluid is distributed across the workpiece surface, via centrifugal force generated by spinning the processing chamber, and removed from the processing chamber via the moveable drain mechanism.

Abstract: A system for thinning a layer on a substrate without damaging a delicate underlying layer in the substrate. The system includes means for mechanically eroding the layer on the substrate, and means for electropolishing the layer on the substrate. In this manner, portions of the layer that cannot be removed by electropolishing can be removed by the mechanical erosion. However, electropolishing can preferentially be used on some portions of the layer so that unnecessary mechanical stresses can be avoided. Thus, the system imparts less mechanical stress to the substrate during the removal of the layer, and the delicate underlying layer receives less damage during the process, and preferably no damage whatsoever.

Abstract: In a method for calculating a time-related fill level signal (h(t)) from a sensor signal (s(t)) of a fill level sensor for detection of the fill level of a liquid, the time-related fill level signal (h(t)) is calculated as a function of the sensor signal (s(t)) and the modeled runoff behavior of the liquid on the fill level sensor.

Abstract: A process for fabricating a semiconductor device having a buried layer comprises the steps of implanting an impurity ion into where the buried layer to be formed in a substrate, providing the substrate inside a reactor furnace, preparing a nonoxidizing atmosphere inside of the reactor furnace, annealing the substrate to activate and diffuse the implanted impurity ion region while increasing inside temperature of the reactor furnace up to a first temperature, and shifting the inside temperature of the reactor furnace from the first temperature to a second temperature in which a epitaxial crystal starts to grow and introducing a epitaxial growth gas into the reactor furnace to grow an epitaxial layer on a surface of the substrate.

Abstract: A method for detecting the endpoint of a chemical mechanical polishing (CMP) process uses the slope variation of temperature difference of polishing pad. The method combines temperature measurement at polishing pad and atmosphere, and numerical analysis to figure out the curve of temperature difference variation versus polishing time. The endpoint of CMP is determined by the change of the slope of the curve. The method allows endpoint to be detected in-situ at the polishing apparatus, without stopping polishing process.

Abstract: A method of manufacturing a semiconductor device, which method comprises the step of epitaxially growing a stack comprising an n-type doped layer of a semiconductor material followed by at least one further layer of a semiconductor material, the stack being grown in one continuous cycle.

Abstract: The invention is a method of determining a set temperature profile for a method of controlling respective substrate temperatures of a plurality of groups in accordance with respective corresponding set temperature profiles, in a method of heat processing a plurality of substrates that are classified into the plurality of groups.

Abstract: The conveyance of wafers in bays (equipment groups) of a clean room is performed by RGVs (Rail Guided Vehicles) that linearly travel on conveying rails (3) laid on the floor of the clean room at high speed. A structure is adopted wherein a conveying area over which the RGV travels, is separated from a human working area by a compartment (partition) (4), and a human does not enter the conveying area upon operation of a line.

Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.

Abstract: A method of securing a substrate in a semiconductor processing machine. The method includes moving latch bodies between latched and unlatched positions while permitting contact between a clamping member of each latch body and the substrate only if the latch bodies are substantially in the latched position. In the latched position, the clamping members apply a clamping force effective to secure the substrate. Generally, contact is prevented by engagement between a support member and an ramp that is inclined such that the clamping member descends toward the substrate as the latch body moves from the unlatched position to the latched position and only contacts the substrate as the latched position is established.

Abstract: By conducting etching treatment using at least two steps with different compositions of gases for each step, and at least one step comprising using a gas capable of decomposing and vaporizing etching products in an etching apparatus continuously, semicondictor devices can be produced with high productivity, low contaminant and good reproducibility of treatment state.