Utilizing Cluster Apparatus Patents (Class 438/908)
  • Patent number: 10747210
    Abstract: A system includes an interface and a controller. The interface is configured to receive a state of a substrate processing tool comprising a plurality of process modules configured to process a substrate. The controller is configured to correlate the state with an input previously received by the substrate processing tool from the interface based on the state and to generate an output to control the substrate processing tool based on the correlation.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 18, 2020
    Assignee: Lam Research Corporation
    Inventors: Rainer Unterguggenberger, Henry Chan, Chung-Ho Huang, Vincent Wong, David Hemker
  • Patent number: 10510566
    Abstract: Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Horng Lin, Tsung-Hsun Yu, Victor Y. Lu
  • Patent number: 9618930
    Abstract: Due to the trend of using larger wafer diameter and smaller lot size, cluster tools need to switch from processing one lot of wafers to another frequently. It leads to more transient periods in wafer fabrication. Their efficient scheduling and control problems become more and more important. It becomes difficult to solve such problems, especially when wafer residency time constraints must be considered. This work develops a Petri net model to describe the behavior during the start-up transient processes of a single-arm cluster tool. Then, based on the model, for the case that the difference of workloads among the steps is not too large and can be properly balanced, a scheduling algorithm to find an optimal feasible schedule for the start-up process is given. For other cases schedulable at the steady state, a linear programming model is developed to find an optimal feasible schedule for the start-up process.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: April 11, 2017
    Assignee: Macau University of Science and Technology
    Inventors: Naiqi Wu, Yan Qiao, Mengchu Zhou
  • Patent number: 8778787
    Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 15, 2014
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8691019
    Abstract: A process for cleaning a compound semiconductor wafer; the compound semiconductor wafer comprises, taking gallium arsenide (GaAs) as a representative, a group III-V compound semiconductor wafer. The process comprises the following steps: 1) treating the wafer with a mixture of dilute ammonia, hydrogen peroxide and water at a temperature not higher than 20° C.; 2) washing the wafer with deionized water; 3) treating the wafer with an oxidant; 4) washing the wafer with deionized water; 5) treating the wafer with a dilute acid solution or a dilute alkali solution; 6) washing the wafer with deionized water; and 7) drying the resulting wafer. The process can improve the cleanliness, micro-roughness and uniformity of the wafer surface.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: April 8, 2014
    Assignee: Beijing Tongmei Xtal Technology Co., Ltd.
    Inventors: Diansheng Ren, Qinghui Liu
  • Patent number: 8492253
    Abstract: Methods of forming contacts for back-contact solar cells are described. In one embodiment, a method includes forming a thin dielectric layer on a substrate, forming a polysilicon layer on the thin dielectric layer, forming and patterning a solid-state p-type dopant source on the polysilicon layer, forming an n-type dopant source layer over exposed regions of the polysilicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped polysilicon regions among a plurality of p-type doped polysilicon regions.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 23, 2013
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8278135
    Abstract: There is provided a film formation apparatus which is capable of forming an EL layer using an EL material with high purity. The EL material is purified by sublimation immediately before film formation in the film formation apparatus, to thereby remove oxygen, water, and another impurity, which are included in the EL material. Also, when film formation is performed using the EL material (high purity EL material) obtained by purifying with sublimation as an evaporation source, a high purity EL layer can be formed.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshimitsu Konuma, Takeshi Nishi
  • Patent number: 8248584
    Abstract: An apparatus comprises a grouping unit dividing substrates into groups, and determining reference and non-reference substrates for each group, a measurement unit measuring a first number of points for the reference substrate, and measuring a second number, smaller than the first number, of points for the non-reference substrate, a correction value determining unit determining a first correction value to position the reference substrate, and a second correction value to position the non-reference substrate, and an exposure unit exposing the reference substrate by positioning it based on the first correction value, and exposing the non-reference substrate by positioning it based on the second correction value, the correction value determining unit determining the first correction value based on the measurement of the reference substrate, and determining the second correction value based on the measurement of the non-reference substrate, and the measurement of the reference substrate or the first correction valu
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 21, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masataro Shiroiwa, Hiroki Suzukawa
  • Patent number: 8227355
    Abstract: An underlying film forming section forming an underlying film on a semiconductor substrate is provided to an apparatus of fabricating a semiconductor device. The apparatus is further provided with a cooling section cooling the semiconductor substrate and a plasma nitriding section introducing active nitrogen into the underlying film while keeping the temperature of the semiconductor substrate cooled by the cooling section at 100° C. or below. The semiconductor substrate is cooled by using liquid nitrogen or liquid helium, and by cooling a stage on which the semiconductor substrate is placed.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mitsuaki Hori
  • Patent number: 8207069
    Abstract: An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: June 26, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Kurt H. Weiner, Tony P. Chiang, Aaron Francis, John Schmidt
  • Patent number: 8110509
    Abstract: A manufacturing apparatus is provided, which can improve a utilization efficiency of an evaporation material, reduce manufacturing costs of a light emitting device having an organic light emitting element, and shorten manufacturing time necessary to manufacture a light emitting device. According to the present invention, a multi-chamber manufacturing apparatus having plural film forming chambers includes a first film forming chamber for subjecting a first substrate to evaporation and a second film forming chamber for subjecting a second substrate to evaporation. In each film forming chamber, plural organic compound layers are laminated, thereby improving the throughput. Further, it is possible that the respective substrates in the plural film forming chambers are subjected to evaporation in the same manner in parallel, while another film forming chamber undergoes cleaning.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: February 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakazu Murakami
  • Patent number: 8087380
    Abstract: A plurality of chamber are arranged about a transport chamber. The linear transport chamber may include a linear track supporting robot arms. The robot arms transport substrates to and from the chambers. Each chamber includes a plurality of evaporators, each controlled independently. Each substrate positioned in the chamber is coated from a plurality of the evaporators, such that by controlling the operation of each evaporator independently the formation of the layers and the concentration gradient of each layer can be precisely controlled.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: January 3, 2012
    Assignee: Intevac, Inc.
    Inventors: Terry Bluck, Michael S. Barnes, Kevin P. Fairbairn
  • Patent number: 8034190
    Abstract: A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, and an interface block. An exposure device is arranged adjacent to the interface block. The interface block comprises washing processing units and an interface transport mechanism. Before a substrate is subjected to exposure processing by the exposure device, the substrate is transported to a washing processing unit by the interface transport mechanism. The substrate is washed and dried by the washing processing unit.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: October 11, 2011
    Assignee: Sokudo Co., Ltd.
    Inventors: Shuichi Yasuda, Masashi Kanaoka, Koji Kaneyama, Tadashi Miyagi, Kasuhito Shigemori, Toru Asano, Akihiro Hisai, Hiroshi Kobayashi, Tsuyoshi Okumura
  • Patent number: 7993820
    Abstract: A liquid film applicator means can apply a photosensitive lyophobic film 18 to a substrate 16. An exposure unit 10 is placed on the back side of the substrate and forms the lyophobic film applied on the substrate into a pattern in alignment with gate electrodes 13. A dropping unit 55 drops a test liquid to a surface of the substrate having a pattern of the lyophobic film formed by the exposure means. A measuring means 58 detects the droplet dropped by the dropping unit. A determining means determines whether the pattern of the lyophobic film formed by the exposure means is proper or not based on the droplet detected by the detecting means.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Inoue, Masahiko Ando, Shuji Imazeki
  • Patent number: 7947584
    Abstract: The present invention generally relates to a thermal processing apparatus and method that permits a user to index one or more preselected light sources capable of emitting one or more wavelengths to a collimator. Multiple light sources may permit a single apparatus to have the capability of emitting multiple, preselected wavelengths. The multiple light sources permit the user to utilize multiple wavelengths simultaneously to approximate “white light”. One or more of a frequency, intensity, and time of exposure may be selected for the wavelength to be emitted. Thus, the capabilities of the apparatus and method are flexible to meet the needs of the user.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: May 24, 2011
    Assignee: Applied Materials, Inc.
    Inventor: Stephen Moffatt
  • Patent number: 7888217
    Abstract: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: February 15, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Thai Cheng Chua, Cory Czarnik, Christopher Sean Olsen, Khaled Z. Ahmed, Philip Allan Kraus
  • Patent number: 7826032
    Abstract: A circulation system for a high refractive index liquid includes a first collecting section configured to collect a high refractive index liquid used in an immersion light exposure section; a first supply section configured to supply the high refractive index liquid collected in the first collecting section to a cleaning section as a cleaning liquid; a second collecting section configured to collect the high refractive index liquid used in the cleaning section; and a second supply section configured to supply the high refractive index liquid collected in the second collecting section to the immersion light exposure section, wherein the high refractive index liquid is circulated between the immersion light exposure section and the cleaning section.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 2, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Taro Yamamoto, Hitoshi Kosugi, Yoshiaki Yamada, Yasuhito Saiga
  • Patent number: 7763503
    Abstract: In a semiconductor device manufacturing process, a gate insulating film forming step, an amorphous semiconductor film forming step, and an insulating film forming step are continuously performed without taking out the substrate to the atmosphere.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: July 27, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Takeshi Fukada
  • Patent number: 7682987
    Abstract: Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: March 23, 2010
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Kazuhiro Kimura, Yasuhiro Megawa
  • Patent number: 7572686
    Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 11, 2009
    Assignee: Eastman Kodak Company
    Inventors: David H. Levy, Roger S. Kerr, Jeffrey T. Carey
  • Patent number: 7432177
    Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Applied Materials, Inc.
    Inventors: James S. Papanu, Han-Wen Chen, Brian J. Brown, Steven Verhaverbeke
  • Patent number: 7358175
    Abstract: A serial thermal processing arrangement for treating a wafer of semiconductor material, the steps including: loading the wafer into a chamber at an initial station and purging the chamber with nitrogen gas; introducing formic acid vapor and nitrogen and heating the wafer at ambient; introducing a vacuum and heat onto the wafer; introducing formic acid vapor and nitrogen, heating the wafer at ambient; introducing nitrogen gas, and cooling the wafer at ambient; and lastly, unloading the wafer from its chamber.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: April 15, 2008
    Inventors: Jian Zhang, Chunghsin Lee
  • Patent number: 7353379
    Abstract: A method for configuring a plasma cluster tool is disclosed. The method includes generating a key file from option specifications, the key file encapsulating configuration restrictions specifically imposed on the plasma cluster tool. The method also includes generating at least one system-wide configuration file and at least one component-level configuration file using the key file. The method additionally includes generating run-time executable objects from a database of option definition files, the at least one system-wide configuration file and the at least one component-level configuration file. Furthermore, the method includes employing the run-time executable objects to configure the plasma cluster tool.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 1, 2008
    Assignee: Lam Research Corporation
    Inventors: Chung-Ho Huang, Shih-Jeun Fan, Chin-Chuan Chang
  • Patent number: 7313452
    Abstract: A substrate transfer controlling apparatus can easily maximize throughput of a substrate processing apparatus such as a semiconductor fabrication apparatus, and can satisfy a demand for immediacy of actions of a transfer device. The substrate transfer controlling apparatus includes an input device for inputting times required for actions of transfer devices and times required to process substrates in processing devices, and a schedule calculator for calculating execution times of actions of the transfer devices for allowing a time when a final one of the substrates to be processed is fully processed and returned from the substrate processing apparatus to be earliest, based on a predetermined conditional formula including, as parameters, the inputted times. The substrate transfer controlling apparatus further includes an action commander for instructing corresponding transfer devices to perform actions at calculated execution times of the actions of the transfer devices.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: December 25, 2007
    Assignee: Ebara Corporation
    Inventors: Yoichi Kobayashi, Yasumasa Hiroo, Tsuyoshi Ohashi
  • Patent number: 7144813
    Abstract: An apparatus for thermally processing a microelectronic workpiece is provided. The apparatus comprises a rotatable carousel assembly configured to support at least one workpiece. A driver is coupled to the carousel assembly and rotates the carousel assembly, moving the workpiece between a loading station, a heating station and a cooling station. The loading, heating and cooling stations are radially positioned and approximately equally spaced about a center axis of the carousel assembly. The heating station includes a heating element and an actuator for moving the heating element into thermal engagement with the workpiece in the heating station. The cooling station includes a cooling element and an actuator for moving the cooling element into thermal engagement with the workpiece in the cooling station. A process fluid distribution manifold for delivering process fluid to the workpieces at each station extends through a central opening in the carousel assembly.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: December 5, 2006
    Assignee: Semitool, Inc.
    Inventors: Paul Zachary Wirth, Jeffry Alan Davis
  • Patent number: 7132016
    Abstract: A vapor deposition shadow mask system includes a number of series connected vacuum vessels each having a material deposition source and shadow mask positioned therein. A substrate is translated along a path that has a longitudinal axis that extends through the vacuum vessels. Centers of shadow masks in first and second vacuum vessels are offset laterally on opposite sides of the longitudinal axis. The system is operative for depositing material on a second area of the substrate via the material deposition source and shadow mask in the second vacuum vessel in a manner that overlaps a portion of the material deposited on a first, adjacent area of the substrate via the material deposition source and shadow mask in the first vacuum vessel.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: November 7, 2006
    Assignee: Advantech Global, Ltd
    Inventors: Thomas Peter Brody, Paul R. Malmberg
  • Patent number: 7097712
    Abstract: A multi-chamber system for providing a process of a high degree of cleanliness in fabricating semiconductor devices such as semiconductor integrated circuits. The system comprises a plurality of vacuum apparatus (e.g., a film formation apparatus, an etching apparatus, a thermal processing apparatus, and a preliminary chamber) for fabrication of semiconductor devices. At least one of these vacuum apparatuses is a laser.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: August 29, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Takenouchi, Yasuhiko Takemura
  • Patent number: 7049154
    Abstract: A vapor phase growth method for growing a semiconductor single crystal thin film on a front surface of a semiconductor single crystal substrate (1) while introducing gas into a reaction chamber (11), has a step of performing heating output power control in a gas introduction region (R1) according to a temperature detected in a region other than the gas introduction region (R1) in the reaction chamber (11).
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 23, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Hisashi Kashino
  • Patent number: 6952622
    Abstract: A wafer cluster tool is described which operates in a regular, periodic fashion. Embodiments of the invention have a periodicity of one sending period. The invention enables the determination of pick-up times for process chambers in the cluster tool, and embodiments of the invention allow the creation and maintenance of an updated timetable. The timetable indicates times when each of the process chambers is to be serviced. These values are updated as the process chambers receive new wafers. Robots in the cluster tool may pre-position themselves in front of modules, or process chambers, to be served. Robot pre-positioning eliminates the wait time of individual modules beyond queue times which have been pre-determined for the modules. This renders the path of the individual robots pre-deterministic, and enables the cluster tool to utilize single gripper robots.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: October 4, 2005
    Assignee: ASML Holding N.V.
    Inventors: Dikran Babikian, Hilario Oh
  • Patent number: 6897100
    Abstract: A multi-chamber system for providing a process of a high degree of cleanliness in fabricating semiconductor devices such as semiconductor integrated circuits. The system comprises a plurality of vacuum apparatus (e.g., a film formation apparatus, an etching apparatus, a thermal processing apparatus, and a preliminary chamber) for fabrication of semiconductor devices. At least one of these vacuum apparatuses is a laser.
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: May 24, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Shimada, Akira Takenouchi, Yasuhiko Takemura
  • Patent number: 6865437
    Abstract: A wafer cluster tool is described which operates in a regular, periodic fashion. Embodiments of the invention have a periodicity of one sending period. The invention enables the determination of pick-up times for process chambers in the cluster tool, and embodiments of the invention allow the creation and maintenance of an updated timetable. The timetable indicates times when each of the process chambers is to be serviced. These values are updated as the process chambers receive new wafers. Robots in the cluster tool may pre-position themselves in front of modules, or process chambers, to be served. Robot pre-positioning eliminates the wait time of individual modules beyond queue times which have been pre-determined for the modules. This renders the path of the individual robots pre-deterministic, and enables the cluster tool to utilize single gripper robots.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: March 8, 2005
    Assignee: ASML Holdings N.V.
    Inventors: Dikran Babikian, Hilario Oh
  • Patent number: 6843809
    Abstract: A vacuum/purge operation of a loadlock chamber prevents an eddy phenomenon from occurring in the chamber and thereby prevents wafers from being polluted and damaged by particles in the chamber. A vacuum pump for providing the loadlock chamber with vacuum pressure, and a gas supply for providing the chamber with purge gas are connected to the loadlock chamber by an exhaust line and a gas supply line, respectively. At least one control valve is installed in each of the lines. At the time the state of pressure in the loadlock chamber is to be changed, the loadlock chamber is provided with both the vacuum pressure and the purge gas at rates that are inter-dependent to establish a flow of gases towards and into the exhaust line. Then, the supplying of one of the vacuum pressure and the purge gas is gradually reduced and cut off.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: January 18, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Jin Park
  • Publication number: 20040219772
    Abstract: An apparatus for manufacturing a semiconductor includes a polyhedral transfer chamber, a first process module for forming a gate dielectric layer by ALD, and a second process module for thermally treating the gate dielectric layer. The first process module is in communication with a first side of the transfer chamber. The second process module in communication with a second side of the transfer chamber. The apparatus further includes at least one load-lock chamber in communication with a third side of the transfer chamber.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 4, 2004
    Inventors: Young-Sub You, Jae-Woong Kim
  • Patent number: 6797617
    Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: September 28, 2004
    Assignee: ASM America, Inc.
    Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylhä
  • Patent number: 6776805
    Abstract: A semiconductor manufacturing method whereby reactive gas processing such as selective epitaxial growth can be carried out with high precision by correctly adjusting conditions during processing is performed by a semiconductor manufacturing apparatus which can restrict increases in the moisture content, prevent heavy metal pollution and the like, and investigate the correlation between moisture content in the process chamber and outside regions. The moisture content in a reaction chamber and in a gas discharge system of the reaction chamber are measured when a substrate is provided, and the conditions for reactive gas processing are adjusted based on the moisture content.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: August 17, 2004
    Assignees: Mitsubishi Materials Silicon Corporation, Nippon Sanso Corporation
    Inventors: Hiroyuki Hasegawa, Tomonori Yamaoka, Yoshio Ishihara, Hiroshi Masusaki
  • Patent number: 6772029
    Abstract: The present invention provides a substrate transfer controlling apparatus which can easily maximize the throughput of a substrate processing apparatus such as a semiconductor fabrication apparatus, and can satisfy a demand for immediacy of actions of a transfer device. The substrate transfer controlling apparatus comprises an input device (12) for inputting times required for actions of transfer devices (1a through 1c) and times required to process substrates in processing devices (3a through 9d), and a schedule calculator (21) for calculating execution times of actions of the transfer devices (1a through 1c) for allowing the time when a final one of the substrates to be processed is fully processed and returned from the substrate processing apparatus to be earliest, based on a predetermined conditional formula including, as parameters, the inputted times.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 3, 2004
    Assignee: Ebara Corporation
    Inventors: Yoichi Kobayashi, Yasumasa Hiroo, Tsuyoshi Ohashi
  • Patent number: 6750155
    Abstract: A chamber for transitioning a semiconductor substrate between modules operating at different pressures is provided. The chamber includes a base defining an outlet. The outlet permits removal of an atmosphere within the chamber to create a vacuum. A substrate support for supporting a semiconductor substrate within the chamber is included. A chamber top having an inlet is included. The inlet is configured to allow for the introduction of a gas into the chamber to displace moisture in a region defined above the substrate support. Sidewalls extending from the base to the chamber top are included. The sidewalls include access ports for entry and exit of a semiconductor substrate from the chamber. A method for conditioning an environment above a region of a semiconductor substrate within a pressure varying interface is also provided.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: June 15, 2004
    Assignee: Lam Research Corporation
    Inventors: Harlan I. Halsey, David E. Jacob
  • Patent number: 6743719
    Abstract: The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of copper oxide (105) over the deposited copper seed layer (110) by exposure to a substantially copper-free reducing agent solution (120), such that the copper oxide (105) is substantially converted to elemental copper, followed by electrochemical deposition of a second copper layer (125) over the copper seed layer (110). Such methods and resulting conductive structures thereof may be advantageously used in methods to make integrated circuits comprising interconnection metal lines.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: June 1, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Linlin Chen, Jiong-Ping Lu, Changfeng Xia
  • Publication number: 20040102059
    Abstract: A semiconductor-manufacturing tool has two load locks, one for semiconductor wafers entering the tool for processing and the other for wafers leaving the tool after being processed. The load locks are of a new generation capable of being evacuated or vented in shorter times than load locks of the prior art, and permit high throughput. The tool is associated with three atmospheric wafer-handling robots to obtain the high throughput permitted by the load locks. One robot transfers wafers to be processed from a supply to a wafer pre-aligner, another robot transfers wafers from the wafer pre-aligner to the load lock for wafers entering the tool, and the third transfers processed wafers from the load lock for wafers leaving the tool back to the supply.
    Type: Application
    Filed: November 25, 2002
    Publication date: May 27, 2004
    Inventor: John Dickinson
  • Patent number: 6693048
    Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Richard H. Lane, Phillip G. Wald
  • Patent number: 6686230
    Abstract: A process for providing a semiconducting device including the steps of depositing a semiconducting layer onto a substrate by means of heating a gas to a predetermined dissociation temperature so that the gas dissociates into fractions, whereby those fractions subsequently condense on the substrate to build up a semiconducting layer.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: February 3, 2004
    Assignee: Debye Instituut, Universiteit Utrecht
    Inventors: Hans Meiling, Rudolf Emmanuel Isidor Schropp
  • Patent number: 6672358
    Abstract: This invention is to provide a processing system suitable for manufacturing an SOI substrate. A processing system includes a scalar robot for conveying a bonded substrate stack held by a robot hand, and a centering apparatus, separating apparatus, inverting apparatus, and cleaning/drying apparatus disposed at substantially equidistant positions from a driving shaft of the scalar robot. When the robot hand is pivoted about the driving shaft in the horizontal plane and moved close to or away from the driving shaft, a bonded substrate stack or separated substrate is conveyed among the processing apparatuses.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: January 6, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazutaka Yanagita, Kazuaki Ohmi, Kiyofumi Sakaguchi
  • Patent number: 6657154
    Abstract: In a manufacturing technology for forming a thin film transistor comprising a laser irradiation step, objects of the present invention are to obtain a high performance and multifunction semiconductor manufacturing apparatus and thin film transistor manufacturing method. A silicon thin film 201 is formed on a glass substrate 202, and laser 203 is irradiated onto this thin film 201 whereby a re-crystallization film is obtained. This re-crystallization film undergoes a hydrogen plasma processing so that dangling-bonds of silicon are terminated. Moreover, a step for forming a silicon dioxide film 205 on the re-crystallization film is included. These steps are performed under the conditions that the glass substrate 202 is not exposed to the air and a processing temperature is 350° C. or less.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: December 2, 2003
    Assignee: NEC Corporation
    Inventors: Hiroshi Tanabe, Setsuo Kaneko
  • Publication number: 20030219977
    Abstract: In accordance with one aspect of the present invention, a method is provided for transporting a workpiece in a semiconductor processing apparatus comprising a transfer chamber, a process chamber, and a gate valve between the transfer chamber and the process chamber. The method comprises vacuum pumping the transfer chamber to achieve a first pressure in the transfer chamber and vacuum pumping the process chamber to achieve a second pressure in the process chamber. An inert gas is flowed into the transfer chamber and shut off in the process chamber. The transfer chamber is isolated from pumping, but pumping continues from the process chamber. The gate valve is opened after isolating the transfer chamber from pumping. The workpiece is then transferred between the transfer chamber and the process chamber. A definitive flow direction from transfer chamber to process chamber is thereby achieved, minimizing risk of back-diffusion.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 27, 2003
    Inventors: Christophe Pomarede, Eric J. Shero, Olli Jylha
  • Publication number: 20030170939
    Abstract: A method of manufacturing thin film field effect transistors is described. The channel region of the transistors is formed by depositing an amorphous semiconductor film in a first sputtering apparatus followed by thermal treatment for converting the amorphous phase to a polycrystalline phase. The gate insulating film is formed by depositing an oxide film in a second sputtering apparatus connected to the first apparatus through a gate valve. The sputtering for the deposition of the amorphous semiconductor film is carried out in an atmosphere comprising hydrogen in order to introduce hydrogen into the amorphous semiconductor film. On the other hand the gate insulating oxide film is deposited by sputtering in an atmosphere comprising oxygen.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 11, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Takashi Inushima, Takeshi Fukada
  • Patent number: 6602797
    Abstract: A wafer processing system occupies minimal floor space by using vertically mounted modules such as reactors, load locks, and cooling stations. Further saving in floor space is achieved by using a loading station which employs rotational motion to move a wafer carrier into a load lock. The wafer processing system includes a robot having extension, rotational, and vertical motion for accessing vertically mounted modules. The robot is internally cooled and has a heat resistant end-effector, making the robot compatible with high temperature semiconductor processing.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: August 5, 2003
    Assignees: WaferMasters, Inc., Tokyo Electron Limited
    Inventors: Hiromitsu Kuribayashi, Woo Sik Yoo
  • Patent number: 6573201
    Abstract: A method and apparatus can provide surface protection of substrates such as semiconductor wafers while they are being transported from one unit process to another unit process. The method comprises coating at least a part of a surface of the substrate with a coagulated film such as an ice film.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: June 3, 2003
    Assignee: Ebara Corporation
    Inventors: Naoaki Ogure, Hiroaki Inoue
  • Patent number: 6566175
    Abstract: A method of manufacturing thin film field effect transistors is described. The channel region of the transistors is formed by depositing an amorphous semiconductor film in a first sputtering apparatus followed by thermal treatment for converting the amorphous phase to a polycrystalline phase. The gate insulating film is formed by depositing an oxide film in a second sputtering apparatus connected to the first apparatus through a gate valve. The sputtering for the deposition of the amorphous semiconductor film is carried out in an atmosphere comprising hydrogen in order to introduce hydrogen into the amorphous semiconductor film. On the other hand the gate insulating oxide film is deposited by sputtering in an atmosphere comprising oxygen.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: May 20, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Takashi Inushima, Takeshi Fukada
  • Patent number: 6558962
    Abstract: A method of manufacturing semiconductor devices uses a wafer carrier having conditioning units to control internal conditions of the wafer carrier. The wafer carrier stores and carries wafers between manufacturing equipments used in manufacturing processes. For each of the manufacturing processes, the method includes placing the wafer carrier on a load port, transferring the wafers from the wafer carrier into the manufacturing equipment through the load port, changing operating conditions of the conditioning units according to the process or test being carried out by the manufacturing equipment, returning the wafers into the wafer carrier through the load port after the completion of the process or test, and operating the conditioning units according to the changed operating conditions to control the internal conditions until the wafer carrier is carried to the next manufacturing equipment.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: May 6, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhiro Nishiki
  • Patent number: RE38760
    Abstract: Oxides are etched with a halide-containing species and a low molecular weight organic molecule having a high vapor pressure at standard conditions, where etching is performed at preset wafer temperature in an enclosed chamber at a pressure such that all species present in the chamber, including water, are in the gas phase and condensation of species present on the etched surface is controlled. Thus all species involved remain in the gas phase even if trace water vapor appears in the process chamber. Preferably, etching is performed in a cluster dry tool apparatus.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: July 19, 2005
    Assignee: Penn State Research Foundation
    Inventors: Robert W. Grant, Jerzy Ruzyllo, Kevin Torek