Gas Flow Control Patents (Class 438/935)
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Patent number: 11804400Abstract: A substrate processing apparatus that includes a chamber, a substrate support disposed in the chamber, and a connection is provided. The chamber is provided with a bottom including a first flow path, and the substrate support includes a second flow path. The connection connects the first flow path to the second flow path, and the connection includes a sleeve through which the first flow path is in fluid communication with the second flow path, and a core including a first rod segment and a first elastic foam segment. The core is disposed in the sleeve, and a gap is defined between an inner surface of the sleeve and a side surface of the first rod segment.Type: GrantFiled: February 25, 2021Date of Patent: October 31, 2023Assignee: Tokyo Electron LimitedInventor: Mitsuaki Sato
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Patent number: 11644852Abstract: A system that controls the flow rates of a plurality of split channels provided parallel to each other to a certain flow split ratio includes: a flow split ratio calculation unit that, in order to be able to diagnose whether a system abnormality that affects the flow split ratio is occurring, calculates a ratio of output values of flow rate sensors obtained by allowing, while fluid control valves of different split channels are closed, fluids to flow in these split channels as an actual flow split ratio; a reference flow split ratio storage unit that stores a reference flow split ratio serving as a reference for the actual flow split ratio; and an abnormality diagnosis unit that compares the actual flow split ratio and the reference flow split ratio, and diagnoses a system abnormality.Type: GrantFiled: May 11, 2021Date of Patent: May 9, 2023Assignee: HORIBA STEC, Co., Ltd.Inventors: Yusuke Kanamaru, Kotaro Takijiri, Kazuya Shakudo
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Patent number: 9713203Abstract: In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator.Type: GrantFiled: March 19, 2012Date of Patent: July 18, 2017Assignee: III HOLDINGS 1, LLCInventor: Krishnakumar Mani
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Patent number: 8658449Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.Type: GrantFiled: March 31, 2010Date of Patent: February 25, 2014Assignee: Sony CorporationInventors: Naoki Jogan, Takahiro Arakida
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Patent number: 8530329Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.Type: GrantFiled: June 16, 2011Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Soon Choi, Jun-Won Lee, Gil-Heyun Choi, Eun-Kee Hong, Hong-Gun Kim, Ha-Young Yi
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Patent number: 8469046Abstract: The method for parallel operation of moisture generating reactors according to the present invention operates so that an orifice, provided with an orifice hole having a predetermined opening diameter, is disposed on a mixed-gas inlet side of each of a plurality of moisture generating reactors connected in parallel with each other, and mixed gas G consisting of hydrogen and oxygen is supplied from a mixer to each of the moisture generating reactors through each orifice, and the flows of moisture generated by the moisture generating reactors are combined, and the resulting combined moisture is supplied to an apparatus that uses high-purity water. Thus, a need to increase the amount of high-purity water supply is met by allowing a plurality of moisture generating reactors to perform a parallel water generating operation by branching off a mixed gas consisting of H2 and O2 by using a simple orifice construction.Type: GrantFiled: April 17, 2007Date of Patent: June 25, 2013Assignee: Fujikin IncorporatedInventors: Yukio Minami, Keiji Hirao, Masaharu Taguchi, Toshiro Nariai, Koji Kawada, Akihiro Morimoto, Nobukazu Ikeda
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Patent number: 8461062Abstract: The substrate processing apparatus includes: a processing chamber for storing and processing substrates stacked in multiple stages in horizontal posture; at least one processing gas supply nozzle which extends running along an inner wall of the processing chamber in the stacking direction of the substrates and supplies a processing gas to the inside of the processing chamber; a pair of inactive gas supply nozzles which are provided so as to extend running along the inner wall of the processing chamber in the stacking direction of the substrates and so as to sandwich the processing gas supply nozzle from both sides thereof along the circumferential direction of the substrates and which supply the inactive gas to the inside of the processing chamber; and an exhaust line for exhausting the inside of the processing chamber.Type: GrantFiled: December 20, 2011Date of Patent: June 11, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Masanori Sakai, Yuji Takebayashi, Tsutomu Kato, Shinya Sasaki, Hirohisa Yamazaki
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Patent number: 8389389Abstract: Provided are a semiconductor layer manufacturing method and a semiconductor manufacturing apparatus capable of forming a high quality semiconductor layer even by a single chamber system, with a shortened process time required for reducing a concentration of impurities that exist in a reaction chamber before forming the semiconductor layer. A semiconductor device manufactured using such a method and apparatus is also provided.Type: GrantFiled: December 5, 2007Date of Patent: March 5, 2013Assignee: Sharp Kabushiki KaishaInventors: Katsushi Kishimoto, Yusuke Fukuoka
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Patent number: 8367566Abstract: A substrate processing apparatus having a processing chamber for processing a substrate; a processing gas feeding line for feeding a processing gas into the processing chamber; an inert gas feeding line for feeding an inert gas into the processing chamber; an inert gas vent line provided in the inert gas feeding line, for exhausting the inert gas fed into the inert gas feeding line without feeding the inert gas into the processing chamber; a first valve provided in the inert gas feeding line, on a downstream side of a part where the inert gas vent line is provided in the inert gas feeding line; a second valve provided in the inert gas vent line; and an exhaust line that exhausts an inside of the processing chamber.Type: GrantFiled: July 12, 2012Date of Patent: February 5, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Atsushi Sano, Hideharu Itatani, Mitsuro Tanabe
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Patent number: 8340827Abstract: A method for establishing a mass flow controller (MFC) control scheme, which is configured for reducing a time scale for gas delivery into a processing chamber, for a recipe is provided. The method includes identifying a set of delayed gas species utilized during execution of the recipe with a set of delivery time slower than a target delivery time scale. The method also includes establishing an initial overshoot strength and an initial overshoot duration for each gas specie of the set of delayed gas species. The method further includes establishing MFC control scheme by adjusting an MFC hardware for each gas specie during the execution of the recipe. Adjusting the MFC hardware includes applying the initial overshoot strength for the initial overshoot duration to determine if the MFC control scheme provides for each gas specie a pressure profile within a target accuracy of an equilibrium pressure for the processing chamber.Type: GrantFiled: June 3, 2009Date of Patent: December 25, 2012Assignee: Lam Research CorporationInventors: Gunsu Yun, Iqbal A. Shareef, Kurt Jorgensen, Robert Charatan
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Patent number: 8291935Abstract: Each of plurality of gas sources flows to a different one of a plurality of separate source gas flow paths. Then, a source gas is distributed directly from each of plurality of separate source gas flow paths to a plurality of separate gas mixture flow paths, thereby distributing a plurality of source gases to each of different flow paths. A plurality of separate gas mixture streams is generated by flowing a plurality of source gases in each of a plurality of separate gas mixture flow paths. In some embodiments, each of a plurality of separate source gas flow paths comprises a gas distribution duct, and each of a plurality of gas mixture flow paths comprises a gas mixing conduit. In some embodiments, a gas distribution duct includes a plurality of gas distribution ports and a gas source port connectable to a gas source. In some embodiments, a gas mixing conduit comprises a plurality of gas inlet holes, a gas mixing region, and a gas outlet hole.Type: GrantFiled: April 7, 2009Date of Patent: October 23, 2012Assignee: Novellus Systems, Inc.Inventors: Neil J. Merritt, Kevin D. Jennings, George A. Gilbert, David E. Bowser, Sooyun Joh
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Patent number: 8048687Abstract: There is provided a processing method for performing a recovery process on a damaged layer formed on a surface of a low-k film of a target substrate by introducing a processing gas containing a methyl group into a processing chamber. The method includes: increasing an internal pressure of the processing chamber up to a first pressure lower than a processing pressure for the recovery process by introducing a dilution gas into the processing chamber maintained in a depressurized state; then stopping the introduction of the dilution gas, and increasing the internal pressure of the processing chamber up to a second pressure as the processing pressure for the recovery process by introducing the processing gas into a region where the target substrate exists within the processing chamber; and performing the recovery process on the target substrate while the processing pressure is maintained.Type: GrantFiled: June 1, 2010Date of Patent: November 1, 2011Assignee: Tokyo Electron LimitedInventors: Wataru Shimizu, Kazuhiro Kubota, Daisuke Hayashi
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Patent number: 7927907Abstract: The invention relates to a method for producing solar cells comprising at least one p-i-n layer sequence containing micro-crystalline layers with the aid of a PECVD method. Said method is characterised in that all layers of the p-i-n layer sequence are deposited in a single-chamber process. The electrodes are interspaced at a distance of between 5 and 15 mm and the gas is distributed by means of a shower-head gas inlet, which guarantees a homogeneous distribution of the gas over the substrate. SiH4 gas streams with values of between 0.01 and 3 sccm/cm2 are added with a process pressure of between 8 and 50 hPa. The heater temperature is set at between 50 and 280° C. and the HF output is between 0.2 and 2 watt/cm2. The H2 gas streams have values of between 0.3 and 30 sccm/cm2, in particular between 0.3 and 10 sccm/cm2.Type: GrantFiled: December 16, 2004Date of Patent: April 19, 2011Assignee: Forschungszentrum Julich GmbHInventors: Tobias Repmann, Bernd Rech
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Patent number: 7910494Abstract: A gas delivery system for supplying a process gas from a gas supply to a thermal processing furnace, a thermal processing furnace equipped with the gas delivery system, and methods for delivering process gas to a thermal processing furnace. The gas delivery system comprises a plurality of regulators, such as mass flow controllers, in a process gas manifold coupling a gas supply with a thermal processing furnace. The regulators establish a corresponding plurality of flows of a process gas at a plurality of flow rates communicated by the process gas manifold to the thermal processing furnace. The gas delivery system may be a component of the thermal processing furnace that further includes a liner that surrounds a processing space inside the thermal processing furnace.Type: GrantFiled: March 29, 2006Date of Patent: March 22, 2011Assignee: Tokyo Electron LimitedInventors: Anthony Dip, Eric J. Malstrom
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Patent number: 7829353Abstract: A system for delivering a desired mass of gas, including a chamber, a first valve controlling flow into the chamber, a second valve controlling flow out of the chamber, a pressure transducer connected to the chamber, an input device for providing a desired mass to be delivered, and a controller connected to the valves, the pressure transducer and the input device. The controller is programmed to receive the desired mass from the input device, close the second valve and open the first valve, receive chamber pressure measurements from the pressure transducer, and close the inlet valve when pressure within the chamber reaches a predetermined level. The controller is then programmed to wait a predetermined waiting period to allow the gas inside the chamber to approach a state of equilibrium, then open the outlet valve at time=t0, and close the outlet valve at time=t* when the mass of gas discharged equals the desired mass.Type: GrantFiled: October 26, 2006Date of Patent: November 9, 2010Assignee: MKS Instruments, Inc.Inventors: Ali Shajii, Siddharth P. Nagarkatti, Matthew Mark Besen, William R. Clark, Daniel Alexander Smith, Bora Akgerman
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Patent number: 7829475Abstract: The present invention relates to control of copper contamination to semiconductor substrates upon operation of a heat treatment apparatus which is a semiconductor manufacturing apparatus and which is constructed with quartz products having been contaminated with copper when machined. The quartz product is placed in a heating atmosphere on the stage where it is not still used for a heat treatment for semiconductor substrates. Baking gases including a hydrogen chloride gas and a gas for enhancing activity of the hydrogen chloride gas, for example, an oxygen gas, are then supplied to the quartz product. Consequently, the copper concentration in the region from the surface to the 30 ?m depth of the quartz product can be controlled below 20 ppb, preferably below 3 ppb. The baking process may be carried out before or after assembling the quartz product into the heat treatment apparatus.Type: GrantFiled: June 20, 2007Date of Patent: November 9, 2010Assignee: Tokyo Electron LimitedInventors: Katsuhiko Anbai, Masayuki Oikawa, Tetsuya Shibata, Yuichi Tani
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Patent number: 7576018Abstract: A method is provided to cause deformation of a substrate during processing of the substrate.Type: GrantFiled: March 12, 2007Date of Patent: August 18, 2009Assignee: Tokyo Electron LimitedInventor: Merritt Funk
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Patent number: 7494941Abstract: At a time of a substrate loading step or/and at a time of a substrate unloading step, particles are effectively eliminated from a reaction chamber. Provided are a step of loading at least one wafer 200 into a reaction chamber 201, a step of introducing reaction gas into the reaction chamber 201, and exhausting an inside of the reaction chamber 201, thereby processing the wafer 200, and a step of unloading the processed wafer 200 from the reaction chamber 201. In the step of loading the wafer 200 or/and in the step of unloading the wafer 200, the inside of the reaction chamber 201 is exhausted at a larger exhaust flow rate than an exhaust flow rate in the step of processing the wafer 200.Type: GrantFiled: November 19, 2004Date of Patent: February 24, 2009Assignee: Hitachi Kokusai Electric Inc.Inventors: Osamu Kasahara, Kiyohiko Maeda, Akihiko Yoneda
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Patent number: 7479443Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.Type: GrantFiled: October 4, 2007Date of Patent: January 20, 2009Assignee: ASM America Inc.Inventors: Matthias Bauer, Paul Brabant, Trevan Landin
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Patent number: 7426939Abstract: A rotatable valve allows the flow of a fluid to be switched between at least two different paths by rotating an element within the valve. Advantageously, both the housing of the valve and the rotatable element within the housing are formed of glass, making the valve resistant to corrosion. The housing has at least three openings for connecting to at least three different conduits. By rotating the rotatable element, a flow path can be created between a first of the conduits and either a second or a third one of the conduits. Thus, the path between the first conduit and the second conduit forms a first path, while the path between the first conduit and the third conduit forms a second path.Type: GrantFiled: September 29, 2006Date of Patent: September 23, 2008Assignee: ASM International N.V.Inventor: Henderikus H. N. J. Jorg
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Patent number: 7354874Abstract: The present invention is directed to a semiconductor apparatus that enables in situ wet processing of semiconductor wafers, and prevents creation of a static pressure within the in situ wet processing system. The apparatus comprises multiple exhaust receptacles. Each exhaust receptacle is operable in an open and closed position and receives an associated toxic wet processing byproduct only in the open position. An exhaust is connected to each exhaust receptacle and suctions the contents of said exhaust receptacle in both the open and closed positions. An intake is connected to said exhaust receptacle only when the exhaust receptacle is in a closed position. The intake introduces a gas chemically compatible to the toxic wet processing byproduct associated with the exhaust receptacle. The exhaust releases the toxic wet processing byproduct and the chemically compatible gas to the same waste stream at the semiconductor factory.Type: GrantFiled: September 23, 2005Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Michael R. Biagetti, Charles J. Taft
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Patent number: 7253032Abstract: First laser light is irradiated (energy density of 400 to 500 mj/cm2) to a semiconductor film 102 in an atmosphere containing oxygen in order to obtain a semiconductor film 102b having large depressions and projections on the surface. Then, an oxidized film 105a formed by the irradiation of the first laser light is removed. After that, an inert gas with an oxygen density of 10 ppm or below is blown thereto, and, at the same time, second laser light is irradiated thereto (the energy density is higher than that of the irradiation of the first laser light). Thus, the surface of the semiconductor film 102b is flattened, and a semiconductor film 102c having fewer depressions and projections on the surface can be obtained.Type: GrantFiled: April 19, 2002Date of Patent: August 7, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Koichiro Tanaka
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Patent number: 7200498Abstract: The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). The measurement system measures an electrical value at a plurality of locations along a surface of the wafer, prior to and after exposure of the surface to an activation system (112). The activation system is provided to cause any copper contamination along the surface to form a precipitate thereon. An analysis component (110) is provided to receive electrical value and location information from the measurement system and to identify, from the measurements, the presence and location of copper contamination along the semiconductor wafer surface.Type: GrantFiled: May 26, 2004Date of Patent: April 3, 2007Assignee: Texas Instruments IncorporatedInventor: Deepak A. Ramappa
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Patent number: 7135418Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.Type: GrantFiled: March 9, 2005Date of Patent: November 14, 2006Assignee: Novellus Systems, Inc.Inventor: George D. Papasouliotis
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Patent number: 7086410Abstract: A common solvent vapor supply source 41 and a common processing gas supply source 42 supply ozone gas and steam to a plurality of processing vessels 30A, 30B. Pressures in the processing vessels are regulated by adjusting the openings of the valuable throttle valves 50A, 50B, which are placed in exhaust lines 80A, 80B, respectively.Type: GrantFiled: March 7, 2003Date of Patent: August 8, 2006Assignee: Tokyo Electron LimitedInventors: Yasuhiro Chouno, Norihiro Ito, Keigo Satake, Tadashi Iino
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Patent number: 7026183Abstract: For manufacturing a long-wavelength semiconductor light emitting device having excellent characteristics and long lifetime, a highly reactive gas is supplied together with a source material of As while the supply of a source material of a group III element is interrupted during the growth of a layer (GaAs optical guide layer) anteriorly adjacent to the active layer or immediately before the growth of the active layer. The highly reactive gas may be di-methyl hydrazine or ammonia (NH3), for example.Type: GrantFiled: August 13, 2004Date of Patent: April 11, 2006Assignee: Sony CorporationInventors: Tomonori Hino, Hironobu Narui, Jugo Mitomo
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Patent number: 7018728Abstract: A boron phosphide-based semiconductor device includes a single crystal substrate having formed thereon a boron-phosphide (BP)-based semiconductor layer containing boron and phosphorus as constituent elements, where phosphorus (P) occupying the vacant lattice point (vacancy) of boron (B) and boron occupying the vacant lattice point (vacancy) of phosphorus are present in the boron-phosphide (BP)-based semiconductor layer. The boron phosphide-based semiconductor device includes a p-type boron phosphide-based semiconductor layer in which boron occupying the vacancy of phosphorus is contained in a higher atomic concentration than phosphorus occupying the vacancy of boron and a p-type impurity of Group II element or Group I V element is added.Type: GrantFiled: December 12, 2002Date of Patent: March 28, 2006Assignee: Showa Denko K.K.Inventor: Takashi Udagawa
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Patent number: 7008880Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: March 7, 2006Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6949450Abstract: A system and sequential method for integrated, in-situ modification of a substrate and subsequent atomic layer deposition of a thin film onto the substrate in an evacuated chamber includes introducing at least one feed gas into the chamber; generating a plasma from the feed gas; exposing said substrate to ions and/or radicals formed by the plasma; modulating any ions; reacting the substrate with said modulated ions and/or radicals to remove any contaminants from the substrate and producing a modified substrate.Type: GrantFiled: November 26, 2001Date of Patent: September 27, 2005Assignee: Novellus Systems, Inc.Inventors: Tony P. Chiang, Karl F. Leeser
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Patent number: 6921707Abstract: A process for forming metal oxides, including mixed metal oxides, in a dilute vapor phase at a temperature below approximately 350 degrees Fahrenheit. The resulting novel oxides can be formed as dense films or coatings with very high strain-to-crack values, or as nanoparticles, depending primarily upon the concentration of the reactants. The novel oxides are formed by the reaction in the vapor phase of reactive metal molecules with atomic oxygen. The reactions are instantaneous at room temperature, which permits this process to be applied to the formation of metal oxides on temperature sensitive substrates. The atomic oxygen and highly reactive metal containing molecules are generated by the application of an effective amount of ultraviolet radiation.Type: GrantFiled: May 26, 2000Date of Patent: July 26, 2005Assignee: UltrametInventors: Alfred Zinn, David Scott
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Patent number: 6905963Abstract: A semiconductor device fabricating method for forming a boron doped silicon film includes the step of forming the boron doped silicon film on a substrate at an inner temperature of the reaction furnace ranging from about 460 to 600° C. or at an average velocity of reaction gases in the reaction furnace being not great than about 2200 cm/min. Further, a substrate processing apparatus for forming a boron doped silicon film on a substrate includes a gas supply line for supplying BCl3 to the reaction furnace. The gas supply line is installed in a portion of the reaction furnace opposite to a heater, and has an outlet for discharging BCl3. The outlet of the gas supply line is provided at an upstream side of gas flow in the reaction furnace.Type: GrantFiled: September 27, 2002Date of Patent: June 14, 2005Assignee: Hitachi Kokusai Electric, Inc.Inventors: Takaaki Noda, Akira Morohashi, Junji Asahi
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Patent number: 6867152Abstract: A rapid vapor deposition (RVD) method conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant, low wet etch rate, low film shrinkage and low stress hysteresis, appropriate for various integrated circuit dielectric gap fill applications such as shallow trench isolation. The method includes the following two principal operations: depositing a thin conformal and saturated layer of aluminum-containing precursor over some or all of the substrate surface; and exposing the saturated layer of aluminum-containing precursor to a silicon-containing precursor gas to form a dielectric layer. In some cases, the substrate temperatures during contact with silicon-containing precursor are greater than about 250 degree Celsius to produce an improved film. In other cases, post-deposition anneal process may be used to improve properties of the film.Type: GrantFiled: September 26, 2003Date of Patent: March 15, 2005Assignee: Novellus Systems, Inc.Inventors: Dennis M. Hausmann, Adrianne K. Tipton, Patrick A. Van Cleemput, Bunsen Nie, Francisco J. Juarez, Teresa Pong
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Patent number: 6858508Abstract: A method for annealing an SOI in which two annealing steps are followed by a cooling step. During the second annealing step, the annealing temperature is from 993° C. to the melting point of silicon. During the cooling step, the cooling rate is not less than 0.12° C./sec when a temperature is from 993° C. to 775° C.Type: GrantFiled: May 20, 2003Date of Patent: February 22, 2005Assignee: Canon Kabushiki KaishaInventor: Masataka Ito
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Patent number: 6844260Abstract: Systems and methods for insitu post atomic layer deposition (ALD) destruction of active species are provided. ALD processes deposit multiple atomic layers on a substrate. Pre-cursor gases typically enter a reactor and react with the substrate resulting in a monolayer of atoms. After the remaining gas is purged from the reactor, a second pre-cursor gas enters the reactor and the process is repeated. The active species of some pre-cursor gases do not readily purge from the reactor, thus increasing purge time and decreasing throughput. A high-temperature surface placed in the reactor downstream from the substrate substantially destroys the active species insitu. Substantially destroying the active species allows the reactor to be readily purged, increasing throughput.Type: GrantFiled: January 30, 2003Date of Patent: January 18, 2005Assignee: Micron Technology, Inc.Inventors: Demetrius Sarigiannis, Shuang Meng, Garo J. Derderian
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Patent number: 6809015Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: GrantFiled: January 9, 2003Date of Patent: October 26, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
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Patent number: 6806211Abstract: A substrate processing apparatus consists of: a processing container; a first processing gas supply unit and a second processing gas supply unit, countering each other, prepared on both sides of a substrate-to-be-processed to the processing container; and a first slit-shaped exhaust opening and a second slit-shaped exhaust opening provided one on each side of the substrate-to-be-processed approximately perpendicular to the flow of the first processing gas and the second processing gas, countering the first processing gas supply unit and the second processing gas supply unit, respectively. The first processing gas is passed along the surface of the substrate-to-be-processed from the first processing gas supply unit to the first exhaust opening, and is adsorbed by the surface of the substrate-to-be-processed.Type: GrantFiled: August 25, 2003Date of Patent: October 19, 2004Assignee: Tokyo Electron LimitedInventors: Hiroshi Shinriki, Koji Homma
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Patent number: 6787377Abstract: The invention is a method of determining a set temperature profile for a method of controlling respective substrate temperatures of a plurality of groups in accordance with respective corresponding set temperature profiles, in a method of heat processing a plurality of substrates that are classified into the plurality of groups.Type: GrantFiled: January 24, 2003Date of Patent: September 7, 2004Assignee: Tokyo Electron LimitedInventors: Wenling Wang, Koichi Sakamoto, Fujio Suzuki, Moyuru Yasuhara
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Patent number: 6720274Abstract: A semiconductor device fabricating method includes the steps of loading one or more substrates into a boat disposed in a waiting room positioned next to a reaction furnace; vacuum-evacuating the waiting room to a vacuum state at a base pressure; loading the boat into the reaction furnace at a first ambient pressure; and recovering a temperature of the reaction furnace at a second ambient pressure. The first or the second ambient pressure is greater than the vacuum state but less than the atmospheric pressure. Further, the method includes the step of increasing the temperature of the one or more substrates at a third ambient pressure, and also the third ambient pressure is greater than the base pressure but less than the atmospheric pressure.Type: GrantFiled: November 12, 2002Date of Patent: April 13, 2004Assignee: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Kenichi Suzaki, Norikazu Mizuno
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Patent number: 6716287Abstract: A processing chamber with a flow-restricting ring is generally provided. In one embodiment, a processing chamber includes a chamber body, a lid assembly, a substrate support and a flow-restricting ring. The chamber body has sidewalls and a bottom. The lid assembly is disposed on the sidewalls and encloses an interior volume of the chamber body. The substrate support is disposed in the interior volume of the chamber body and is adjustable in elevation between the lid assembly and the bottom of the chamber body. The flow-restricting ring has an outer edge disposed proximate the sidewalls of the chamber body and an inner edge disposed proximate the substrate support when the substrate support is disposed in an elevated position. The inner edge of the ring and the substrate support are disposed in a spaced-apart relation defining an annular flow control orifice.Type: GrantFiled: October 18, 2002Date of Patent: April 6, 2004Assignee: Applied Materials Inc.Inventors: James V. Santiago, Damian W. Sower
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Publication number: 20040058512Abstract: A method for activating implanted dopants in a semiconductor substrate to form shallow junctions comprises the steps of: maintaining gas pressure in the processing chamber at a level significantly lower than atmospheric pressure, providing a flow of a carrier gas into the processing chamber, subjecting the substrate to a temperature treatment process, and introducing oxygen into the processing chamber during all or part of the temperature treatment process.Type: ApplicationFiled: September 20, 2002Publication date: March 25, 2004Inventors: Dean Jennings, Sairaju Tallavarjula, Randhir Thakur
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Patent number: 6706585Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.Type: GrantFiled: April 2, 2003Date of Patent: March 16, 2004Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
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Patent number: 6689677Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: GrantFiled: November 1, 2002Date of Patent: February 10, 2004Assignee: STMicroelectronics, Inc.Inventors: Guang-Bo Gao, Hoang Huy Hoang
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Patent number: 6686281Abstract: A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3 as a doping gas. The substrate processing apparatus includes a plurality of gas outlets for supplying GeH4 at different locations in the reaction tube and a doping gas line for supplying BCl3 at least at an upstream side of gas flow in the reaction tube.Type: GrantFiled: September 5, 2002Date of Patent: February 3, 2004Assignee: Hitachi Kokusai Electric Inc.Inventors: Hirohisa Yamazaki, Takaaki Noda
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Patent number: 6645879Abstract: Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device.Type: GrantFiled: August 8, 2002Date of Patent: November 11, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Kee Hong, Ju-Bum Lee, Ju-Seon Goo, Myeong-Cheol Kim, Hong-Gun Kim
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Patent number: 6638880Abstract: In the chemical vapor deposition apparatus, a substrate stage for mounting a substrate is provided inside a reaction chamber of the apparatus. A source gas inlet for introducing a source gas and exhaust outlets and for exhausting the source gas are provided. Exhaust outlet valves provided for exhaust outlets are open and shut successively with time. The direction of the flow of source gas relative to the fixed substrate varies with time. The present chemical vapor deposition apparatus allows the improved evenness of film thickness, the composition ratio, and the like within the substrate surface as well as the reduction of particles of foreign substance generated inside the reaction chamber.Type: GrantFiled: October 19, 2001Date of Patent: October 28, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mikio Yamamuka, Takaaki Kawahara, Masayoshi Tarutani, Tsuyoshi Horikawa, Shigeru Matsuno, Takehiko Sato
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Patent number: 6596641Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.Type: GrantFiled: March 1, 2001Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Mark E. Jost, Chris W. Hill
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Patent number: 6596650Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: August 28, 2001Date of Patent: July 22, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6573184Abstract: An atomic layer deposition (ALD) thin film deposition apparatus including a reactor in which a wafer is mounted and a thin film is deposited on the wafer, a first reaction gas supply portion for supplying a first reaction gas to the reactor, a second reaction gas supply portion for supplying a second reaction gas to the reactor, a first reaction gas supply line for connecting the first reaction gas supply portion to the reactor, a second reaction gas supply line for connecting the second reaction gas supply portion to the reactor, a first inert gas supply line for supplying an inert gas from an inert gas supply source to the first reaction gas supply line, a second inert gas supply line for supplying the inert gas from the inert gas supply source to the second reaction gas supply line, and an exhaust line for exhausting the gas from the reactor.Type: GrantFiled: March 7, 2002Date of Patent: June 3, 2003Assignee: IPS, Ltd.Inventor: Young-Hoon Park
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Patent number: 6569780Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: August 28, 2001Date of Patent: May 27, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6553332Abstract: A process chamber (12) is used for plasma etching of a wafer (21) disposed therein. A gas mixture supplied to the chamber eventually passes through openings (28) in a baffle plate (27). After the chamber has been cleaned, several test wafers are etched under conditions which are equivalent, except that a different gas pressure is used for each wafer. The effective etch rates are measured from these wafers, and used to extrapolate a reference curve (141) representing effective etch rate relative to pressure. During subsequent production use of the chamber, a similar procedure is periodically used to generate a test curve (142). The peak values (143, 144) of the reference and test curves are compared (147) to monitor process drift within the chamber. The peak values of respective curves obtained from two or more similar chambers can be compared to evaluate performance differences between the chambers.Type: GrantFiled: November 30, 2000Date of Patent: April 22, 2003Assignee: Texas Instruments IncorporatedInventor: Yaojian Leng