Gas Flow Control Patents (Class 438/935)
  • Patent number: 6518202
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: February 11, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20030003696
    Abstract: Generally, a substrate processing apparatus is provided. In one aspect of the invention, a substrate processing apparatus is provided. In one embodiment, the substrate processing apparatus includes one or more chamber bodies coupled to a gas distribution system. The chamber bodies define at least a first processing region and a second processing region within the chamber bodies. The gas distribution system includes a first, a second and a third gas supply circuit. The first gas supply circuit is teed between the first and second processing regions and is adapted to supply a first processing gas thereto. The second gas supply circuit is coupled to the first processing region and adapted to supply a second process gas thereto. The third gas supply circuit is coupled to the second processing region and is adapted to supply a third process gas thereto. Alternatively, the processing regions may be disposed in a single chamber body.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Avgerinos Gelatos, Joel M. Huston, Lawrence Chung-Lai Lei, Vicky Uyen Nguyen, Yin Lin, Fong Chang
  • Publication number: 20020153350
    Abstract: A method and an apparatus for preventing contamination in a plasma process chamber when the primary heating means for the chamber is turned off is provided. In the method, a heated gas is flown over the top chamber lid of the plasma process chamber. A suitable heated gas can be nitrogen gas that is heated to a temperature between about 100° C and about 150° C. The present invention is further directed to an apparatus of a plasma process chamber that is equipped with a primary heating means and an auxiliary heating means. The auxiliary heating means is turned on as soon as the primary heating means is turned off such that a heated gas is flown onto the top chamber lid, thus preventing contaminating particles from falling off the chamber wall and preventing contamination of a wafer situated inside the chamber.
    Type: Application
    Filed: April 18, 2001
    Publication date: October 24, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Liang Lu, Yung-Chih Yao
  • Publication number: 20020137312
    Abstract: Provided herein is an emissivity-change-free pumping plate kit used in a single wafer chamber. This kit comprises a top open pumping plate, and optionally a skirt and/or a second stage choking plate. The skirt may be installed around the wafer heater, underneath the wafer heater, or along the chamber body inside the chamber. The choking plate is installed downstream of the top open pumping plate along the purge gas flow. Also provided is a method of preventing emissivity change and further providing optimal film thickness uniformity during wafer processing by utilizing such kit in the chamber.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 26, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Lee Luo, Henry Ho, Shulin Wang, Binh Hoa Tran, Alexander Tam, Errol A.C. Sanchez, Xianzhi Tao, Steven A. Chen
  • Patent number: 6422264
    Abstract: A fluid supply apparatus with a plurality of flow lines branching out from one pressure regulator with the flow lines arranged in parallel and constructed so that opening or closing one flow passage will have no transient effect on the steady flow of the other flow passages. Each flow passage is provided with a time delay-type mass flow controller MFC so that when one closed fluid passage is opened, the mass flow controller on that flow passage reaches a set flow rate Qs in a specific delay time &Dgr;t from the starting point. The invention includes a method and an apparatus in which a plurality of gas types can be controlled in flow rate with high precision by one pressure-type flow control system.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: July 23, 2002
    Assignees: Fujikin Incorporated, OHMI, Tadahiro, Tokyo Electron Ltd.
    Inventors: Tadahiro Ohmi, Satoshi Kagatsume, Kazuhiko Sugiyama, Yukio Minami, Kouji Nishino, Ryousuke Dohi, Katsunori Yonehana, Nobukazu Ikeda, Michio Yamaji, Jun Hirose, Kazuo Fukazawa, Hiroshi Koizumi, Hideki Nagaoka, Akihiro Morimoto, Tomio Uno, Eiji Ideta, Atsushi Matsumoto, Toyomi Uenoyama, Takashi Hirose
  • Publication number: 20020013069
    Abstract: Disclosed in an original chuck effective to prevent deformation of an original as the same is attracted and held by the chuck, thereby to reduce distortion of a pattern of the original or distortion of a pattern transferred to a substrate, such as a wafer, due to the deformation of the original. The original chuck includes four attracting and holding portions disposed to attract four corners of the original, and each attracting and holding portion has a steel ball to be engaged with the original and an attracting pad surrounding the steel ball and being made of an elastic material. A negative pressure is produced inside the attraction pad, in response to an operation of a vacuum source and through an attracting bore, such that the attracting pads attract the original while the steel balls support the original through point contact. In one preferred from, at least one of the attracting and holding portions is made adjustable upwardly/downwardly.
    Type: Application
    Filed: May 23, 2001
    Publication date: January 31, 2002
    Inventor: Yukihiro Yokota
  • Patent number: 6337224
    Abstract: In a method of manufacturing a silicon-based thin film photoelectric converter, a crystalline photoelectric conversion layer included in the photoelectric converter is deposited by plasma CVD under the following conditions: the temperature of the underlying film is at most 550° C.; a gas introduced into a plasma reaction chamber has a silane-based gas and a hydrogen gas where the flow rate of the hydrogen gas relative to the silane-based gas is at least 50 times; the pressure in the plasma reaction chamber is set to 3 Torr; and the deposition speed is 17 nm/min in the thickness-wise direction.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: January 8, 2002
    Assignee: Kaneka Corporation
    Inventors: Yoshifumi Okamoto, Masashi Yoshimi, Kenji Yamamoto
  • Patent number: 6333272
    Abstract: A gas distribution system for processing a semiconductor substrate includes a plurality of gas supplies, a mixing manifold wherein gas from the plurality of gas supplies is mixed together, a plurality of gas supply lines delivering the mixed gas to different zones in the chamber, and a control valve. The gas supply lines include a first gas supply line delivering the mixed gas to a first zone in the chamber and a second gas supply line delivering the mixed gas to a second zone in the chamber. The control valve controls a rate of flow of the mixed gas in the first and/or second gas supply line such that a desired ratio of flow rates of the mixed gas is achieved in the first and second gas supply lines.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: December 25, 2001
    Assignee: Lam Research Corporation
    Inventors: Brian K. McMillin, Robert Knop
  • Patent number: 6303403
    Abstract: A method for preparing a gallium nitride phosphor which is capable of emitting light at luminance increased to a degree sufficient to permit the phosphor to be practically used. A dopant compound containing elements reacted with H2 and gasified by heating is arranged on an upstream side in a calcination oven in which NH3 is flowed and a matrix element compound is arranged on the downstream side therein, resulting in calcination of the compound being carried out. This permits GaN to be surrounded with ammonia and the dopant during the calcination, so that the GaN phosphor may be fully doped with the dopant.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: October 16, 2001
    Assignee: Futaba Denshi Kogyo, K.K.
    Inventors: Yoshitaka Sato, Yoriko Suda, Fumiaki Kataoka, Hitoshi Toki, Yuji Nomura
  • Patent number: 6296709
    Abstract: An improved vertical diffusion furnace for semiconductor manufacturing processes is provided. Temperature and flow rate management enables more uniform temperature distribution across the wafer during ramp up and ramp down, thereby preventing wafer warp.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: October 2, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Patent number: 6287989
    Abstract: A semiconductor wafer is treated in a chamber by introducing into the chamber a silicon-containing gas or vapor and hydrogen peroxide in vapor form. The silicon-containing gas or vapor is reacted with the hydrogen peroxide to form a short chain, inorganic fluid polymer on the wafer, which thus forms a generally planar layer.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: September 11, 2001
    Assignee: Trikon Technologies Limited
    Inventor: Christopher David Dobson
  • Patent number: 6239041
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: May 29, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Patent number: 6162716
    Abstract: A method of forming an amorphous-Si (.alpha.-Si) gate with two or more .alpha.-Si layers with mismatched grains. The first embodiment involves forming two or more amorphous silicon layers over the gate dielectric. The amorphous silicon layers are formed insitu (in a reactor chamber without removing the wafer from the chamber). An amorphous silicon layer is deposited by exposing the substrate to a Silicon containing gas (E.g., SiH.sub.4). The Si containing gas flow is stopped. The chamber is pumped down and back filled with an inert gas to remove said silicon containing gas. In the next insitu step, the Si containing gas is restarted thus depositing the next amorphous Si layer. This deposition and purge cycle is repeated the desired number of times to form two or more mismatched .alpha.-Si layers. In the second embodiment, after an .alpha.-Si layer is deposited, the wafer is etched, for example in an HF vapor or wet clean. Then the wafer is returned to the chamber and another .alpha.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: December 19, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Jih-Churng Twu
  • Patent number: 6140215
    Abstract: Method and apparatus are disclosed for low temperature deposition of CVD and PECVD films utilizing a gas-dispersing showerhead position within one inch of a rotating substrate. The showerhead is positioned a suitable distance below a gas-dispensing apparatus such as a steady stay flow of gas develops between the ring and showerhead. A cylindrical structure extends between the gas-dispersing ring and a showerhead to contain the gas over the showerhead yielding a small boundary layer over the substrate to ensure efficient uniform deposition of a film on a substrate surface. In the one embodiment of the present invention the showerhead is bias with RF energy such that it acts as an electrode to incite a plasma proximate with the substrate for PECVD. The cylinder is isolated from the showerhead such as by a quartz insulator ring to prevent ignition of a plasma within the cylinder, or alternatively, the cylinder is fabricated of quartz material.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: October 31, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Robert F. Foster, Joseph T. Hillman, Rikhit Arora
  • Patent number: 6127271
    Abstract: A process for dry etching a surface within a vacuum treatment reactor includes evacuating the reactor, generating a glow discharge within said reactor, feeding a reactive etching gas into said reactor and reacting said etching gas within said reactor, removing gas with reaction products of said reacting from said reactor and installing an initial flow of said etching gas into said reactor and reducing said flow after a predetermined time span and during said reacting. The vacuum treatment reactor has a reactor with a pumping arrangement for evacuating the reactor. A glow discharge generating arrangement is connected to an electric power supply. A gas tank arrangement is connected to the reactor and has a reactive etching gas such as SF.sub.4.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: October 3, 2000
    Assignee: Balzers Hochvakuum AG
    Inventors: Emmanuel Turlot, Jacques Schmitt, Philippe Grousset
  • Patent number: 6110844
    Abstract: A method of reducing particle deposition during the fabrication of microelectronic circuitry is presented. Reduction of particle deposition is accomplished by controlling the relative temperatures of various parts of the deposition system so that a large temperature gradient near the surface on which fabrication is taking place exists. This temperature gradient acts to repel particles from that surface, thereby producing cleaner surfaces, and thus obtaining higher yields from a given microelectronic fabrication process.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: August 29, 2000
    Assignee: Sandia Corporation
    Inventors: Daniel J. Rader, Ronald C. Dykhuizen, Anthony S. Geller
  • Patent number: 6109915
    Abstract: A drafting apparatus in a furnace. A buffer board having a plurality of gas intakes is disposed in a front end of the drafting apparatus. A laminar flow board having a plurality of gas outtakes is disposed in a rear end of the drafting apparatus. A drafting region is enclosed by the drafting apparatus. The drafting region comprises at least one drafting board to draft and redirect the gas flow. A laminar flow is then obtained to flow through the outtakes on the laminar board.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: August 29, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Tien-Jui Liu, Eric Chu, Tony Chen
  • Patent number: 6080297
    Abstract: The present invention provides an electrochemical system and process for the production of very high purity hydride gases and the feed product streams including these hydride gases at constant composition over extended periods of time. The processes and apparatuses of the invention can employ a lined pressure vessel (1) within which resides an electrochemical cell including cathode (2) and anode (3) material. The hydride gas produced within the vessel exits through port (4) to a manifold which contains automatic valve (8) to allow exit of the hydride gas. The hydride gas passes through one or more filters (7). The gas finally exits the manifold through a pressure regulator (6) to the point where it is utilized in semiconductor fabrication. A source of gas (11) for mixing with the hydride gas is also included.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: June 27, 2000
    Assignee: Electron Transfer Technologies, Inc.
    Inventor: William M. Ayers
  • Patent number: 6071796
    Abstract: The invention provides a method of making silicon-on-glass substrates used in the manufacture of flat panel displays. A layer of amorphous silicon film is deposited on a glass substrate. The amorphous silicon is annealed by excimer laser annealing, transforming the amorphous silicon into polycrystalline silicon. The excimer laser annealing is carried out in a predominantly air ambient environment at atmospheric pressure and room temperature. The process requires no environmental chamber to house the substrate during excimer laser annealing. The process displaces the ambient air immediately surrounding the target region on the surface of the silicon film, where the laser beam strikes the silicon film, with inert gas. As a result, the ambient environment at the point of annealing on the substrate is depleted of oxygen and the oxygen content of the resultant polycrystalline silicon layer is kept below a predetermined level.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: June 6, 2000
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Tolis Voutsas
  • Patent number: 6037272
    Abstract: An apparatus for low pressure chemical vapor deposition for fabricating a semiconductor device comprises a group of reaction chambers, a group of high-vacuum pumps connected to the reaction chambers, a group of gate valves connected to the high-vacuum pumps, and a low-vacuum pump connected to the gate valves. There are fewer gate valves than high-vacuum pumps. A method for fabricating a semiconductor device using the above apparatus includes the sequence and duration of opening gate valves, injecting reaction gases, and pumping with the low vacuum pump. According to the present invention, since the number of pumps is reduced, the cost for installation, operation and maintenance of the semiconductor device fabrication apparatus is reduced.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: March 14, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Sig Park, Young Sun Kim, Jung Ki Kim
  • Patent number: 6030902
    Abstract: A novel batch processing system used, for example, in plasma etching and chemical vapor deposition, wherein the pressure in the reactor is cycled through a varying pressure to increase the transfer of the reactant materials to the center of the wafer. One version of the invention provides a method that includes the steps of (i) feeding reactant gases into a reaction vessel, (ii) exhausting unused reactive gases and/or reaction by-products from the reaction vessel, and (iii) cycling the pressure in the reaction vessel between a higher pressure P.sub.high and a lower pressure P.sub.low. Another version of the invention provides an apparatus that comprises (i) a reaction vessel, (ii) a feed means for feeding reactive gases into the reaction vessel, (iii) an exhaust means for exhausting unused reactive gases and/or reaction by-products from the reaction vessel, and (d) a pressure control means for cycling the pressure in the reaction vessel between a higher pressure P.sub.high and a lower pressure P.sub.low.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: February 29, 2000
    Inventor: Kevin G. Donohoe
  • Patent number: 6015503
    Abstract: Apparatus and process for conditioning a generally planar substrate, contained in a chamber isolatable from the ambient environment and fed with a conditioning gas which includes a reactive gas. The apparatus includes a support for supporting the substrate in the chamber, the substrate being in a lower pressure reaction region of the chamber. A gas inlet is provided for feeding conditioning gas into a gas inlet region of the chamber which is at a higher pressure than the lower pressure reaction region so that the pressure differential causes the conditioning gas to flow toward the surface of the substrate wherein the conditioning gas component will chemically react with and condition the substrate surface, both said higher and lower pressure regions operating in a viscous flow regime.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: January 18, 2000
    Assignee: FSI International, Inc.
    Inventors: Jeffery W. Butterbaugh, David C. Gray, Robert T. Fayfield, Kevin Siefering, John Heitzinger, Fred C. Hiatt
  • Patent number: 5997589
    Abstract: A semiconductor fabrication chamber is disclosed which contains (a) a main chamber; (b) a baffle member separating the main chamber into a first chamber and a second chamber, (c)a vacuum pump to pump gas through the main chamber; and (d) a computer. The first chamber contains a gas inlet, a metering device, and a supporting member to support a wafer to be fabricated, and the second chamber contains a gas outlet and a first pressure gauge. The baffle member contains at least one adjustable opening which is controllable by the computer. Prior to a fabrication process, such as plasma etching, a pressure difference between the first pressure gauge and a temporary pressure gauge installed inside the second chamber is calculated and compared against a standard value, and the computer will adjust the opening of the baffle plate so as to minimize such pressure difference, which is related to the deposition of particulate matters on the opening.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: December 7, 1999
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Chung Tien
  • Patent number: 5968845
    Abstract: An etching method for performing dry-etching on a III-V group compound semiconductor or a II-VI group compound semiconductor in a dry-etching apparatus comprising a plasma source for creating a plasma of density of about 10.sup.10 cm.sup.-3 or greater, using a mixed gas containing a gas including a halogen element and a gas including nitrogon. The etching conditions are as follows: (a flow rate of the gas containing said halogen gas)/(a flow rate of said nitrogen gas) .gtoreq.1; and an internal pressure during etching reaction is about 1 mTorr or greater.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: October 19, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoji Chino, Yasuhito Kumabuchi, Isao Kidoguchi, Hideto Adachi
  • Patent number: 5937273
    Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: August 10, 1999
    Assignee: Fujitsu Limited
    Inventors: Takuya Fujii, Mitsuru Ekawa, Tsuyoshi Yamamoto, Hirohiko Kobayashi
  • Patent number: 5925232
    Abstract: Described are methods and apparatuses for the electrochemical generation and constant concentration delivery of high purity gases used in the production of semiconductors and the doping of semiconductors.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: July 20, 1999
    Assignee: Electron Tranfer Technologies
    Inventor: William M. Ayers
  • Patent number: 5895530
    Abstract: A method and apparatus for directing a process gas through a wafer processing apparatus, such as a vapor deposition chamber is provided. The apparatus comprises a pumping plate (4) defining a central opening (62) surrounding the wafer (W) and having an upper surface (64) facing the processing chamber (12) and a opposite, lower surface (66) facing a pumping channel (14). The plate defines a plurality of circumferentially spaced gas holes (90) extending between the first and second surfaces for discharging process gases from the chamber into the pumping channel. The gas holes are essentially straight so that they flow directly through the pumping plate, thereby minimizing the residence time of the gases within the processing chamber and reducing the time required to clean the gas holes. In addition, the gas holes extend in a radially outward direction relative to the central opening to substantially uniformly discharge the gas from the processing chamber.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: April 20, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Ashish Shrotriya, Todd C. Bryant
  • Patent number: 5879970
    Abstract: Polycrystalline silicon-germanium alloy is grown on a glass substrate through a chemical vapor deposition under the conditions where the substrate temperature ranges from 350 degrees to 450 degrees in centigrade, the ratio between gas flow rate of Si.sub.2 H.sub.6 and the gas flow rate of GeF.sub.4 ranges from 20:0.9 to 40:0.9 and the dilution gas is selected from the group consisting of helium, argon, nitrogen and hydrogen, and the composition ratio of silicon of the polycrystalline silicon-germanium is equal to or greater than 80 percent so that the carrier mobility is drastically improved.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: March 9, 1999
    Assignee: NEC Corporation
    Inventors: Kunihiko Shiota, Jun-ichi Hanna
  • Patent number: 5856240
    Abstract: Vacuum CVD chambers are disclosed which provide a more uniformly deposited thin film on a substrate. The chamber susceptor mount for the substrate is heated resistively with a single coil firmly contacting the metal of the susceptor on all sides, providing uniform temperatures across the susceptor mount for a substrate. A purge gas line is connected to openings in the susceptor outside of the periphery of the substrate to prevent edge and backside contamination of the substrate. A vacuum feed line mounts the substrate to the susceptor plate during processing. A refractory purge guide, or a plurality of placement pins, maintain a fixed gap passage for the purge gases to pass alongside the edge of the wafer and into the processing area of the chamber. An exhaust pumping plate improves the uniformity of exhaustion of spent gases from the chamber.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: January 5, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Ashok Sinha, Mei Chang, Ilya Perlov, Karl A. Littau, Alan F. Morrison, Lawrence Chung-Lai Lei
  • Patent number: 5789324
    Abstract: A uniform gas flow is provided at the surface of a planar device or wafer in a processing system having a substantially cylindrical chamber through which processing gases flow toward an asymmetrically located outlet port by using an appropriately disposed collar or baffle along the gas stream in the chamber in the plane of the surface of the planar device or wafer.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: August 4, 1998
    Assignee: International Business Machines Corporation
    Inventors: Anthony John Canale, Randy Dean Cox, Dennis Stanley Grimard, Tracy Charles Hetrick
  • Patent number: 5789309
    Abstract: A method for monocrystalline epitaxial deposition which reduces the occurrence of large area defects for chemical vapor depositions carried out at near atmospheric pressure. Reactant gas is passed over a semiconductor wafer in a reaction chamber to an exhaust in a conventional manner. A venturi tube in fluid communication with the reaction chamber is adjusted to draw a vacuum pressure in the reaction chamber. The relatively small vacuum pressure produces a more laminar flow of reactant gas leaving the reaction chamber. Reduction in turbulence and eddy currents reduces the possibility that particles from matter deposited near the exhaust of the reaction chamber can be transported upstream in the gas flow onto the wafer, causing large area defects. A system for carrying out the method is also disclosed.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: August 4, 1998
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Lance G. Hellwig
  • Patent number: 5763326
    Abstract: A plasma etching process for cleaning laterally exposed p-n junctions of semiconductor elements, in particular power diodes after soldering together the semiconductor chip in question and connection elements is proposed, wherein the etching gases employed are fluorine compounds. Since the process according to the present invention does not involve doping dependence and crystal orientation dependence, it produces essentially vertically oriented chip-edges after etching and as a result a lower failure rate compared to the known wet-etching process. Since numerous rinsing processes can also be dispensed with, the plasma etching process is more suitable for mass production.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: June 9, 1998
    Assignee: Robert Bosch GmbH
    Inventor: Stephan-Manuel Barth
  • Patent number: 5665608
    Abstract: A method and apparatus for monitoring and controlling reactant vapors prior to chemical vapor deposition (CVD). The reactant vapors are monitored at full concentration without sampling as they are transported to a CVD reactor. Contaminants detected cause a process controller to switch the transport path to direct reactant vapors to a system pump.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: September 9, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Daniel Chapple-Sokol, Richard Anthony Conti, James Anthony O'Neill, Narayana V. Sarma, Donald Leslie Wilson, Justin Wai-Chow Wong
  • Patent number: 5662772
    Abstract: In a method for the selective removal of SiO.sub.2 relative to semiconductor materials and/or metal, a specimen to be processed and containing SiO.sub.2 is placed into a chamber having at least one gas admission opening and one gas outlet opening. Using controllable valves at the gas admission opening, dosed quantities of hydrogen fluoride gas and water vapor are admitted into the chamber. These gasses proceed to the SiO.sub.2 in a specimen in a quantity adequate for etching. However, the quantities of these gasses are limited such that a condensation of the water vapor to form liquid water on the specimen during the etching event is avoided. An etching event is then implemented. Water vapor that arises as a reaction product during the etching is eliminated through the gas outlet opening before the occurrence of condensation and, simultaneously, an inert gas is admitted into the chamber through the gas admission opening. These steps are repeated as needed.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: September 2, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Scheiter, Ulrich Naeher, Christofer Hierold
  • Patent number: 5631199
    Abstract: A furnace for manufacturing a semiconductor device and a method of forming a gate oxide film by utilizing the same is disclosed, which can decrease the budget of the device and improve the quality of the oxide film. First N.sub.2 O gas in a source furnace maintained at a high temperature. This eliminates factors contributing to poor quality. These factors include the increase of H.sub.2 generated as a result of the difference in the resolving temperatures of N.sub.2 O and NH.sub.3 in the oxidization process. Also, the invention results in the oxidizing a selected portion of a wafer by making N.sub.2 O and NH.sub.3 react in the main furnace maintained at low temperature.
    Type: Grant
    Filed: July 7, 1995
    Date of Patent: May 20, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Mi Ra Park
  • Patent number: 5622595
    Abstract: Contaminant particles in a vacuum plasma processing chamber can be removed from the surface of a substrate in the chamber by first reducing the pressure in the chamber so as to elevate the particles above any obstruction about the substrate, including a clamping ring and the like, maintaining a plasma from a gas fed to the chamber so that the particles are in the plasma, and then increasing the gas flow to the chamber so as to sweep the particles out of the chamber through the exhaust system of the processing chamber while maintaining a plasma in the chamber.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: April 22, 1997
    Assignee: Applied Materials, Inc
    Inventors: Anand Gupta, Joseph Lanucha
  • Patent number: 5618349
    Abstract: A process tube is surrounded by a heater. A number of gas inlet holes and a number of gas outlet holes are formed in the side wall of the process tube, the gas inlet and outlet holes facing each other and formed distributed in the longitudinal direction of the process tube. An oxidizing gas is supplied from a gas supply pipe to the gas inlet holes, and exhausted to a gas exhaust pipe via the gas outlet holes or lower gas outlet holes.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: April 8, 1997
    Assignee: Yamaha Corporation
    Inventor: Tomohiro Yuuki