Abstract: The present disclosure provides a touch panel, including at least a plurality of first electrode axes, a plurality of second electrode blocks. Each first electrode axis and corresponding second electrode block are disposed at the same level, staggered and electrically isolated from each other. Each first electrode axis is an uninterrupted structure. The touch panel of the present disclosure provides a new electrode pattern, and since all electrodes are disposed at the same level, therefore the electrodes can be formed simultaneously, thereby decreasing the cost of manufacturing process.

Abstract: An arrangement (1) for holding a substrate (10) in a material deposition apparatus, which substrate (10) has a deposition side (10a) upon which material (M) is to be deposited, and which arrangement (1) comprises: a shadow mask (20) comprising a number of deposition openings (Di); a support structure (30) comprising a number of surround openings (Si); and a support structure holding means (6) for holding the support mask (30) and/or a substrate holding means (5) for holding the substrate (10), such that the support structure (30) is on the same side as the deposition side (10a) of the substrate (10), and the shadow mask (20) is positioned between the substrate (10) and the support structure (30) such that at least one deposition opening (Di) of the shadow mask (10) lies within a corresponding surround opening (Si) of the support structure (30).

Abstract: A deposition mask 601 is used to form a thin film 3 in a prescribed pattern on a substrate 10 by deposition. Each of a plurality of improved openings 62A of the deposition mask 601 has a protruding opening portion 64, and is formed so that the opening amount at an end in a lateral direction is larger than that in a central portion in the lateral direction. In a deposition apparatus 50, the deposition mask 601 is held in a fixed relative positional relation with a deposition source 53 by a mask unit 55. In the case of forming the thin film 3 in a stripe pattern on the substrate 10 by the deposition apparatus 50, deposition particles are sequentially deposited on the substrate 10 while relatively moving the substrate 10 along a scanning direction with a gap H being provided between the substrate 10 and the deposition mask 601.

Abstract: An arrangement (1) for holding a substrate (10) in a material deposition apparatus, which substrate (10) has a deposition side (10a) upon which material (M) is to be deposited, and which arrangement (1) comprises: a shadow mask (20) comprising a number of deposition openings (Di); a support structure (30) comprising a number of surround openings (Si); and a support structure holding means (6) for holding the support mask (30) and/or a substrate holding means (5) for holding the substrate (10), such that the support structure (30) is on the same side as the deposition side (10a) of the substrate (10), and the shadow mask (20) is positioned between the substrate (10) and the support structure (30) such that at least one deposition opening (Di) of the shadow mask (10) lies within a corresponding surround opening (Si) of the support structure (30).

Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.

Abstract: A mask device, a method of fabricating the mask device with improved reliability, a method of manufacturing a large-sized division mask device by forming a striped aperture parallel to the roll direction, and a method of fabricating an organic light emitting display device (OLED) using the mask device. The mask device includes: at least one mask alignment mark formed on a mask; a blocking region formed on the mask and blocking a deposition material; and an aperture region formed on the mask and through which the deposition material passes, wherein the at least one mask alignment mark is formed outside the aperture region, the aperture region has a stripe pattern, and the roll direction of the mask substrate is parallel to the longitudinal direction of the stripe pattern.

Abstract: A system and method for providing an active array of temperature sensing and cooling elements, including an active heatsink which further includes an active temperature sensing layer, a thermoelectric cooling layer, and a heatsink, which further includes a plurality of cooling channels. The temperature sensing element within the active temperature sensing layer includes a plurality of switching transistors, a linear transistor, a current sense resistor, a thermistor, a voltage sensing bus, a voltage setting bus, a current measurement bus, a measurement switching bus, a sense control bus, a storage capacitor, and a supply voltage, all under the control of a process control computer. The method of using an active array of temperature sensing and cooling elements includes the steps of aligning the shadow mask, depositing the material, detecting a thermal gradient, and controlling the thermoelectric cooling.

Abstract: A photoelectric conversion device comprising: a semiconductor substrate; an inorganic photoelectric conversion layer provided within the semiconductor substrate; and an organic photoelectric conversion layer provided above the inorganic photoelectric conversion layer, wherein the organic photoelectric conversion layer is prepared by a shadow mask method.

Abstract: A method of fabricating organic solar arrays for application in DC power supplies for electrostatic microelectromechanical systems (MEMS) devices. A solar array with 20 miniature cells (as small as 1 mm2) interconnected in series is fabricated and characterized. Photolithography is used to isolate individual cells and output contacts of the array, whereas the thermal-vacuum deposition is employed to make the series connections of the array. With 1 mm2 for single cell and a total device area of 2.2 cm2, the organic solar array based on bulk heterojunction structure of ?-conjugated polymers and C60 derivative (6,6)-phenyl C61 butyric acid methyl ester produces an open-circuit voltage of 7.8 V and a short-circuit current of 55 ?A under simulated air mass (AM) 1.5 illumination with an intensity of 132 mW/cm2. The present method can be used in the fabrication of microarrays as small as 0.01 mm2.

Abstract: In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.

Abstract: Aimed at suppressing roughening in a circumferential portion of a layer to be etched in the process of removing a hard mask formed thereon, an etching apparatus of the present invention has a process chamber, an electrode, a stage, and a shadow ring, wherein the process chamber allows an etching gas to be introduced therein; the electrode is disposed in the process chamber, and is used for generating plasma by ionizing the etching gas; the stage is disposed in the process chamber, onto which a substrate is disposed; the shadow ring has an irregular pattern on the inner circumferential edge thereof, and is disposed in the process chamber and placed above the stage 30, so as to cover a circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner.

Abstract: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

Abstract: A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.

Abstract: The invention relates to a self-adjusting serial connection of thin layers and a method for the production thereof. The invention is characterized in that electrically conducting conductor tracks (20) are applied to a substrate (10), whereupon several main deposit layers (30, 40, 50) of conducting, semi-conducting or insulating materials are applied to the substrate. The application of the layers is carried out at various angles of incidence to the surface of the substrate.

Abstract: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer using a first implanting mask adjacent to the first side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess.

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract: The invention relates to a method for the production of automatically adjusting serial connections of thick and/or thin layers. The method comprises the following process steps: applying electrically conductive strip conductors (20) to a substrate (10); applying a first main layer (30) at an angle a relative to the surface of the substrate; applying a second main layer which is made of granular-shaped particles (40) to the substrate (10); applying several layers in conjunction with material and process-dependent processing steps; applying a third main layer (70) at an angle ? relative to the surface of the substrate; and applying a fourth main layer (80) at an angle y relative to the surface of the substrate.

Abstract: The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.

Abstract: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

Abstract: Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids.

Abstract: A thin film circuit is fabricated using a lithographic technique in combination with an inkjet printing technique. The lithographic technique, providing extremely high resolution, is used to fabricate transistor source and drain electrodes, parts of interconnections and circuit electrodes, enabling highly conductive materials to be used. Semiconductor regions, insulator regions, gate electrodes and other parts of the interconnections, and in particular interconnection cross-over points, are patterned using an inkjet printing technique. A variety of materials can be used in the inkjet printing technique and the alignment concerns associated with the use of multiple lithographic steps and, in particular, with the use of plastics substrates, are substantially alleviated.

Abstract: When an opening diameter of a top end of a substantially column-shaped contact hole is S1, an opening diameter of a top end of a substantially column-shaped contact hole is T1, and a thickness of a silicon insulating layer is h, then contact holes are formed so as to satisfy the following conditional expression 1. T1/h<tan &thgr;1<S1/h (expression 1). With this formation method, a manufacturing method of a semiconductor device can be provided which does not need covering processing using a photolithography technique when impurity regions of different conductivity types are formed using contact holes.

Abstract: A method facilitates the doping of fins of a semiconductor device that includes a substrate. The method includes forming fin structures on the substrate, where each of the fin structures includes a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first one of the fins with n-type impurities and performing a second tilt angle implant process to dope a second one of the fins with p-type impurities.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.

Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: A shadow mask is applicable to forming a minute film on a substrate by evaporation or the like. The shadow mask comprises a support film, a stopper film, a polyimide film and a thin plate.

Abstract: Upon formation of a layer such as an emissive layer of an organic EL element by attaching an emissive material onto a substrate (10), an evaporation mask (100) including an opening (110) corresponding to the layer formed to have a plurality of individual patterns and having an area, for example, smaller than the substrate is disposed between the substrate (10) and a material source (200). A relative position between the mask (100) and the material source (200), and the substrate (10) is slid by a predetermined pitch corresponding to the size of a pixel of the substrate (10), thereby forming a material layer (such as the emissive layer 64) in a predetermined region of the substrate. As a result, the material layer can be formed on the substrate through, for example, evaporation with a high accuracy.

Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving contacting the semiconductor structure including the resist with a plasma comprising at least one inert gas selected from the group consisting of nitrogen, helium, neon, argon, krypton and xenon; exposing the semiconductor structure including the resist to actinic radiation having a wavelength of about 160 nm or less through a lithography mask; and developing the resist with a developer.

Abstract: A method of depositing material on a substrate using a shadow mask. The mask includes a plurality of etched features which correspond to a plurality of features in the substrate. Spheres are provided in the features of the mask or substrate so that the mask and substrate are aligned when each of the spheres occupy both of the corresponding features in the mask and substrate.

Abstract: An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.

Abstract: The present invention overcomes the limitations of the prior art to allow for the creation of smaller components for use in logic circuits. The invention provides a new method of defining and forming features on a semiconductor substrate by using a layer of material, referred to as a shadow mandrel layer, to cast a shadow. A trough is etched in the shadow mandrel layer. At least one side of the trough will be used to cast a shadow in the bottom of the trough. A conformally deposited photoresist is used to capture the image of the shadow. The image of the shadow is used to define and form a feature. This allows for the creation of images on the surface of a wafer without the diffraction effects encountered in conventional photolithography. This allows for a reduced device size and increased chip operating speed.

Abstract: A method of manufacturing a shadow mask by making use of a coating apparatus, wherein a gravure roll 20 mm to 60 mm in diameter is disposed below a metallic thin plate and any supporting member is not disposed at an opposite side portion of the metallic thin plate to be contacted with the gravure roll. An etching resistant liquid is fed onto the gravure roll being rotated in a direction opposite to that of the metallic thin plate and at a peripheral speed of 4 to 25 times as high as that of a feeding speed of the metallic thin plate, and an excessive portion of the etching resistant liquid is wiped away by the doctor blade before the etching resistant liquid is transferred to the metallic thin plate thereby to form an etching resistant layer on the metallic thin plate.

Abstract: The present invention discloses a method for fabricating a MOSFET device supported on a substrate.

Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.

Abstract: A composite shadow ring for use in an etch chamber that does not generate contaminating oxygen gas when bombarded by a gas plasma and a method for using such composite shadow ring are presented. The composite shadow ring may have a structure of a body portion of a ring shape that is made of a material that is substantially of silicon dioxide and an insert portion which is intimately joined to the body portion and is adjacent to a plasma cloud in the etch chamber when the shadow ring is positioned juxtaposed to the wafer, the insert portion of the shadow ring may also have a ring shape and is eccentric with the body portion, it generally has a diameter smaller than a diameter of the body portion, the insert portion may be fabricated of a material that does not generate oxygen when bombarded by a fluorine-containing gas plasma. The body portion may have a crosssection of a rectangle which has an upper inner corner of the rectangle missing to form a cavity for receiving an insert member intimately therein.

Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.

Abstract: In order to facilitate resuming molecular beam epitaxy after etching a substrate or an epitaxial layer, the etching method is implemented in an ultra-high vacuum, and it consists in producing at least two simultaneous chemical beams converging towards the substrate or the layer, the beams being formed of substances, each of which is capable of reacting with elements of different types in the substrate or the layer so as to form volatile compounds. Application in particular to manufacturing photonic and optoelectronic components.

Abstract: A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa.

Abstract: A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event to diffuse an emitter region of the bipolar transistor. The emitter is diffused or implanted to a depth greater than the depth to which a source and a drain region of the MOSFET are diffused. By using only the base region and source/drain region masks, and developing in sequence, each of two coatings of photoresist applied on top of one another, an access opening to the emitter region is define solely by the co-location of openings in each of the two coatings, thereby allowing the emitter region to be separately and additionally implanted. The access to the base region for the additional implication is achieved using only a few additional photo-ops and not as a result of using an additional emitter mask.

Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.