Masking Patents (Class 438/942)
  • Patent number: 9040405
    Abstract: A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tom Hasche, Sven Beyer, Gerhard Lembach, Alexander Ebermann
  • Patent number: 8987008
    Abstract: The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tsai-Sheng Gau, Yao-Ching Ku
  • Patent number: 8975195
    Abstract: A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Todd Lukanc, Christopher Heinz Clifford, Tamer Coskun
  • Patent number: 8946078
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 3, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 8946089
    Abstract: Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Kim, Jae-Woo Nam, Chul-Ho Shin, Shi-Yong Yi
  • Patent number: 8912881
    Abstract: Methods and apparatus for visually authenticating an entity which displays a radio frequency identification (RFID) tag are disclosed. In one embodiment, an apparatus includes a locator that determines when a radio frequency (RF) receiver is present within a vicinity. The apparatus also includes a server configured to identify a security element and configured to obtain an information element associated with the RF receiver when the RF receiver is present within the vicinity, as well as a transmitter. The transmitter transmits a first representation of the security element to a display arrangement, a second representation of the security element to the RF receiver, and the information element to the RF receiver. The second representation of the security element is arranged to overlay the information element when the second representation of the security element and the information element are displayed.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: December 16, 2014
    Assignee: Cisco Technology, Inc
    Inventor: Michael O. Tjebben
  • Patent number: 8912103
    Abstract: A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a template stage, mounting a template substrate on the template stage, and scanning the template substrate with light from the light source in an exposure process in which the light passes through the reticle and impinges the template substrate at an oblique angle of incidence.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Seok Heo, Jeong-Ho Yeo
  • Patent number: 8895439
    Abstract: A method for forming a fine exposure pattern where a width and an interval of the pattern are each 1CD, by first exposing a photoresist by using an exposure mask where an interval ratio of a light shielding part and a light transmission part is 2CD:1CD to 4CD:1CD, and then second exposing the photoresist after the exposure mask is shifted at a predetermined interval, or second exposing the photoresist by using an exposure mask formed at a position where a light transmission part is shifted at a predetermined interval, and developing the photoresist, such that it is possible to form a display device having a pixel electrode including a plurality of fine branch electrodes having a smaller width and interval than a resolution of an exposure apparatus.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Woo-Seok Jeon, Jong Kwang Lee, Jin Ho Ju, Min Kang, Hoon Kang, Seung Bo Shim, Gwui-Hyun Park, Bong-Yeon Kim, Seon-II Kim
  • Patent number: 8895382
    Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Noriko Takagi, Hiroyuki Mori
  • Patent number: 8895453
    Abstract: A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Holger Schulze
  • Patent number: 8889562
    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ying Zhang
  • Patent number: 8883644
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Mirzafer K. Abatchev
  • Patent number: 8860184
    Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 8846525
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Patent number: 8828839
    Abstract: Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: David P. Brunco, Witold Maszara
  • Patent number: 8772166
    Abstract: Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Mark Kiehlbauch, Steve Kramer, John Smythe
  • Patent number: 8770143
    Abstract: The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: July 8, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Rick Endo, Kurt Weiner, Indranil De, James Tsung, Maosheng Zhao
  • Patent number: 8772183
    Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Chang Ming-Ching, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
  • Patent number: 8741781
    Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Ranjan Khurana, David Swindler, Jianming Zhou
  • Patent number: 8741776
    Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer. Forming a plurality of elongated protrusions in a third layer above the first and second layers. Forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. Forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho Wei De, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 8735297
    Abstract: A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: May 27, 2014
    Assignee: Sidense Corporation
    Inventor: Wlodek Kurjanowicz
  • Patent number: 8716133
    Abstract: A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Ryan O. Jung, Neal V. Lafferty, Yunpeng Yin
  • Patent number: 8709267
    Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chwen Yu, Fei-Gwo Tsai, Kai-Wen Cheng
  • Patent number: 8703000
    Abstract: A slimming method includes transferring an object to be processed on which a patterned carbon-containing thin film is formed into a process chamber in an oxidation apparatus; and oxidizing and removing the surface of the carbon-containing thin film by an oxidizing gas while supplying moisture into the process chamber, to reduce widths of the protruded portions on the pattern of the carbon-containing thin film.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 22, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Jun Sato, Masayuki Hasegawa
  • Patent number: 8679975
    Abstract: A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: March 25, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Barbara Will, Heribert Weber
  • Patent number: 8677929
    Abstract: Disclosed are methods and apparatus for masking of substrates for deposition, and subsequent lifting of the mask with deposited material. Masking materials are utilized that can be used in high temperatures and vacuum environment. The masking material has minimal outgassing once inside a vacuum chamber and withstand the temperatures during deposition process. The mask is inkjeted over the wafers and, after deposition, removed using agitation, such as ultrasonic agitation, or using laser burn off.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: March 25, 2014
    Assignee: Intevac, Inc.
    Inventors: Alexander J. Berger, Terry Bluck, Vinay Shah, Judy Huang, Karthik Janakiraman, Chau T. Nguyen, Greg Stumbo
  • Patent number: 8664042
    Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 4, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Patent number: 8658440
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 25, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
  • Patent number: 8652874
    Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: February 18, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhong L. Wang, Christopher J. Summers, Xudong Wang, Elton D Graugnard, Jeffrey King
  • Patent number: 8642428
    Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: February 4, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 8637363
    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a preliminary mask pattern on an etch target layer. The preliminary mask pattern includes wave line type patterns, and each of the wave line type patterns includes main pattern portions and connection bar pattern portions. Node separation walls are formed on sidewalls of the preliminary mask patterns. The etch target layer is etched using the node separation walls as etch masks to form through holes penetrating the etch target layer. Nodes are formed in respective ones of the through holes.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 28, 2014
    Assignee: SK hynix Inc.
    Inventor: Yong Soon Jung
  • Patent number: 8598038
    Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 3, 2013
    Inventors: Yves Morand, Thierry Poiroux
  • Patent number: 8592258
    Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 kgf, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 26, 2013
    Assignees: United Test and Assembly Center, Ltd., QIMONDA AG
    Inventors: Denver Paul C. Castillo, Bryan Soon Hua Tan, Rodel Manalac, Kian Teng Eng, Pang Hup Ong, Soo Pin Chow, Wolfgang Johannes Hetzel, Werner Josef Reiss, Florian Ammer
  • Patent number: 8557704
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David H Wells, Mirzafer K Abatchev
  • Patent number: 8513131
    Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chung-hsun Lin, Chun-chen Yeh
  • Patent number: 8513105
    Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: August 20, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Charles Baldwin, James Walter Blatchford
  • Patent number: 8491799
    Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung
  • Patent number: 8461054
    Abstract: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from the conductive layer, on the conductive layer; forming a photo-resist pattern of a fixed pattern on the mask layer; forming a mask pattern, which has an undercut shape to the photo-resist pattern, by etching the mask layer by use of the photo-resist pattern as an etching mask; removing the photo-resist pattern; and etching the conductive film by use of the mask pattern as an etching mask, to provide at least any one of the common electrode and the pixel electrode.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: June 11, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Kye-Chan Song, Jeong Oh Kim, Young Kwon Kang
  • Patent number: 8461005
    Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 11, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Huan-Ting Tseng, Chun-Hsien Huang, Hung-Chin Huang, Chen-Wei Lee
  • Patent number: 8450833
    Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: May 28, 2013
    Assignee: GlobalFoundries Inc.
    Inventor: Ryoung-han Kim
  • Patent number: 8440569
    Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: May 14, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Milind Weling, Abdurrahman Sezginer
  • Patent number: 8415257
    Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: April 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hartmut Ruelke, Volker Jaschke
  • Patent number: 8377766
    Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: February 19, 2013
    Assignee: AU Optronics Corp.
    Inventors: Chia-Ming Chang, Hsiang-Chih Hsiao
  • Patent number: 8372295
    Abstract: Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the invention use a self-templating or multilayer approach to induce ordering of a self-assembling block copolymer film to an underlying base film to produce a multilayered film having an ordered array of nanostructures that can be removed to provide openings in the film which, in some embodiments, can be used as a template or mask to etch openings in an underlying material layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8358010
    Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 22, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini
  • Patent number: 8350365
    Abstract: A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: January 8, 2013
    Assignee: Xilinx, Inc.
    Inventors: Yun Wu, Hong-Tsz Pan, Qi Lin, Bang-Thu Nguyen
  • Patent number: 8349645
    Abstract: A mask includes: a tabular first section which includes a side portion and an opening portion formed at a position corresponding to a film formation region of a substrate and on which the substrate is to be disposed so that the first section overlaps a face of the substrate on which a film is to be formed; and a second section which is provided along the side portion of the first section, and covers at least one of portions of a side face of the substrate, wherein second sections of two adjacent masks overlap each other and a superposed section is thereby formed when a plurality of masks are arrayed in a lateral direction thereof.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: January 8, 2013
    Assignee: Ulvac, Inc.
    Inventors: Miwa Watai, Kazuya Saito, Takashi Komatsu, Yusuke Mizuno, Atsushi Ota, Shunji Kuroiwa
  • Patent number: 8343861
    Abstract: An ion implantation method includes performing ion implantation a plurality of times using a plurality of ion implantation masks each including main mask portions, bridge portions connecting between the main mask portions, and openings corresponding to parts of annular regions where ions are to be implanted, whereby a plurality of annular ion-implanted regions are formed by combining the plurality of ion implantation masks.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: January 1, 2013
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 8336000
    Abstract: According to one embodiment, a method is disclosed for determining position of an auxiliary pattern on a photomask. The method can include generating a first set for each of three or more imaging positions of an exposure optical system. The method can include generating a second set for each of the three or more imaging positions by inverse Fourier transforming each of the first set. The method can include calculating a second order differential with respect to the imaging position of an index indicating amplitude of light belonging to the second set. In addition, the method can include extracting a position where the second order differential assumes an extremal value on an imaging plane of the exposure optical system. At least part of positions on the photomask each corresponding to the position assuming the extremal value on the imaging plane is used as a formation position of the auxiliary pattern.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Kai, Katsuyoshi Kodera
  • Patent number: 8298956
    Abstract: A method for fabricating a fine pattern includes forming a first photomask including first light transmission regions set in a line shape over a first phase shift mask (PSM) region and a first binary mask (BM) region adjacent to the first phase shift mask region. A second photomask may be formed to include second light transmission regions set in a line shape over a second phase shift mask region and a second binary mask region adjacent to the second phase shift mask region, wherein the second light transmission regions intersect the first light transmission regions. A resist layer may first be exposed using the first photomask and secondly exposed using the second photomask. The first and secondly exposed resist layer may be developed to form resist patterns with open regions corresponding to portions where the first light transmission regions intersect the second light transmission regions.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 30, 2012
    Assignee: SK Hynix Inc.
    Inventor: Hyun Jo Yang