Abstract: A III-nitride based quantum dot (QD) laser is formed of InGaN/GaN quantum dots and capable emitting at a single wavelength within the visible region, including the violet wavelength region (400-440 nm), the blue wavelength region (440-490 nm), the green wavelength region (490-570 nm), the yellow wavelength region (570-590 nm), the orange wavelength region (590-620 nm), and the red wavelength region (620-700 nm), with varying composition as described.

Abstract: A light-emitting element includes a n-type silicon oxide film and a p-type silicon nitride film. The n-type silicon oxide film and the p-type silicon nitride film formed on the n-type silicon oxide film form a p-n junction. The n-type silicon oxide film includes a plurality of quantum dots composed of n-type Si while the p-type silicon nitride film includes a plurality of quantum dots composed of p-type Si. Light emission occurs from the boundary between the n-type silicon oxide film and the p-type silicon nitride film by injecting electrons from the n-type silicon oxide film side and holes from the p-type silicon nitride film side.

Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

Abstract: Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Abstract: A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of quantum dots and organic molecules, and the emission spectra were resolved without significant signal rejection. Quantum dots were then conjugated with organic molecules and detected to demonstrate efficient multicolor detection. PCH was used to analyze coincident detection and to characterize the degree of binding. The use of a small fluidic channel to detect quantum dots as fluorescent labels was shown to be an efficient technique for multiplexed single molecule studies. Detection of single molecule binding events has a variety of applications including high throughput immunoassays.

Abstract: A gallium nitride substrate includes a plurality of physical level differences in a surface thereof. All the physical level differences existing in the surface have a dimension of not more than 4 ?m. A relationship of (H?L)/H×100?80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference.

Abstract: Provided are quantum dots having a gradual composition gradient shell structure which have an improved luminous efficiency and optical stability, and a method of manufacturing the quantum dots in a short amount of time at low cost. In the method, the quantum dots can be manufactured in a short amount of time at low cost using a reactivity difference between semiconductor precursors, unlike in uneconomical and inefficient conventional methods where shells are formed after forming cores and performing cleaning and redispersion processes. Also, formation of the cores is followed by formation of shells having a composition gradient.

Abstract: The present invention relates to growth of vertically-oriented crystalline nanowire arrays upon a transparent conductive or other substrate for use in 3rd generation photovoltaic and other applications. A method of growing crystalline anatase nanowires includes the steps of: deposition of titania onto a substrate; conversion of the titania into titanate nanowires; and, treatment of the titanate nanowires to produce crystalline anatase nanowires.

Abstract: In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: An optical semiconductor device includes a substrate; and an active layer disposed on the substrate, wherein the active layer includes a first barrier layer containing GaAs, a quantum dot layer, which is disposed on the first barrier layer, which includes a quantum dot containing InAs, which includes a side barrier layer which covers at least a part of the quantum dot and a side surface of the quantum dot, and having an elongation strain inherent therein, and a second barrier layer disposed on the quantum dot layer.

Abstract: The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.

Abstract: A method of forming an optoelectronic device. The method includes providing a deposition surface and contacting the deposition surface with a ligand exchange chemical and contacting the deposition surface with a quantum dot (QD) colloid. This initial process is repeated over one or more cycles to form an initial QD film on the deposition surface. The method further includes subsequently contacting the QD film with a secondary treatment chemical and optionally contacting the surface with additional QDs to form an enhanced QD layer exhibiting multiple exciton generation (MEG) upon absorption of high energy photons by the QD active layer. Devices having an enhanced QD active layer as described above are also disclosed.

Abstract: Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (120, 135) is associated with another material (130, 125) such as a metal. The carbon nanotube material facilitates the electrical connection between different circuit components.

Abstract: A vertically oriented nanometer-wires structure is disclosed. The vertically oriented nanometer-wires structure includes a non-crystalline base and many straight nanometer-wires. The straight nanometer-wires are uniformly distributed on the non-crystalline base, and the angle between each of the straight nanometer-wire and the non-crystalline base is 80-90 degrees. The straight nanometer-wires structure can be widely applied in semiconductor, optoelectronic, biological and energy field. What is worth to be noticed is that the non-crystalline base can be glass, ceramics, synthetic, resin, rubber or even metal foil, and the straight nanometer-wires and the non-crystalline base are still orthogonal to each other.

Abstract: The present invention relates to a quantum dot light emitting diode device in which a hole transportation layer is formed after forming a quantum dot light emitting layer by a solution process by applying an inverted type quantum dot light emitting diode device for making free selection of a hole transportation layer material that enables easy injection of a hole to the quantum dot light emitting layer; and display device and method therewith.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.

Abstract: Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

Abstract: Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.

Abstract: Provided herein are embodiments of a three-dimensional bicontinuous heterostructure, a method of producing same, and the application of this structure. The three-dimensional bicontinuous heterostructure includes two interpenetrating layers which are spatially continuous, include only protrusions or peninsulas, and have no islands. The method of producing the three-dimensional bicontinuous heterostructure includes forming an essentially planar continuous bottom layer of a first material; forming a layer of this first material on top of the bottom layer that is textured to produce protrusions for subsequent interpenetration with a second material, coating this second material onto this structure, and forming a coating with the second material that ensures that only the second material is contacted by subsequent layer. One of the materials includes visible and/or infrared-absorbing semiconducting quantum dot nanoparticles, and one of materials is a hole conductor and the other is an electron conductor.

Abstract: The disclosure concerns a microelectronic device provided with one or more <<quantum wires>>, able to form one or more transistor channels, and optimized in terms of arrangement, shape or/and composition. The invention also uses a method for fabricating said device, comprising the steps of: the forming, in one or more thin layers resting on a support, of a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, and of a structure connecting the first block to the second block, and the forming, on the surface of the structure, of wires connecting a first region of the first block with another region of the second block which faces the first region.

Abstract: A process for forming nanostructures comprises generating charged nanoparticles with an electrospray system and introduction of the charged nanoparticles to a substrate, so that the particles adhere to the substrate in order to form the desired structure. The charged nanoparticles may be directed to a target position by at least one deflector in the electrospray apparatus, which may also include a column optic system. The adhered nanoparticles may be sintered to form the structure. The electrospray apparatus may be single source, multi-source injection, or multi-source selection. An array of electrospray apparatuses with deflectors may be used concurrently to form the structure.

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: The present invention provides a “microminiaturizing method of nano-structure” with fabricating process steps as follows: First deposit the material of molecule or atom state on the top-opening of the nano cylindrical pore, which having formed on the substrate, so that the diameter of said top-opening gradually reduce to become a reduced nano-aperture, whose opening diameter is smaller than that of said top-opening; Then, directly pass the deposit material of gas molecule or atom state through said reduced nano-aperture; thereby a nano-structure of nano quantum dot, nano rod or nano ring with smaller nano scale is directly formed on the surface of said substrate, which being laid beneath the bottom of said nano cylindrical pore.

Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.

Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.

Abstract: Methods for the site-selective growth of horizontal nanowires are provided. According to the methods, horizontal nanowires having a predetermined length and diameter can be grown site-selectively at desired sites in a direction parallel to a substrate to fabricate a device with high degree of integration. Further provided are nanowires grown by the methods and nanodevices comprising the nanowires.

Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method including the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.

Abstract: A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

Abstract: There is provided a method for epitaxial growth, wherein a quantum dot is formed on an epitaxial layer using a quantum-dot forming material with an excellent lattice matching property, and the formed quantum dot is positioned on a defect in the epitaxial layer, thereby minimizing transfer of the defect into an epitaxial layer formed through a subsequent process. The method includes preparing a first epitaxial layer having a defect formed therein; coating an anti-surfactant on the first epitaxial layer; supplying a quantum-dot forming material lattice-matched with respect to the first epitaxial layer, thereby forming a quantum dot obtained by allowing the anti-surfactant to react with the quantum-dot forming material on the first epitaxial layer; allowing the quantum dot to be moved onto a step of the first epitaxial layer due to a difference of surface energies between the quantum dot and the first epitaxial layer; and growing a second epitaxial layer on the first epitaxial layer.

Abstract: An example quantum dot (QD) device comprises a QD layer on a substrate, and may be fabricated by aerosol deposition, for example by mist deposition. An example approach includes providing a liquid precursor including QDs dispersed in a liquid carrier, generating a mist of droplets of the liquid precursor, directing the droplets towards the substrate so as to form a liquid precursor film on the substrate, and removing the liquid carrier from the liquid precursor film to form the quantum dot layer on the substrate. Example devices include multi-color QD-LED (light emitting diode) displays, and other devices.

Abstract: Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.

Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.

Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.

Abstract: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract: The present disclosure generally relates to techniques for controlled quantum dot growth as well as a quantum dot structures. In some examples, a method is described that includes one or more of providing a substrate, forming a defect on the substrate, depositing a layer on the substrate and forming quantum dots along the defect.

Abstract: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T1, and the barrier layers are formed at a growth temperature T2, where T1<T2. Then, a second type doped semiconductor layer is formed on the light emitting layer.

Abstract: Novel phase-separation behavior by a mixture, including binary mixture, of patterning compounds, including alkanethiols, when deposited onto a surface, including a gold surface, using micro and nano-deposition tools such as tip and stamp methods like micro-contact printing (?CP), and Dip-Pen Nanolithography (DPN). This behavior is significantly different than that observed in the bulk. This behavior was demonstrated using three examples of compounds: 16-mercaptohexadecanoic acid (MHA), 1-octadecanethiol (ODT), and CF3(CF2)11(CH2)2SH (PFT). The identity of the resulting segregated structure was confirmed by lateral force microscopy (LFM), and by selective metal-organic coordination chemistry. This phenomenon is exploited to print sub-100 nm wide alkanethiol features via conventional ?CP and to form sub-15 nm features using DPN printing, which is below the ultimate resolution of both these techniques. These nano-patterned materials also can serve as templates for constructing more complex architectures.

Abstract: The present invention provides a method for the controlled synthesis of nanostructures on the edges of electrodes and an apparatus capable of optical and electrochemical sensing. In accordance with the present invention, a method of fabricating nanowires is provided. In one embodiment, the method includes providing a substrate, creating a dielectric thereon, depositing a metal catalyst on the dielectric, patterning the metal catalyst, selectively etching dielectric, creating an electric field originating in metal catalyst, and applying a heat treatment. In another embodiment, the method includes providing a substrate, depositing a dielectric thereon, printing a metal catalyst on the dielectric and plastic substrate, printing silicide along the edges of metal catalyst, creating an electric field originating in metal catalyst; and applying chemical vapor deposition.

Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.

Abstract: A light-emitting device includes an n-type silicon thin film (2), a silicon thin film (3), and a p-type silicon thin film (4). The silicon thin film (3) is formed on the n-type silicon thin film (2) and the p-type silicon thin film (4) is formed on the silicon thin film (3). The n-type silicon thin film (2), the silicon thin film (3), and the p-type silicon thin film (4) form a pin junction. The n-type silicon thin film (2) includes a plurality of quantum dots (21) composed of n-type Si. The silicon thin film (3) includes a plurality of quantum dots (31) composed of p-type Si. The p-type silicon thin film (4) includes a plurality of quantum dots (41) composed of p-type Si. Electrons are injected from the n-type silicon thin film (2) side and holes are injected from the p-type silicon thin film (4) side, whereby light is emitted at a silicon nitride film (3).

Abstract: There is provided a semiconductor light-emitting element and a method of producing the same including high density and high quality quantum dots emitting light at a wavelength of 1.3 ?m. A semiconductor light-emitting element has a first GaAs layer, a second InAs thin film layer having the plurality of InAs quantum dots formed on the first GaAs layer, a third InGaAs layer formed on the second InAs thin film layer having the plurality of InAs quantum dots, and a fourth GaAs layer formed on the third InGaAs layer, wherein the As source is As2.

Abstract: A method of making a quantum dot memory cell, the quantum dot memory cell including an array of quantum dots disposed between a first electrode and a second electrode, includes obtaining values for a tunneling current through the quantum dot memory cell as a function of a voltage applied to the quantum dot memory cell and selecting parameters of the quantum dot memory cell such that the tunneling current through the quantum dot memory cell exhibits a bistable current for at least some values of the voltage applied to the quantum dot memory cell. The values for the tunneling current are determined on the basis of a density of states of the array of quantum dots.

Abstract: Method of manufacturing an optical device, and an optical device, the optical device having one or more layers (13) of quantum-dots located in-between barrier layers (12). A spacer layer (15) is grown on a barrier layer (12), such that the spacer layer (15) is adapted for substantially blocking strain fields induced by quantum-dot layers, thereby producing a smooth growth front for a subsequent barrier layer (12).