Abstract: A method that includes, obtaining a substrate, placing a reinforcing layer over a first side of the substrate; and thinning the substrate by removing material from an opposite side of the substrate.

Abstract: A method of adjusting the threshold voltage in an ultra-thin SOI MOS transistor includes preparing a SOI substrate; thinning the SOI top silicon film to a thickness of between about 10 nm and 50 nm; forming an absorption layer on the top silicon film; and implanting ions into the top silicon film through the absorption layer.

Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.

Abstract: A method of transferring a thin film device onto a plastic sheet. A silver-containing buffer layer is formed on a glass substrate. A transferred layer including a thin film device is formed on part of the silver-containing buffer layer. At least one first hole penetrates the transferred layer and an edge of the silver-containing buffer layer is exposed. A first plastic layer including at least one second hole is adhered to the transferred layer with a removable glue, wherein the second hole corresponds to the first hole, and part of the first plastic layer is located above the edge of the silver-containing buffer layer. The silver-containing buffer layer is oxidized to expand, thereby separating the silver-containing buffer layer from the transferred layer. A second plastic layer is adhered to the transferred layer. The removable glue is eliminated to remove the first plastic layer.

Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electro-magnetic radiation.

Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

Abstract: Methods are disclosed for manufacturing semiconductor device dies and for separating dies from a semiconductor wafer, wherein one or more channels are etched in the top of the wafer between individual die areas. Material is then removed from the bottom side of the wafer in order to separate the individual dies. Methods are also disclosed for removing material from the bottom side of the wafer dies, wherein a contoured surface is provided on the die bottom, such as through an etching process. In addition, methods are disclosed for removing material from the bottom side of a wafer, and for securing a semiconductor device to a surface. Semiconductor wafers and dies are also disclosed having contoured bottom surfaces.

Abstract: The separation method of a semiconductor layer according to the present invention comprises separating a semiconductor layer and a semiconductor substrate at a separation layer formed therebetween, wherein a face of the semiconductor layer at the side opposite to the separation layer and/or a face of the semiconductor substrate at the side opposite to the separation layer are held by utilizing an ice layer, whereby it is unnecessary to use an adhesive as holding means and at the same time it is possible to easily and uniformly separate them.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A compound semiconductor substrate is manufactured by forming a higher-quality compound semiconductor layer having a smaller number of crystalline defects on a single-crystal substrate, and removing the single-crystal substrate without causing damage to the compound semiconductor layer. The method comprises the steps of forming the compound semiconductor layer (first, second and third compound semiconductor layers) on the single-crystal substrate (sapphire substrate) through crystal growth so as to partially have a space between the compound semiconductor layer and the single-crystal substrate; and removing the compound semiconductor layer from the sapphire substrate by irradiating the compound semiconductor layer from a side of the sapphire substrate with a laser beam passing through the single-crystal substrate and being absorbed in the compound semiconductor layer to melt an interface between the single-crystal substrate and the compound semiconductor.

Abstract: A method for fabricating LGA-, LCCY- and BGA-types of very thin, chip size semi-conductor packages (“VCSP's”) includes substantially reducing the thickness of a semiconductor wafer containing the semiconductor chips to be packaged by grinding and/or etching the wafer from its back side prior to singulation of the chips from the wafer. The thinned-down chips thus produced are electrically connected to corresponding insulative substrates contained in an integral array thereof using the “flip chip” interconnection method. The narrow row space between the chips and the substrates are sealed with an underfill material, and the individual, finished VCSP's are then singulated from the array.

Abstract: A process for the production of an electric part, comprising performing a circuit-parts-forming step including the introduction of impurities on one surface (surface A) of a semiconductor substrate, then bonding the surface A to a holding substrate, performing a back surface treatment step essentially including a polishing of an exposed surface (surface B) of the semiconductor substrate to a thickness of 100 &mgr;m or less to obtain an electric-part-formed thinned substrate and separating the thinned substrate from the holding substrate, wherein a resin composition containing a swelling inorganic compound (WC) is used for an adhesion layer and in the separating step the thinned substrate is separated from the holding substrate after decreasing the adhesive strength of the thinned substrate and the holding substrate by swelling the swelling inorganic compound (WC).

Abstract: A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer of top silicon formed thereon, includes growing a gate oxide layer on the top silicon layer; depositing a first layer of material on the gate oxide layer; removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region; forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer; depositing a second layer of material over the first layer of material and the insulating cup; etching the first layer of material and the second layer of material to form a gate electrode; implanting ions to form a source region and a drain region; passivating the structure; and metallizing the structure.

Abstract: The invention relates to a semiconductor structure that is formed by delaminating a semiconductor substrate and by bonding the top section of the substrate to a transfer substrate. Delaminating is carried out by causing a polymer film to achieve greater adhesion that an embrittlement layer in the semiconductor substrate.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 &mgr;m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: Semiconductor chips are mounted on a multilayer wiring of a silicon carrier substrate, while the bottom side of the carrier substrate is provided with soldering contacts in the form of solder balls and is structured in such a way that for each soldering contact a cavity, which extends through the silicon carrier substrate and is filled by the respective solder ball, is formed, so that the solder ball itself makes contact with the multilayer wiring. In this configuration, at least the side walls of the cavity are lined with an insulating material. The insulating layer is applied prior to the application of the multilayer wiring to the structured silicon carrier substrate.

Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the expitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.

Abstract: A method and apparatus comprising thinning a substrate sufficiently to allow it to be mechanically compliant with a material deposited on its surface is disclosed. The mechanical compliance allows a reduction in the interlayer stress generated by dissimilarities in the materials.

Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.

Abstract: A method for transferring layers containing semiconductor devices and/or circuits to substrates other than those on which these semiconductor devices and/or circuits have been originally fabricated. The method comprises fabricating the semiconductor devices and/or circuits, coating them with a protective layer of photoresist followed by coating with a layer of wax. A special perforated structure is then also wax coated and the waxed surface of the structure is brought into a contact with the waxed surface of photoresist. The original seed substrate is removed and the exposed surface is then coated with adhesive followed by dissolving wax through the openings in the perforated structure and attaching the layer with semiconductor devices and/or circuits to another permanent substrate. As an alternative, a disk-shaped water-soluble structure can be used instead of the perforated structure.

Abstract: A method for placing nitride laser diode arrays on a thermally and electrically conducting substrate is described. The method uses an excimer laser to detach the nitride laser diode from the sapphire growth substrate after an intermediate substrate has been attached to the side opposite the sapphire substrate. A secondary layer is subsequently deposited to act as a transfer support structure and bonding interface. The membrane is released from the intermediate substrate and a thermally conducting substrate is subsequently bonded to the side where the sapphire substrate was removed. Similarly, the secondary layer may be used as the new host substrate given an appropriate thickness is deposited prior to removal of the intermediate substrate.

Abstract: A method of separating two layers of material from one another in such a way that the two separated layers of material are essentially fully preserved. An interface between the two layers of material at which the layers of material are to be separated, or a region in the vicinity of the interface, is exposed to electromagnetic radiation through one of the two layers of material. The electromagnetic radiation is absorbed at the interface or in the region in the vicinity of the interface and the absorbed radiation energy induces a decomposition of material at the interface.

Abstract: The present invention provides a method for forming a semiconductor device with a metal substrate. The method includes providing at least one semiconductor substrate; forming at least one semiconductor layer on the semiconductor substrate; forming the metal substrate on the semiconductor substrate and then removing the semiconductor substrate. The metal substrate has advantages of high thermal and electrical conductivity that can improve the reliability and lifetime of the semiconductor device.

Abstract: To be capable of arbitrarily designing an interconnection shape of a surface layer to thereby promote reliability of connection in laminating layers and making destruction of a semiconductor element difficult to cause in a semiconductor apparatus having interconnections for connecting laminated layers on a surface and a back of a substrate and capable of laminating layers in multiple stages, a semiconductor apparatus is fabricated by a step of mounting a semiconductor element in a recess portion shallower than a thickness of a semiconductor element formed in a surface of a substrate having interconnection patterns connected by a through hole on two of the surface and a back in which a thickness of an interconnection on the surface is made thicker than a thickness of an interconnection on the back with a front thereof disposed on the lower side, a step of sealing the semiconductor element in the recess portion by synthetic resin and a step of grinding the substrate and the semiconductor element up to the inter

Abstract: A method of forming a thin-piece sample for use in an electron microscope. The ion beam scanning used for etching a sample block to form a thin-wall portion is initiated from the outer perimeter of two opposite sides of the sample block to be formed, one side at a time, and the ion beam is directed from the outer perimeter of the sample block inwards towards the center of the sample block. When the two sides of the sample block are etched from the outside into the sample block, a thin wall is produced at the interior portion of the sample block. Also, a plurality of samples may be set in a known positional relationship, and a series of forming functions, including ion beam scanning, may be programmed for automation, allowing a plurality of samples to be formed all at one time easily and efficiently.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: In a method for fabricating a silicon-on-insulation wafer having fully processed devices in its upper-most silicon layer, the wafer is reduced in thickness from a surface opposite to the device layer surface by performing a first etching step of etching the semiconductor substrate to the insulation layer, so that the insulation layer functions as an etch stop layer, and a second etching step of etching the insulation layer to the semiconductor device layer, so that the semiconductor device layer functions as an etch stop layer. The semiconductor device layer is then separated into individual chips for fabricating a three-dimensionally integrated circuit thereof.

Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.

Abstract: A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then the wafer backside is etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and corners. The grooves' aspect ratio is large to reduce the lateral etch rate of the chip sidewalls and thus allow more area for on-chip circuitry.

Abstract: A method of smoothing a silicon surface formed on a substrate. According to the present invention a substrate having a silicon surface is placed into a chamber and heated to a temperature of between 1000°-1300° C. While the substrate is heated to a temperature between 1000°-1300° C., the silicon surface is exposed to a gas mix comprising H2 and HCl in the chamber to smooth the silicon surface.

Abstract: The invention provides a thin-film transferring method, which can separate a thin film from a supply substrate and transfer it to a demand substrate. The method is practiced first by a process of ion implantation, which implants ions in a supply substrate to form an ion separation layer under implanted surface, and then followed by a wafer-bonding method, which joins the supply substrate with a demand substrate. The resulting bonded structure is to be going through a high-energy ion activation activity, in which the implanted ions incorporate into aerial particles, which fill the cleaves, resulting in a separation film, which is to be transferred to the demand substrate in wafer bonding process. As a part of this invention, the cooling device can remove the heat current produced from the high-energy ion activation, so as to prevent the bonded structure—made from different materials—being damaged by heat due to the different thermal expansion coefficient.

Abstract: A method for reducing microsteps on an epitaxial layer deposited on a polished semiconductor wafer substrate by post-epitaxial thermal oxidation. The method produces very smooth semiconductor wafers by performing the steps of depositing an epitaxial layer on a wafer substrate, oxidizing a top portion of the epitaxial layer, and removing the oxidized top portion. As a result, the wafer's surface presents little or no microsteps thereon.

Abstract: A method of fabricating a semiconductor device includes the steps of, after sawing a semiconductor substrate into individual semiconductor chips in a state that the semiconductor substrate is covered by an adhesive tape, applying a dry gas to the adhesive tape in a state that the adhesive tape carries thereon the semiconductor chips, applying an infrared radiation to the adhesive tape in a state that the adhesive tape carries thereon the semiconductor chips and curing the adhesive layer on the adhesive tape in a state that the adhesive tape carries thereon the semiconductor chips, by irradiating a ultraviolet radiation to the adhesive tape, wherein the step of applying the dry gas, the step of applying the infrared radiation and the said step of curing the adhesive layer are conducted substantially simultaneously.

Abstract: N+ or P+ diffusions are formed in a lightly doped P type or N type starting wafer. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) diffusions. The trenches extend through the thin device layer to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of the tubs. At least one diffusion of each cell is connected to a diffusion of an adjacent cell to connect each of a predetermined number of the cells. The N+ or (P+) diffusions may be each enclosed by a ring shaped P+ or N+ contact diffusion. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.

Abstract: The invention relates to a method of separating into two wafers (2,4) a plate (1) of material for manufacturing substrates for electronics, optics, or optoelectronics, or for manufacturing microsystems, said wafers being situated on either side of a plane of weakness (6), the method being characterized in that it comprises the steps consisting in: exerting a deformation force on at least one of the wafers so as to cause the wafers (2, 4) to separate from each other in a zone of the plate (1) at said plane of weakness; and exerting guided separation movement on the wafers (2, 4). The invention also provides apparatus (100) for implementing the method, which apparatus has gripping members (30, 32) suitable for exerting said deformation force and for performing said separation.

Abstract: A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions.

Abstract: A wafer having a rounded edge is thinned to 100 microns or less, producing a tapered razor like edge. The edge is ground to blunt it and reduce danger to personnel and equipment during handling of the wafer.

Abstract: A method for the fine tuning of a passive electronic component having at least a carrier substrate and at least one electrically conducting layer containing a material having a conducting nitride, a conducting oxynitride, a semiconductor, or chromium, by means of a focused laser emission, which laser emission induces a heating effect which heating effect causes the material to be converted to a locally electrically non-conducting material.

Abstract: The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Abstract: A process for producing a large number of semiconductor chips from a semiconductor wafer having a large number of rectangular areas defined by streets arranged on the front surface in a lattice form, semiconductor circuits being formed in the respective rectangular areas. This process comprises the steps of forming a plurality of grooves having a predetermined depth in the back surface of the semiconductor wafer, grinding the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer to a predetermined value and thereafter, cutting the semiconductor wafer along the streets to separate the rectangular areas from one another to obtain semiconductor chips.

Abstract: An object of this invention is to provide a substrate processing method capable of satisfactorily performing in etching in the step of removing a porous silicon layer by etching.

Abstract: The invention concerns a method for treating substrates, in particular semiconductors, by implanting atoms so as to produce a substrate of cavities at a controlled depth, characterized in that it comprises steps which consists in: implanting atoms in the substrate at a first depth, to obtain a first concentration of atoms at said first depth; implanting atoms in the substrate at a second depth, different from the first, to obtain at said second depth, a second concentration of atoms, lower than the first; carrying out on the substrate a treatment for causing at least part of the atoms implanted in said second depth to migrate towards the first depth so as to create the cavities at the first depth preferably.

Abstract: A method of fabricating devices incorporating microelectromechanical systems (MEMS) using UV curable tapes includes providing a silicon substrate 12 with a MEMS layer 14 arranged on one side of the substrate 12. A first UV curable tape 22 is applied to the MEMS layer 14. At least one operation is performed on the substrate 14 via an opposed side of the substrate 14. A second UV curable tape 32 is applied to the opposed side of the substrate 14 and the first tape 22 is removed by exposing it to UV light. At least one operation is performed on the MEMS layer to form individual MEMS chips which are able to be removed individually from the second UV tape 32 by localized exposure of the tape 32 to UV light.

Abstract: The present invention provides new and improved methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is optionally grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film or an upper portion of the semiconductor substrate is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices.

Abstract: This invention is to manufacturing of SOI (Silicon On Insulator) wafer; with respect to manufacturing of SOI wafer, preparation process of silicon wafer with desired thickness (100), deposition of Alumina(Al2O3) as insulator by an ALE (Atomic Layer Epitaxial) method such as ALCVD, ALD, ASCVD, etc . . . (110), bonding of this wafer with another silicon wafer by various bonding methods (120), Cutting of this bonded wafer by various methods of cutting(130), Polishing the surface of the cut wafer (140). For the insulator material, titanium oxide (TiO2) or tantalum oxide(Ta2O5) can be used other than Alumina(Al2O3) and such bonding process can be done by unibonding method and cutting method can be done by Smart Cut process.

Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.

Abstract: A system and method provides for effective analysis of an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, the system includes a system (e.g., a nanomachining arrangement) adapted to remove a selected portion of the backside of a semiconductor device having SOI structure, and to electrically isolate a selected portion of circuitry on the SOI semiconductor device circuitry side. The isolated circuitry then is analyzed.