Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.

Abstract: A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate semiconductor dice may be formed upon a surface thereof. At least one region of the semiconductor wafer may be thinned and at least one reinforcement structure for reinforcing the semiconductor wafer may be formed. A semiconductor wafer is disclosed comprising at least one thinned region and at least one reinforcement structure having a first portion and a second portion extending from respective thinned surfaces of the at least one thinned region. A method of designing a semiconductor wafer is disclosed wherein at least one region thereof is selected for thinning. Remaining unthinned regions of the semiconductor wafer may be selected for forming at least one reinforcement structure. At least one semiconductor die location may be selected within the at least one thinned region.

Abstract: This invention relates to a method for making a thin layer starting from a wafer comprising a front face with a given relief, and a back face, comprising steps consisting of: a) obtaining a support handle with a face acting as a bonding face; b) preparing the front face of the wafer, this preparation including incomplete planarisation of the front face of the wafer, to obtain a bonding energy E0 between a first value corresponding to the minimum bonding energy compatible with the later thinning step, and a second value corresponding to the maximum bonding energy compatible with the subsequent desolidarisation operation, the bonding energy E0 being such that E0=?.

Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

Abstract: A lead frame of the present invention includes a pair of base portions having a substantially flat bottom each. An island portion and electrode portions are partly connected to the tops of the base portions. The lead frame needs a minimum of production cost and promotes dense mounting of semiconductor devices to a circuit board.

Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.

Abstract: A method for producing a semiconductor entity is described. The method includes providing a donor substrate having a zone of weakness at a predetermined depth to define a thin layer, and the donor substrate includes a bonding interface. A receiver substrate is also provided that includes at least one motif on its surface. The technique further includes bonding the donor substrate at the bonding interface to the at least one motif on the receiver substrate, and supplying sufficient energy to detach a portion of the thin layer from the donor substrate located at the at least one motif and to rupture bonds within the thin layer. The energy thus supplied is insufficient to rupture the bond at the bonding interface. Also described is fabrication of a wafer and the use of the method to produce chips suitable for use in electronics, optics, or optoelectronics applications.

Abstract: An LC device having a substrate, a support layer having upper and lower sides formed on the substrate, inductors formed on either the upper or lower side of the support layer, and capacitors formed in the opposite side of the support layer. The support layer may be formed of a low-k dielectric material, and a connection portion may be provided to connect the inductors and capacitors in the support layer. The inductors and capacitors are disposed in a stacked structure on the upper and lower sides of the low-k dielectric support layer on the substrate, so that space efficiency may be maximized on the substrate. The low-k dielectric support layer provides support between the inductors and capacitors so that substrate loss is minimized and a Q factor of the inductors is enhanced.

Abstract: The present invention is relates to a polishing method for polishing a semiconductor wafer (W) by pressing the semiconductor wafer (W) against a polishing surface (10) with use of a top ring (23) for holding the semiconductor wafer (W). A pressure chamber (70) is defined in the top ring (23) by attaching an elastic membrane (60) to a lower surface of a vertically movable member (62). The semiconductor wafer (W) is polished while a pressurized fluid is supplied to the pressure chamber (70) so that the semiconductor wafer (W) is pressed against the polishing surface (10) by a fluid pressure of the fluid. The semiconductor wafer (W) which has been polished is released from the top ring (23) by ejecting the pressurized fluid from an opening (62a) defined centrally in the vertically movable member (62).

Abstract: A method of relieving surface stress on a thin wafer by removing a small portion of the wafer substrate, the substrate being removed by applying a warm solution of KOH to the backside of the wafer while the wafer spins. The wafer may be supported on a rotatable platform adapted to direct the flow of chilled, deionized water underneath the device side of the wafer. The chilled water supports the wafer and protects the devices built-up on the wafer from the corrosive effects of KOH and from thermal damage.

Abstract: According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.

Abstract: A method for manufacturing a light emitting device includes (a) preparing a semiconductor element formed with a crystalline substrate, and a temporary element, the temporary element including a laser-transmissive substrate and a laser-dissociable layer formed on the laser-transmissive substrate, (b) attaching the laser-dissociable layer of the temporary element to the epitaxial layer of the semiconductor element through a adhesive layer, (c) thinning the crystalline substrate, (d) applying a laser beam to the temporary element so as to dissociate the laser-dissociable layer of the temporary element, and removing the temporary element from the adhesive layer, and (e) removing the adhesive layer from the epitaxial layer of the semiconductor element.

Abstract: A method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate. The method includes providing an initial structure that includes a useful layer having a front face on a support substrate. Atomic species are implanted into the useful layer to a controlled mean implantation depth to form a zone of weakness within the useful layer that defines first and second useful layers. Next, a stiffening substrate is bonded to the front face of the initial structure. The first useful layer is then detached from the second useful layer along the zone of weakness to obtain a pair of semiconductor structures with a first structure including the stiffening substrate and the first useful layer and a second structure including the support substrate and the second useful layer. The structures obtained can be used in the fields of electronics, optoelectronics or optics.

Abstract: An SOI (Silicon On Insulator) substrate is provided with: a support substrate (201); a single crystal silicon layer (202) disposed above one surface of the support substrate; an insulation portion (205) disposed between the support substrate and the single crystal silicon layer, the insulation portion comprising a single layer of an insulation film or a lamination structure of a plurality of insulation films, and including a silicon nitride film or a silicon nitride oxide film (204).

Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.

Abstract: Disclosed is a method for generating chip stacks during the production of chips from wafers, the chips located on the wafer being separated from one another, the wafer being ground thin and the chips being stacked to form chip stacks, the chips being checked for the purpose of a functional check, characterized in that the chips are checked in a first work step, that adhesive material is applied on the good chips, whereas the bad chips are not provided with adhesive material, that the wafer is assembled and ground thin afterwards and that the bad chips are subsequently removed and replaced by good chips.

Abstract: Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points.

Abstract: A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.

Abstract: The invention relates to a method of producing a thin layer of semiconductor material including: a step of implanting ions through a flat face (2) of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face, a thermal treatment step in order to achieve coalescence of the microcavities possibly, a step of creating at least one electronic component (5) in the thin layer (6), a separation step of separating the thin layer (6) from the rest (7) of the wafer.

Abstract: A semiconductor apparatus that allow miniaturization of a multichip module using an interposer substrate and a method of manufacturing the same are provided. It is configured that an embedded electrode (4) penetrating through an interposer substrate (1) is provided, one end thereof is made to be connected to a connection electrode (2) on which device chips (10) are flip-chip mounted, and connecting to an unillustrated mounting substrate via a bump electrode (5), that is, because an electrode connecting the mounting substrate is made to be drawn out from the back surface of the interposer substrate (1), a multichip module can be miniaturized.

Abstract: To provide a technique for manufacturing a high-performance display device by employing a plastic substrate. A peeling layer is formed on an element-forming substrate, and a semiconductor element and a luminous element are further formed thereon. Then, a fixed substrate (130) is bonded on the luminous element by using a first adhesive (129). The entire substrate in this state is exposed in a gas containing halogen fluoride to thereby remove the peeling layer and separate the element-forming substrate. Thereafter, a bonding substrate (132) that comprises a plastic substrate is bonded in place of the separated element-forming substrate.

Abstract: A method of manufacturing an organic electroluminescent display device includes preparing an auxiliary substrate, which has a flat side; forming a first protective layer on the auxiliary substrate; forming an organic electroluminescent unit on the first protective layer; bonding a flexible main substrate onto the organic electroluminescent unit; and etching the auxiliary substrate to remove it.

Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.

Abstract: A method for forming a, single-crystal silicon layer on a transparent substrate. A transparent substrate having an amorphous silicon layer formed thereon and a silicon wafer having a hydrogen ion layer formed therein are provided. The silicon wafer is then reversed and laminated onto the amorphous silicon layer so that a layer of single-crystal silicon is between the hydrogen ion layer and the amorphous silicon layer. The laminated silicon wafer and the amorphous silicon layer are then subjected to laser or infrared light to cause chemical bonding of the single crystal silicon layer and the amorphous silicon layer and inducing a hydro-cracking reaction thereby separating the silicon wafer is and the transparent substrate at the hydrogen ion layer, and leaving the single-crystal silicon layer on the transparent substrate.

Abstract: A method is provided for manufacturing a semiconductor device, a semiconductor device, a circuit board, and an electronic apparatus. In such a semiconductor device, semiconductor chips can be readily aligned when they are stacked and terminals can be prevented from being short-circuited, thereby enhancing the reliability of the connection between electrodes of the semiconductor chips. According to the method, semiconductor chips are perforated, and a conductive material such as copper is filled into each perforation, thereby forming a terminal that contains the conductive material and has a recessed portion, disposed in the upper face thereof.

Abstract: A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semiconductor substrate is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate is greater than the etching amount with respect to the insulating layer, and the conductive portion is caused to project while covered by the insulating layer. At least a portion of the insulating layer formed on the bottom surface of the depression is etched with a second etchant having characteristics such that at least the insulating layer is etched without forming a residue on the conductive portion, to expose the conductive portion.

Abstract: An electric component package having a base and a lid, the base and lid defining a hermetically sealed cavity therebetween for accommodating an electric component. The base includes at least one conductive via extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component to be coupled to the conducive vias to pass signals between the sealed cavity and the exterior of the package without passing through the junction between the base and lid. The electric component package can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.

Abstract: In accordance with the present invention, a method for producing at least two different chips with a controlled total chip thickness such that when these chips are placed into a corresponding pocket of a plurality of pockets located in a wafer chip carrier wherein each of the plurality of pockets have a total pocket depth (Tdp) at least substantially equal to one another, a substantially planarized top surface of said wafer chip carrier is achieved. The method comprises forming at least a first chip on a first dummy carrier and at least a second chip different from the first chip on a separate second dummy carrier using partial wafer bonding and partial wafer dicing.

Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods also provided.

Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming a first insulating film on a first substrate; forming a second insulating film on the first insulating film; forming an amorphous silicon film on the second insulating film; holding a metal element that promotes the crystallization of silicon in contact with a surface of the amorphous silicon film; crystallizing the amorphous silicon film through a heat treatment to obtain a crystalline silicon film; forming a thin-film transistor using the crystalline silicon film; forming a sealing layer that seals the thin-film transistor; bonding a second substrate having a translucent property to the sealing layer; and removing the first insulating film to peel off the first substrate.

Abstract: A device integration method and integrated device. The method includes the steps of polishing surfaces of first and second workpieces each to a surface roughness of about 5–10 ?. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1–10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

Abstract: A method of fabricating MEMS devices is provided. The method includes the steps of (a) providing a silicon wafer having a MEMS layer arranged on a MEMS side of the wafer; (b) applying a first holding means to the MEMS side of the wafer; (c) performing at least one operation on the wafer from a back side of the wafer opposed to the MEMS side; (d) applying a second holding means to said back side of the wafer; (e) removing the first holding means; (f) performing at least one deep silicon etch on the MEMS side of the wafer to define individual MEMS chips, each chip being composed of a part of the wafer and at least one part of the MEMS layer; and (g) causing the individual chips to be released from the second holding means.

Abstract: A detection apparatus for detecting a feature portion of a composite member having a structure in which a first member having a separation layer inside is brought into tight contact with a second member. The composite member has, as the feature portion, a portion at which a peripheral edge of the first member projects outside a peripheral edge of the second member. The apparatus includes a shift detection section which detects a shift between the peripheral edge of the first member and the peripheral edge of the second member along an outer periphery of the composite member and a determination section which determines the feature portion on the basis of a detection result by the shift detection section.

Abstract: A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the lead between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.

Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaxy on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.

Abstract: A method of manufacturing bonded substrates. The method includes providing a metallic substrate. The metal substrate has a predetermined thickness. The method also includes bonding a first thickness of compound semiconductor material overlying the metallic substrate and reducing a thickness of the first thickness of compound semiconductor material to a second thickness. The method includes forming one or more via structures through a portion of the second thickness of compound semiconductor material to a portion of the underlying metal substrate, whereupon the via structure electrically connects to the metal substrate.

Abstract: In some embodiments, a fabrication method comprises: forming a structure that has one or more substrates, wherein the one or more substrates are either a single substrate or a plurality of substrates bonded together, wherein the structure comprises a non-electronically-functioning component which includes at least a portion of the one or more substrates and/or is attached to the one or more substrates; wherein the one or more substrates include a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; wherein the method comprises removing material from the structure so that the conductor becomes exposed on a second side of the first substrate. In some embodiments, the second side is a backside of the first substrate, and the exposed conductor provides backside contact pads.

Abstract: A semiconductor structure and methods for fabricating are disclosed. In an implementation, a method of fabricating a semiconductor structure includes forming a first semiconductor material substrate with a first dielectric area having a first thickness and a second dielectric area having a second thickness, bonding the first substrate to a second semiconductor substrate, and thinning at least one of the first and second substrates. The invention also pertains to a semiconductor structure. The structure includes a semiconductor substrate having a surface layer of semiconductor material, a first dielectric layer of a first dielectric material buried under the surface layer, and a second dielectric layer buried under the surface layer. In an embodiment, the thickness of the first dielectric layer is different than the thickness of the second dielectric layer.

Abstract: A method of manufacturing a vertical semiconductor device includes preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over the semiconductor substrate, forming a semiconductor element at a surface portion of the semiconductor layer, forming a first metal layer for a first electrode of the semiconductor element over the surface portion of the semiconductor layer, grinding a back of the semiconductor substrate to thin the semiconductor substrate and roughen a back surface of the semiconductor substrate, performing a wet etching upon the back surface; and forming on the back surface a second metal layer for a second electrode of the semiconductor element.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: A process comprises reducing the thickness of a substrate carrying a plurality of devices, with at least certain of the devices having a micro-machined mesh. A carrier wafer is attached to the back side of the substrate and the fabrication of the devices is completed from the top side of the substrate. Thereafter the plurality of devices is singulated. Various alternative embodiments are disclosed which demonstrate that the thinning of the wafer may occur at different times during the process of fabricating the MEMS devices such as before the mesh is formed or after the mesh is formed. Additionally, the use of carrier wafers to support the thinned wafer enables process steps to be carried out on the side opposite from the side having the carrier wafer. The various alternative embodiments demonstrate that the side carrying the carrier wafer can be varied throughout the process.

Abstract: A process is described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. A thin diamond layer is formed on a sacrificial wafer, and an integrated circuit is then formed on the thin diamond layer. The sacrificial wafer is then removed to expose the thin diamond layer. The resulting combination wafer is subsequently diced into individual dies. Each die has an exposed diamond layer forming the majority of the die and serving to conduct heat from the integrated circuit to a backside of the die, from where the heat can convect or be conducted away from the die.

Abstract: In a method for thinning a semiconductor wafer by grinding a back surface of the semiconductor wafer in which semiconductor devices 2 are formed on its surface, the surface of the semiconductor wafer 1 is adhered to a support 4 via an adhesive layer 3, the back surface of the semiconductor wafer is ground while holding the support, and then the thinned semiconductor wafer is released from the support. Preferably, a semiconductor wafer is used as the support, a thermal release double-sided adhesive sheet is used as the adhesive layer, and they are separated by heating after grinding. Thus, there are provided a method for thinning a semiconductor wafer, which enables production of semiconductor wafers having a thickness of about 120 ?m or less without generating breakage such as cracking or chipping during the processing step and so forth as much as possible at a low cost, and a semiconductor wafer thinned further compared with conventional products in spite of a large diameter of 6 inches (150 mm) or more.

Abstract: A method and apparatus for removing layers from a circuit side of a semiconductor die includes the use of a holder, for example a semiconductor wafer having an opening therein for receiving the semiconductor die. Additionally the holder can include one or more layers thereover which are removed at a similar rate as those layers which comprise the semiconductor die. A die is placed into the opening and a circuit side of the die is aligned with a front side of the holder, for example using a generally planar surface, and is secured to the holder with an adhesive material. Using a holder reduces uneven layer removal which is known to occur in conventional processing, for example excessive removal at the edges of the die. A potting jig which aids in aligning and securing the die to the holder is also described.

Abstract: A method for creating a MEMS structure is provided. In accordance with the method, an article is provided which comprises a substrate (101) and a single crystal semiconductor layer (105), and having a sacrificial layer (103) comprising a first dielectric material which is disposed between the substrate and the semiconductor layer. An opening (107) is created which extends through the semiconductor layer (105) and the sacrificial layer (103) and which exposes a portion of the substrate (101). An anchor portion (109) comprising a second dielectric material is then formed in the opening (107). Next, the semiconductor layer (105) is epitaxially grown to a suitable device thickness, thereby forming a device layer (111).

Abstract: A peeling layer (13) and semiconductor thin film (20a) are formed on a first substrate (11), individual support materials (19) are formed thereupon, grooves (23) penetrating the semiconductor thin film and reaching the peeling layer (13) are formed in the semiconductor thin film (20a) by etching using the individual support materials (19) as a mask so as to divide the semiconductor thin film (20a) into a plurality of semiconductor thin film pieces (20) and form a plurality of assemblies of the semiconductor thin film pieces (20) and the individual support materials (19) fixed thereto, the semiconductor thin film pieces (20) are separated from the first substrate (11) while the individual support materials (19) remain fixed to the semiconductor thin film pieces (20), and they are then affixed to a second substrate (31). The invention facilitates handling of semiconductor thin film pieces.

Abstract: The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer) in the first wafer, a bonding process where the surface subjected to the ion implantation of the first wafer is bonded to a surface of a second wafer, and a delamination process where the first wafer is delaminated at the micro bubble layer, wherein the ion implantation process is performed in divided multiple steps, and a bonded wafer. Thus, there are provided a method for producing a bonded wafer, which is for reducing micro-voids generated in the ion implantation and delamination method and a bonded wafer free from micro-voids.

Abstract: In a method of manufacturing a semiconductor device by dividing a semiconductor wafer 6, on which a plurality of semiconductor elements are formed, into individual pieces of the semiconductor elements, after thickness of a reverse face of a circuit formation face 6a is reduced by machining, a mask to determine cutting lines 31b is formed by a resist film 31a, and the semiconductor wafer 6 is divided into individual pieces of semiconductor elements 6c by conducting plasma etching on portions of the cutting lines 31b when plasma is exposed from the mask side, and then the resist film 31a is removed by plasma, and further a micro-crack layer 6b generated on the machined face is removed by plasma etching. A series of the above plasma processing is executed by the same plasma processing apparatus.