Of Layers Of Insulation Patents (Class 439/85)
  • Patent number: 11963307
    Abstract: A ball-grid-array component of a ball-grid array assembly is analyzed prior to reflow. A predicted warping pattern of the ball-grid-array component that is likely to occur during reflow is predicted based on the analyzing. A solder ball ball-grid-array defect that could be caused by the predicted warping pattern is predicted. An initial via suction pattern to mitigate the ball-grid-array defect is assigned. A vacuum head is applied to a via in the ball-grid-array assembly. The solder ball is located at the opposite end of the via from the vacuum head. Suction is applied to the via based on the via suction pattern. The suction draws a portion of the solder ball into the via during reflow.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Matthew Doyle, Thomas W. Liang, Layne A. Berge, John R. Dangler, Jason J. Bjorgaard, Kyle Schoneck, Matthew A. Walther
  • Patent number: 11785717
    Abstract: An electronic board assembly comprises a board comprising an electronic component and a connector mounted to the board and electrically connected to the electronic component. The connector is configured to receive an electronic card assembly, and the connector comprises an electrical contact and a friction contact. The electrical contact is configured to exert a first amount of force on the electronic card assembly when the electronic card assembly is being seated in the connector. The friction contact is configured to exert a second amount of force on the electronic card assembly when the electronic card assembly is being seated in the connector. The second amount of force is greater than the first amount of force.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Tyler Jandt, Mark Plucinski, Sandra J. Shirk/Heath, Phillip V. Mann
  • Patent number: 11772179
    Abstract: Disclosed is a method for producing a high-temperature-resistant, lead-free solder joint between a circuit board and a part, wherein a lead-free solder preform is used that has a composite material having a first composite component arranged substantially in layers and wherein the part is soldered with the solder preform in a hot-bar selective soldering process. Also disclosed is a high-temperature-resistant, lead-free solder joint and a field device of automation technology for determining and/or monitoring the process variable of a medium with a high-temperature-resistant, lead-free solder joint.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 3, 2023
    Assignee: Endress+Hauser SE+Co. KG
    Inventors: Elke Schmidt, Dietmar Birgel
  • Patent number: 11756721
    Abstract: A planar transformer includes a coil substrate including a flexible substrate and multiple coils formed on the flexible substrate. The coil substrate is formed to have coil parts and coilless parts such that the coil parts have the coils and that the coilless parts do not have the coils, and the coil substrate is folded such that at least one of the coilless parts is sandwiched between two of the coil parts.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 12, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Hitoshi Miwa, Shinobu Kato, Toshihiko Yokomaku, Hisashi Kato, Takahisa Hirasawa, Tetsuya Muraki, Takayuki Furuno
  • Patent number: 11540431
    Abstract: A voltage conversion device having a circuit board and a metal shielding cover are provided in this disclosure. The circuit board has a front surface and a back surface. The front surface of the circuit board is provided with a transformer circuit and an assembling terminal electrically connected to the transformer circuit. A through hole is defined at a position on the circuit board corresponding to the assembly terminal. The back surface of the circuit board is covered by the metal shielding cover, and the metal shielding cover is provided with a conductive pin corresponding to the assembling terminal. The assembling terminal is provided with a clamp, and the clamp is arranged corresponding to the position of the through hole. The conductive pin passes through the through hole and clamped by the clamp, and the metal shielding cover is thereby fixed on the circuit board.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: December 27, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Heng-Chao Chen, Chia-Min Ho, Li-Yen Chang
  • Patent number: 11101296
    Abstract: The present disclosure provides a device, a preparing method thereof, and a display device. A device comprises: a flexible substrate; at least two islands on the flexible substrate, each of the islands including a semiconductor layer, adjacent islands being separated by a trench; and at least one inter-island connection line each for electrically connecting corresponding islands.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 24, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Meng Zhao, Weixin Ma
  • Patent number: 10090155
    Abstract: Various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 2, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiyang He, Chenglong Zhang
  • Patent number: 9059552
    Abstract: Aspects of the present invention relate to land grid array socket cartridge structures. In one embodiment, a land grid array (LGA) cartridge structure includes: a deformable thin film having at least one aperture configured to hold a substantially liquid metal, whereby in a compressed state of the deformable thin film, the substantially liquid metal of the deformable thin film is configured to electro-mechanically couple a carrier and a socket base. Another embodiment includes a method of forming a LGA cartridge structure. The method includes: providing a deformable thin film having a first surface and a second surface, and forming at least one aperture within the deformable thin film through the first surface and the second surface, wherein the aperture is configured to hold a substantially liquid metal.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Erwin B. Cohen, Mark C. H. Lamorey
  • Publication number: 20140275873
    Abstract: Embodiments of the present disclosure relate to patient monitoring systems having a connector configured to couple a medical sensor to a monitor. According to certain embodiments, the connector may include a layered printed circuit board having a first surface comprising a plurality of electrical contacts and a second surface having a plurality of electrical contacts. The electrical contacts of the first surface and the electrical contacts of the second surface may be configured to enable the connector to be reversible and to electrically couple the medical sensor to the monitor when the connector is in a first orientation or in a second orientation with respect to the monitor.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: COVIDIEN LP
    Inventors: Timothy W. Fries, Wanran Ma
  • Patent number: 8394911
    Abstract: A phenol resin composition used as a curing agent for an epoxy resin includes a naphthol novolac resin (a1) represented by general formula (1) (wherein R1 and R2 each independently represent a hydrogen atom, an alkyl group, or an alkoxy group, and n is a repeating unit and an integer of 1 or more), and a compound (a2) represented by general formula (2) (wherein R1 and R2 each independently represent a hydrogen atom, an alkyl group, or an alkoxy group), wherein the total ratio of compounds with n=1 and n=2 in the general formula (1) present in the composition is in the range of 10 to 35%, the average of n in the general formula (1) is in the range of 3.0 to 7.0, and the content of the compound (a2) in the composition is 1 to 6%.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: March 12, 2013
    Assignee: DIC Corporation
    Inventors: Yutaka Satou, Kazuo Arita, Ichirou Ogura
  • Publication number: 20100087075
    Abstract: A conductive contact holder includes a holder substrate and a holding member. The holder substrate is made of a conductive material and has an opening for holding a conductive contact for inputting and outputting a signal to and from a circuit structure. The holding member is formed by filling the opening with an insulating material, smoothing the surface of the insulating material, and forming a hole through the insulating material for inserting the conductive contact.
    Type: Application
    Filed: December 13, 2007
    Publication date: April 8, 2010
    Applicant: NHK SPRING CO., LTD.
    Inventors: Toshio Kazama, Tomohiro Kawarabayashi, Shigeki Ishikawa, Shinya Miyaji
  • Patent number: 7489524
    Abstract: An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: February 10, 2009
    Assignee: Tessera, Inc.
    Inventors: Ronald Green, Sridhar Krishnan, Stuart E. Wilson, James Gill Shook, Ming Tsai, Andy Stavros
  • Patent number: 7485802
    Abstract: In a circuitry assembly, a first insulative sheet is disposed between first electric wires and second electric wires intersecting each other. A wiring member holds the first electric wires and the second electric wires. The circuitry assembly is accommodated in a casing body of an electrical junction box. Each of the first electric wires held by the wiring member is press-fitted to a first terminal to be electrically connected therewith. Each of the second electric wires held by the wiring member is press-fitted to a second terminal to be electrically connected therewith.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: February 3, 2009
    Assignee: Yazaki Corporation
    Inventors: Masaoki Yoshida, Katsuhiro Kubota
  • Publication number: 20080305651
    Abstract: An electrical connector for connecting a cable to a card edge interface has a housing portion. The housing portion has a first surface, and a second surface opposite said first surface, and the surfaces are spaced apart to define a housing portion slot for the card edge interface. Furcated contact elements are disposed within the housing. Each contact element has a first tine portion with an exposed contact interface portion, a second tine portion; a web portion connecting the first and second tine portions, and a wire termination portion for terminating a conductor of the cable. The first and second tine portions are arranged within the housing portion with the contact interface exposed for mating with a respective contact surface of the card edge interface.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Matthew Edward MOSTOLLER, Christopher George DAILY
  • Publication number: 20080261418
    Abstract: An electrical card connector assembly includes an electrical card connector (100) and a PCB (4) where the electrical card connector is assembled. The electrical card connector includes a metal shield (1), an insulating housing (2) and a terminal module (3) received in the insulating housing. The insulating housing associates with the metal shield to define a card receiving room. The metal shield forms a base (10) and a plurality of sidewalls (11) extending from the base. Each sidewall forms a locking portion (111) thereof. Each locking portion has a vertical portion (1110) and a horizontal portion (1111) extending from a lower end of the vertical portion. At least one of the sidewalls forms an elastic piece (12) extending along a card insertion/ejection direction and the elastic piece forms a declined portion (120). The PCB defines a plurality of cutouts (44) and at least one aperture (47).
    Type: Application
    Filed: April 23, 2008
    Publication date: October 23, 2008
    Inventors: Chien-Jen Ting, Kuo-Lung Lin
  • Publication number: 20080038945
    Abstract: A film capacitor 13 for filtering mounted on a substrate is higher than a projected lead wire of the high voltage terminal. The lead wire of the high voltage terminal is interposed between the film capacitor and a connector housing. A gap is so formed between the film capacitor and the connector housing as to prevent a finger from entering the gap.
    Type: Application
    Filed: June 25, 2007
    Publication date: February 14, 2008
    Inventor: Yoshihiro Kawamura
  • Patent number: 7147490
    Abstract: A cleaning apparatus (100) for cleaning an endface (202) of an optical fiber contained within an interface device (200) is provided. The cleaning apparatus includes a housing (110) having an interface portion (116) adapted to be received by the interface device. The cleaning apparatus also includes at least a first nozzle (126) operable to deliver a pressurized gas and a solvent upon the endface to aid in the removal of contaminants on the endface. A method for cleaning an endface of an optical fiber contained within an interface device is also provided. The method comprises the steps of inserting an interface portion within the interface device so as to position a nozzle in proximity to the endface of the interface device. The method further comprises the steps of directing a pressurized gas through the nozzle toward the endface and intermixing a solvent with the pressurized gas.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: December 12, 2006
    Assignee: Westover Scientific, Inc.
    Inventor: Gregory J. Gerhard
  • Patent number: 7114960
    Abstract: An apparatus and method for making a compliant interconnect assembly adapted to electrically couple a first circuit member to a second circuit member. The first dielectric layer has a first major surface and a plurality of through openings. A plurality of electrical traces are positioned against the first major surface of the first dielectric layer. The electric traces include a plurality of conductive compliant members having first distal ends aligned with a plurality of the openings in the first dielectric layer. The first distal ends are adapted to electrically couple with the first circuit member. The second dielectric layer has a first major surface positioned against the electric traces and the first major surface of the first dielectric layer. The second dielectric layer has a plurality of through openings through which the electric traces electrically couple with the second circuit member.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: October 3, 2006
    Assignee: Gryhics, Inc.
    Inventor: James J. Rathburn
  • Patent number: 7025607
    Abstract: A material for use as part of an internal capacitor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ferroelectric ceramic component, the ferroelectric ceramic component nano-particles having a particle size substantially in the range of between about 0.01 microns and about 0.9 microns and a surface within the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate adapted for using such a material and capacitor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: April 11, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich, Mark D. Poliks
  • Patent number: 6957963
    Abstract: An apparatus and method for making a compliant interconnect assembly. The compliant interconnect assembly includes a first carrier having a first major surface and a plurality of through openings. A first major surface of a first flexible circuit member having a plurality of electrical traces is attached to the first major surface of the first carrier. The electrical traces include a plurality of compliant members having at least one distal end projecting in one of the openings of the first carrier. A first major surface of a second carrier is positioned opposite a second major surface of the first flexible circuit member. The second carrier has a plurality of through openings aligned with the plurality of the compliant members.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: October 25, 2005
    Assignee: Gryphics, Inc.
    Inventor: James J. Rathburn
  • Patent number: 6939143
    Abstract: A method and apparatus for achieving a fine pitch interconnect between a flexible circuit member and another circuit member with co-planar electrical contacts that have a large range of compliance. The interconnect assembly includes a substrate with one or more compliant raised portions. At least one flexible circuit member having a first surface with a plurality of contact pads and a second surface is provided. The substrate is located along the second surface of the flexible circuit member with the compliant raised portions aligned with the contact pads so that the compliant raised portions bias the contact pads with corresponding contact pads on the first circuit member when in a compressive relationship.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: September 6, 2005
    Assignee: Gryphics, Inc.
    Inventor: James J. Rathburn
  • Patent number: 6878014
    Abstract: An electrical connector assembly has live-phase conductive strips (5) potted in a solid polymer body (4). The strips are cut to provide transverse terminals (5a) on opposite sides. The polymer body (4) is confined within a housing (3) which is made from a series of body sections (6) joined end-to-end. These sections (6) extend around the periphery of the body (4) and have slots (11) through which the terminals (5a) project. Each section may be formed from two shells (7, 8) joined at longitudinal edges. A desired housing length can be built up by selection of an appropriate number of body sections (6). The assembly (24) can be enclosed within a box-shaped container (25) together with electrical devices (2), such as switches, connected to the assembly (24) and having operating members (33) which are accessible through openings (31) in a top wall (30) of the container (25).
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: April 12, 2005
    Inventor: Derek Linaker
  • Patent number: 6444920
    Abstract: The invention relates to a thin film circuit with component. The thin film circuit comprises a network of capacitors, or a network of capacitors and resistors, or a network of capacitors, resistors and inductances, or a network of capacitors and inductances. Current supply contacts such as, for example, SMD end contacts or bump end contacts render it possible for the thin film circuit to be connected to further components of a circuit or, for example, to be combined with active components through the use of contact surfaces.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: September 3, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Mareike K. Klee, Hans-Wolfgang Brand, Uwe Mackens, Rainer Kiewitt, Antonius J. M. Nellisen, Antal F. J. Baggerman, Martin Fleuster, Marc De Samber
  • Patent number: 5917707
    Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: June 29, 1999
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 5742484
    Abstract: A surface mountable flexible interconnect (10) for connecting two circuit board (30, 32) consists of a flex circuit (12) with solderable runners (14) on one side, the runners traversing the flex circuit from one end to the other. There is a solderable pad (16) at the end of each runner, and each solderable pad has a solder bump (18) fused to it. A rigid carrier ring (20) is used to hold the flex circuit in position prior to placement on the PCB. The flex circuit is formed into a U-shaped loop (26), and the loop is aligned to the carrier so that the loop is situated in an aperture (24) in the carrier. The solder pads lie directly under the carrier ring and face away from it. An adhesive (22) bonds the flex circuit to the carrier ring.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: April 21, 1998
    Assignee: Motorola, Inc.
    Inventors: Joseph G. Gillette, Scott G. Potter, Pradeep Lall
  • Patent number: 5652553
    Abstract: In a system having modules (20), voltage supply (15), signal transmission via terminated signal lines (13) and signal ground (14), the impedance of the signal lines (13) with respect to both the signal ground (14) and the voltage supply (15) is identical, an AC coupling of the contacts for signal ground and voltage supply being effected on the modules and close to the termination of the signal lines.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: July 29, 1997
    Assignee: Siemens Nixdorf Informationssysteme Aktiengesellschaft
    Inventor: Werner Pollmeier
  • Patent number: 5480309
    Abstract: A universal laminated base board assembly for connecting an integrated circuit device to a pcb has a series of alternating, overlying, conductive and insulating layers with two of the conductive layers providing ground and current lines on respective opposite faces. A plurality of through-holes extend through the layers and insulated from the conductive layers for receiving respective socket forming body portions of contact elements selected from signal, current and grounding types with the signal contact elements remaining insulated from the conductive layers and the current and grounding types having conductive layer connecting portions bridging the insulation into connection with the current and ground layers respectively. The contact elements are inserted in those through holes which are aligned with signal, current and ground line terminal lead pins, respectively, of the particular device chosen, adapting the base board to any one of a variety of different devices.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: January 2, 1996
    Assignee: Kel Corporation
    Inventor: Hiroshi Arisaka
  • Patent number: 5477612
    Abstract: A supported conductive network (SCN), which can be flexible or rigid, can have self-aligning conductors which connect with corresponding conductors of other networks. The conductive network can be fabricated into densely packed contact clusters for use as electrical interconnectors or circuits. The methods and apparatus for making the conductive network involve forming a sheet of conductive material into ridges and troughs one of which defines the conductive network and the other of which is waste material and then mechanically removing the waste material. The conductive network thus formed is supported by a dielectric layer.
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: December 26, 1995
    Assignee: Rock Ltd. Partnership
    Inventor: Joseph A. Roberts
  • Patent number: 5343616
    Abstract: A conductive network, which can be flexible or rigid, can have self-aligning conductors which connect with corresponding conductors of other networks. The conductive network can be fabricated into densely packed contact clusters for use as electrical interconnectors or circuits. The contact clusters, which can be configured to substantially any shape, are the essential components of high density connector assemblies. The methods and apparatus for making the conductive network and cluster contacts are also described.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: September 6, 1994
    Assignee: Rock Ltd.
    Inventor: Joseph A. Roberts
  • Patent number: 5199162
    Abstract: A wire-electrode arrangement for effecting a spark-erosive cutting and a method for the manufacture of a wire electrode. In order to be able to cut non-conductive materials, a plus potential and also a minus potential can be applied to the electrode, since the wire electrode is formed by a first and a second electrode, which are insulated from one another and which extend substantially parallel to one another.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: April 6, 1993
    Assignee: Berkenhoff GmbH
    Inventor: Heinrich Groos
  • Patent number: 5057026
    Abstract: To standardize electric junction boxes so that the internal circuits can be applied to various requirements without markedly changing parts, the junction box is divided into plural stackable distributing units each connectable to each subharness via each subharness connector. The junction box comprises a plurality of stackable distributing units including a plurality of parallel arranged wires connectable with at least one external subharness; wire shorting bus bars or wire branch bars arranged so as to cross the parallel arranged wires; and an interlayer connecting unit or plural interlayer connecting terminals arranged so as to cross the surfaces of the plural distributing units for connecting the parallel arranged wires and the wire shorting bus bars arranged on different distributing units. Further, when male connector terminals are provided on each distributing unit, it is possible to form a subharness connector by use of these male connector terminals on each distributing unit.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: October 15, 1991
    Assignee: Yazaki Corporation
    Inventors: Mamoru Sawai, Mitsugu Watanabe, Hiroshi Suzuki, Keiichi Ozaki
  • Patent number: 5044966
    Abstract: An electrical panel for particularly supporting and supplying electrical connections for a plurality of electrical components comprises a sandwich formed by a central conducting layer computer design to form a plurality of conducting paths which are laser cut from a sheet of cooper and a pair of covering plastic layers of insulating material. Mechanical anchoring points extend through the sandwich missing the conducting paths into an optional supporting steel sheet. Electrical connecting points comprise screw threaded pins which engage into female screw threads formed in the front insulating layer and into the conducting layer.
    Type: Grant
    Filed: May 23, 1989
    Date of Patent: September 3, 1991
    Inventor: Peter Friesen
  • Patent number: 4992059
    Abstract: The invention is a fine line electrical cable with two ends having a plurality of first conductor lines in a plane. The lines of the cable are embedded in an insulating laminate material, are closely spaced at one end to be compatible with the closely spaced contacts from IC chips and are fanned out along the length of the cable to the other end where the lines are spaced somewhat apart and compatible with conventional electrical connectors. Contact posts extent from each line end so that external connections may be made with the IC chips and the conventional connectors. At least one second conductor line may be embedded within the other side of the laminate material and appropriate contact posts extend from the line ends so that external connections may also be made at these locations. A method for fabricating the fine line elecrical cable is also disclosed.
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: February 12, 1991
    Assignee: Westinghouse Electric Corp.
    Inventors: David R. King, David B. Harris
  • Patent number: 4944684
    Abstract: An improved electrical junction box includes a housing, a multilayer printed circuit board supported by the interior of the housing and an array of electrical connectors supported by the exterior of the housing. The electrical connectors make electrical contact with one or more circuit traces in the multilayer circuit board. The circuit traces are of varying thicknesses according to the current levels to be conducted by the traces, thus minimizing the amount of copper required to fabricate the junction box. The circuit traces with the greater thicknesses are positioned in the outer layers of the circuit board to enhance heat dissipation from the circuit board.
    Type: Grant
    Filed: June 28, 1988
    Date of Patent: July 31, 1990
    Assignee: TRW, Inc.
    Inventor: Joseph D. Leibowitz
  • Patent number: 4906198
    Abstract: A circuit assembly (e.g., printed circuit board) including an insulative substrate having opposed surfaces each defining a walled opening therein. Each walled opening includes a layer of conductive material (e.g., copper) plated thereon, these openings being electrically connected through a common channel or the like, which channel in turn has been plated to include copper material therein. Located within each opening is a compliant contact pin including a compliant end portion designed to provide an interference fit within one of the respective openings and an extending portion designed for extending from the board's outer surfaces to be electrically connected to a designated external component (e.g., printed circuit board, wiring, conductive socket).
    Type: Grant
    Filed: December 12, 1988
    Date of Patent: March 6, 1990
    Assignee: International Business Machines Corporation
    Inventors: Raymond J. Cosimano, Reinhold E. Tomek
  • Patent number: 4894016
    Abstract: A stepped electrical connector having a printed circuit board mounted in an electrically insulating housing. The board has a first collection of electrical contacts extending in a given direction and a second collection of contacts extending in the opposite direction. The number of contacts in the second collection is less than the first collection and the circuitry on the board accommodates the difference.
    Type: Grant
    Filed: June 27, 1988
    Date of Patent: January 16, 1990
    Assignee: GTE Products Corporation
    Inventor: John O. Wright
  • Patent number: 4860088
    Abstract: A flexible beam lead tape having three layers having trace conductors, a dielectric and a ground plane. Vias extend through the dielectric layer at the first and second ends of the electrical conductors for providing versatile connections to either ends of the conductors. The ends of the conductors may be provided with electrical connections on either or both sides of the tape and may be connected by pressure contact or by bonding.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: August 22, 1989
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Robert T. Smith, Chang-Hwa Chung
  • Patent number: 4781600
    Abstract: A watertight and leak-proof junction box for use, for example, in vehicles such as automobiles, and a process of assembling such a junction box are provided. The wiring board assembly comprising a plurality of insulating plates, wiring conductors strips and electric contacts formed by raising the free ends of the strips so as to project from the outer surface of the wiring plate pile which is embedded in an insulating resin through molding to form a resin-embedded wiring board assembly prior to assembling the junction box, and then the resin-embedded wiring board assembly joined with a connector support board having connector bodies for receiving the terminals of electrical units and/or wire harnesses is contained in a watertight case.
    Type: Grant
    Filed: June 8, 1987
    Date of Patent: November 1, 1988
    Assignee: Yazaki Corporation
    Inventors: Masaaki Sugiyama, Mitsugu Watanabe, Hideharu Hayashi, Yukio Nishio, Masaki Yamamoto
  • Patent number: 4767674
    Abstract: It is disclosed that a metal cored board which comprises an electrically conductive layer whose one surface at least composed of a hardly oxidizable metal, an insulating organic polymer layer baked on the surface of the hardly oxidizable metal, and a metal core adhered on the insulating organic polymer layer, and a method for manufacturing a metal cored board, which comprises a step to coat the surface of a hardly oxidizable metal layer of an electrically conductive metal foil with an insulating varnish, a step to bake a layer of the varnish, and a step to adhere a metal core on the baked varnish layer.
    Type: Grant
    Filed: July 26, 1985
    Date of Patent: August 30, 1988
    Assignee: Dainichi-Nippon Cables, Ltd.
    Inventors: Hideaki Shirai, Kimio Chiba, Koji Okawa, Hiroshi Ishibashi, Akihiro Ishii, Hirotaka Itoh, Hirokazu Kuzushita, Michihiko Yoshioka, Michio Hirose
  • Patent number: 4689103
    Abstract: A plurality of physically separate plastic substates are injection molded, each with at least one pattern of channels formed in a surface of thereof defining a conductive circuit to be formed. The plurality of substrates are then physically connected in a common planar array either by inserting them in corresponding receptacles in a carrier board, by mating peripheral connecting elements, by using adhesive or by some other suitable connecting mechanism. Where a carrier board with pre-formed receptacles is not utilized, the individual substrates in the array are pierced and replaced. The planar array is processed to simultaneously form a conductive circuit on each substrate consisting of metal deposited in its pattern of channels. The planar array of metallized substrates may then be stuffed with electronic components on an automatic insertion machine, wave soldered. The individual finished circuit boards are then pressed out.
    Type: Grant
    Filed: November 18, 1985
    Date of Patent: August 25, 1987
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: Vito D. Elarde