Semiconductor Patents (Class 455/252.1)
  • Patent number: 10912196
    Abstract: A power distribution assembly includes a printed circuit board (PCB) having a power input and electrical components connected to PCB conductive trace. A power bus extends from the PCB and has a conductive core, a dielectric layer on an exterior surface of the conductive core, a conductive trace on the dielectric layer, and a power cut through the dielectric layer to the conductive core. The conductive core is connected to the power input by way of the power cut through and the at least one second conductive trace is connected to the PCB conductive trace.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 2, 2021
    Assignee: GE Aviation Systems Limited
    Inventor: Alexander James Rainbow
  • Patent number: 10573602
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: February 25, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Mao-Ying Wang, Pei-Lin Huang
  • Patent number: 10439671
    Abstract: Embodiments of the invention include a communication module that includes a die having a transceiver and a phase shifter die that is coupled to the die. The phase shifter includes a power combiner and splitter. The communication module also includes a substrate that is coupled to the phase shifter die. The substrate includes an antenna unit with steerable beam forming capability for transmitting and receiving communications.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios C. Dogiamis, Vijay K. Nair
  • Patent number: 9367711
    Abstract: Embodiments of the present invention provide RFID systems having battery-assisted, Semi-Passive RFID tags that operate with sensitive transistor based square law tag receivers utilizing a plurality of tag receiver dynamic range states. Embodiments of the present invention are also enhanced with receiver training and synchronizing methods suited to the high tag sensitivity and need for dynamic range state switching. These enhancements may employ pseudo-random sequence based receiver training, activation signaling, and frame synchronizing. Further enhancement is achieved via design of system command sets and tag state machine behavior that control system interference and allow maximum usage of high sensitivity. Command set design also allows for convenient expansion to active transmitters and receivers in tags operating within the same system.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 14, 2016
    Assignee: Intelleflex Corporation
    Inventors: Farron Dacus, Joseph Bouchez, Johannes Albertus van Niekerk, Alfonso Rodriguez
  • Patent number: 9143089
    Abstract: An example embodiment of an active cascode circuit has a control circuit for control of the gate to source voltage (VGS) of at least one transistor in the active cascode circuit. The embodiment may be configured so that control of the VGS also controls the voltage Vin on the input. Vin may be adjusted without altering the device geometry or changing the drain current. This allows for better control and optimization of available headroom for the input voltage in low voltage designs and also results in higher active cascode circuit bandwidth and/or higher output impedance (Rout) for a given power level.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 22, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Daniel F. Kelly
  • Patent number: 9042860
    Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 26, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Torkel Arnborg
  • Patent number: 9020420
    Abstract: An antenna module embeds front end circuitry with an antenna. Adaptive matching circuitry external to the antenna module is electrically connected between the embedded front end circuitry and the embedded antenna.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Jasper Display Corp.
    Inventors: Ching-Juang Peng, Wei-Hsuan Lee, Jin-Tsang Jean, Yi-Ching Pao
  • Publication number: 20150111514
    Abstract: A radio frequency (RF) receiver front end includes an RF attenuator for receiving an RF input signal and a low noise amplifier (LNA). In one form, the LNA provides a differential output signal and includes a first polarity amplifier and a plurality of second polarity amplifiers. The first polarity amplifier has an input terminal coupled to the output of the RF attenuator, an output terminal for providing a first component of the differential RF output signal, and has a first input impedance. Each of the plurality of second polarity amplifiers has an input terminal coupled to the output of said RF attenuator, and an output terminal. The output terminals of said plurality of second polarity amplifiers are coupled together and form a second component of the differential RF output signal. Each of the plurality of second polarity amplifiers has a second input impedance higher than the first input impedance.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 23, 2015
    Applicant: Silicon Laboratories Inc.
    Inventors: Navin Harwalkar, Tim Stroud, Dan Kasha
  • Patent number: 8971832
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy Van De Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 8903342
    Abstract: A high dynamic range precision variable amplitude controller includes a gain portion configured to apply a controllable amount of amplitude adjustment to an input signal. The gain portion includes two or more amplification stages each amplification stage having branches that are cross-coupled with branches of the other amplification stage. A control portion controls the current supply to the two or more amplification stages to control the amount of amplitude adjustment by the gain portion. The amplitude controller also includes a load portion that provides balanced impedances to the cross-coupled branches of the amplification stages throughout the amplitude control range.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 2, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman
  • Patent number: 8897832
    Abstract: Disclosed is a semiconductor device including a semiconductor chip and a semiconductor package. The semiconductor package includes an antenna formed of a lead frame, a first wire that connects the antenna and a first electrode pad of the semiconductor chip, and a second wire that connects the antenna and a second electrode pad of the semiconductor chip. The semiconductor chip is disposed in one of four regions in the semiconductor package sectioned by line segments connecting midpoints of two pairs of opposing sides of the semiconductor package. A centroid of the semiconductor chip is positioned outside a closed curve composed of a straight line segment connecting a first connection point where the antenna and the first wire are connected and a second connection point where the antenna and the second wire are connected, and a line connecting the first and second connection points along the antenna.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichiro Hijioka, Koichi Yamaguchi
  • Patent number: 8892158
    Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Jun Koyama
  • Patent number: 8855590
    Abstract: Disclosed is a radio frequency signal receiving device, which includes a low-noise amplifier (LNA) and a mixer. The LNA includes a first inductor and a second inductor. The mixer has a first differential pair and a second differential pair, common ends of the first differential pair and the second differential pair are respectively coupled to the first differential output end and the second differential output end. The first inductor and the second inductor are serially connected between the first differential output end and the second differential output end of the LNA, so as to reduce power consumption and reach suitable frequency response. The first inductor and the second inductor generate a resonance effect with parasitic capacitance on the mixer, so as to effectively reduce flicker noises, and improve a working benefit of the radio frequency signal receiving device.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 7, 2014
    Assignee: Montage Technology (Shanghai) Co., Ltd.
    Inventors: Shih-Ming Chiu, Keng-Chang Liang
  • Patent number: 8838058
    Abstract: A communications radio or transceiver having an extended upper operating frequency limit of at least 6 GHz. The radio includes a first IF conversion stage for receiving and downconverting a RF input signal to a first IF signal, and a second IF conversion stage for downconverting the first IF signal to a second IF signal. The first and the second conversion stages each have adjustable first and second attenuators, a serial peripheral interface (SPI) for controlling the attenuators in response to command words, a mixer coupled to an output of the second attenuator, and a buffer for applying a local oscillator (LO) signal to an input of the mixer. Each conversion stage is in the form of an integrated circuit chip. Component devices of each chip and electrical connections between the components, are dimensioned so that the chip has a 6 GHz upper frequency limit.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 16, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Michael S. Vogas
  • Patent number: 8660502
    Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 25, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yusuke Wachi, Takashi Kawamoto, Yuta Sugiyama
  • Patent number: 8655296
    Abstract: A frequency synthesizer includes a phase-locked loop circuit having an output. A frequency divider is connected to the output of the phase-locked loop circuit for receiving the signal therefrom and dividing the frequency of the signal. A tunable bandpass filter is connected to the frequency divider and is tuned for selecting a harmonic frequency to obtain a fractional frequency division for a signal output from the phase-locked loop circuit.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: February 18, 2014
    Assignee: Harris Corporation
    Inventor: Amilcar Deleon
  • Patent number: 8588681
    Abstract: Disclosed is a semiconductor device which performs signal transmission by using inductor coupling. The semiconductor device comprises one or more transmission and reception coil pair, each pair comprising a single transmission coil and a plurality of reception coils, or a plurality of transmission coils and a single reception coil, or a plurality of transmission coils and a plurality of reception coils.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: November 19, 2013
    Assignee: NEC Corporation
    Inventor: Yoshihiro Nakagawa
  • Patent number: 8559906
    Abstract: An embodiment of a system and method provides a carbon nanotube transistor (CNT) mixer with a low local oscillator power requirement and no inter-modulation products. Specifically, an embodiment of the system and method provides two kinds of device current-voltage (I-V) characteristics on the same integrated circuit: exponential and linear. The CNT I-V characteristics support both the ideal exponential control characteristic (determined by physics constants) and the ideal linear control characteristic (also determined by physics constants), resulting in an ideal multiplier. In other words, the CNT mixer is mathematically equivalent to an ideal multiplier. Such an ideal multiplier can be used as a mixer with low local oscillator power requirement and virtually no inter-modulation products.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 15, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Dale E. Dawson, John X. Przybysz, Maaz Aziz
  • Patent number: 8489052
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: July 16, 2013
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy van de Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 8467825
    Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: June 18, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Jun Koyama
  • Publication number: 20130137388
    Abstract: The first control circuit controls the gain of the variable gain amplifier circuit and the cut-off frequency of the first low-pass filter so as to keep constant a product of a transfer function of the variable gain amplifier circuit and a transfer function of the first low-pass filter. The second control circuit compares a level of the second feedback signal and a preset threshold value after completion of gain control of the variable gain amplifier circuit, the second control circuit inputting the signal outputted from the first low-pass filter, as the first feedback signal to the first terminal as long as the level of the second feedback signal is not lower than the threshold value, the second control circuit inputting the signal outputted from the second low-pass filter, as the first feedback signal to the first terminal.
    Type: Application
    Filed: March 19, 2012
    Publication date: May 30, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Daisuke Miyashita
  • Patent number: 8396441
    Abstract: A mixer circuit suitable for broadband RF applications is disclosed. A unique biasing scheme for a conventional Gilbert-cell type 4-quadrant multiplier is used, resulting in relatively good linearity, relatively low noise, and relatively low power consumption. Disclosed techniques provide programmability in gain for the mixer and a broadband frequency of operation. A non-linear feedback loop is wrapped around the circuit to stabilize the common-mode voltage shifts due to programming. In one embodiment, a non-linear switch as load-resistance is used to improve the linearity of the circuit.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: March 12, 2013
    Assignee: PMC-Sierra, Inc.
    Inventor: Vikas Choudhary
  • Patent number: 8385875
    Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasunobu Yoshizaki, Tetsuya Wakuda
  • Patent number: 8364195
    Abstract: An embodiment of a wireless galvanic isolator device is formed by a transmitter circuit, a receiver circuit, and a wireless coupling structure, arranged between the transmitter circuit and the receiver circuit. The wireless coupling structure is formed by a pair of antennas each arranged on an own die and integrated together with the respective transmitter and receiver circuit. The two dice may be arranged adjacent to each other in a planar configuration or arranged on top of each other and bonded together.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: January 29, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nunzio Spina, Giovanni Girlando, Santo Alessandro Smerzi, Giuseppe Palmisano
  • Patent number: 8306495
    Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi Takahashi
  • Patent number: 8265582
    Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi Takahashi
  • Publication number: 20120225631
    Abstract: A semiconductor device (1), comprising: an input attenuator (10) adapted to receive an antenna signal (20) and to output a first attenuated signal (22), the first attenuated signal corresponding to the antenna signal attenuated by a first attenuation factor, the input attenuator being further adapted to receive a control signal (24) and to select one of a plurality of predetermined attenuation factors as said first attenuation factor depending on the control signal; an analogue to digital converter unit (12) adapted to generate an intermediate signal (28) by digitizing said first attenuated signal (22); and a digital attenuator (14) adapted to receive the intermediate signal (28) and to output a second attenuated signal (32), the second attenuated signal corresponding to the intermediate signal attenuated by a second attenuation factor (44), the second attenuation factor being set such as to compensate a gain quantization error of the control signal (24).
    Type: Application
    Filed: February 2, 2012
    Publication date: September 6, 2012
    Applicant: Sony Corporation
    Inventor: Gerd SPALINK
  • Patent number: 8260245
    Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventor: Torkel Arnborg
  • Patent number: 8238867
    Abstract: A low-noise amplifier includes first and second transconductance paths and first and second variable capacitive dividers. The first transconductance path has a first terminal for receiving a first input signal, a control terminal, and a second terminal for providing a first output signal. The second transconductance path has a first terminal for receiving a second input signal, a control terminal, and a second terminal for providing a second output signal. The first variable capacitive divider has a first terminal for receiving the first input signal, a second terminal coupled to a reference voltage terminal, and an intermediate terminal coupled to the control terminal of the second transconductance path. The second variable capacitive divider has a first terminal for receiving the second input signal, a second terminal coupled to the reference voltage terminal, and an intermediate terminal coupled to the control terminal of the first transconductance path.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 7, 2012
    Assignee: Silicon Laboratories Inc
    Inventor: Ramin Khoini-Poorfard
  • Patent number: 8238864
    Abstract: The present invention aims to efficiently calibrate the characteristics of a pair of reception or transmission low-pass filters by a receiving or transmitting circuit. A semiconductor integrated circuit includes an RF receiver that processes an RF reception signal, an RF transmitter that generates an RF transmission signal and a frequency synthesizer. A reception low-pass filter of the RF receiver suppresses undesired components contained in I and Q baseband reception signals. A transmission low-pass filter of the RF transmitter suppresses noise due to D/A conversion, which is contained in I and Q transmission analog baseband signals. A calibration test signal is supplied to the inputs of the pair of reception or transmission low-pass filters. A difference in phase between the pair of filters is detected by a phase detection unit. A calibration controller calibrates a relative mismatch between the cut-off frequencies of the pair of filters.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Manabu Kawabe, Satoshi Tanaka, Yoshikazu Nara
  • Patent number: 8224277
    Abstract: An object is to provide a semiconductor device which operates normally even when the communication distance is extremely short, while the maximum communication distance is maintained, and which can make amplitude of a response waveform large even when a large amount of electric power is supplied to the semiconductor device and a protection circuit operates. The object is achieved with a semiconductor device including a first modulation circuit and a second modulation circuit each of which performs load modulation by an input signal, a detection circuit which determines an output signal by electric power supplied externally, a protection circuit which is controlled by the output signal of the detection circuit, and a modulation selecting circuit which switches the first modulation circuit and the second modulation circuit depending on the output signal of the detection circuit.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: July 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuma Furutani
  • Patent number: 8200179
    Abstract: In one embodiment, a combined VGA-and-equalizer (VGA-EQ) circuit for a communication link includes a current-mode logic (“CML”) amplifier with an inductive load circuit. The CML amplifier has a gain control terminal and is operable to amplify, with an adjustable gain, a signal received at an input terminal and provide the amplified signal at an output terminal. The CML amplifier has a first gain at frequencies below a predetermined frequency value and a second gain at frequencies in a predetermined frequency range above the predetermined frequency value, wherein the second gain is higher than the first gain. The higher second gain of the VGA-EQ circuit causes a reduction in inter-symbol interference in a signal received by the receiver.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: June 12, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventors: Paulius Mosinskis, Richard Booth
  • Patent number: 8175545
    Abstract: A communication device includes an integrated circuit having an on-chip thermal sensing circuit that generates a temperature signal based on a temperature of the integrated circuit. A processing module processes the temperature signal to generate temperature information that can be transmitted to a remote device or processes the temperature signal to generate control for adjusting transmit and/or receive characteristics of an RF transceiver.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: May 8, 2012
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Reza Rofougaran
  • Patent number: 8064859
    Abstract: An integrated circuit radio transceiver and method therefor includes a high-pass variable gain amplifier (HPVGA) operably disposed within one of the transmitter and the receiver front ends operable to provide a linear variable gain and a substantially constant high-pass frequency corner that does not vary with changes in gain level settings. The HPVGA includes an amplifier operably disposed to receive an input signal and to produce an amplified output based upon the input signal, an adjustable resistance block operable to adjust resistance based upon a gain control input and corner drift compensation block operably disposed to provide corner frequency compensation at the input terminal of the amplifier that is further coupled to receive the input signal from the adjustable resistance block.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: November 22, 2011
    Assignee: Broadcom Corporation
    Inventors: Michael S. Kappes, Arya Reza Behzad
  • Patent number: 8045940
    Abstract: An integrated circuit, IC, for reception of radio frequency; RF, signals in an antenna network system, the IC comprising: a plurality of amplifying paths to cover a plurality of radio frequency bandwidths or standards, each amplifying path comprising at least one low noise amplifier, at least one variable attenuator unit, and/or at least one gain flattening unit, each of the low noise amplifier, the attenuator unit, and the gain flattening unit being adapted to operate at a respective radio frequency bandwidth or standard; at least one control interface connected with at least one of the low noise amplifier, the attenuator unit, and the gain flattening unit on each amplifying path and adapted for communication with a digital processing unit to control operation of the at least one of the low noise amplifier, the attenuator unit, and the gain flattening unit.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: October 25, 2011
    Assignee: Alcatel Lucent
    Inventors: Muriel Gohn, Thomas Gerner Noergaard, Dennis Olesen
  • Patent number: 8000672
    Abstract: In one embodiment, the present invention includes a receiver having two complementary input sense amplifiers to receive, amplify and latch a differential signal and to output complementary stage differential output signals to a latch coupled to receive and combine the n? them into a latched differential output signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventor: Taner Sumesaglam
  • Patent number: 7995982
    Abstract: The present invention aims to efficiently calibrate the characteristics of a pair of reception or transmission low-pass filters by a receiving or transmitting circuit. A semiconductor integrated circuit includes an RF receiver that processes an RF reception signal, an RF transmitter that generates an RF transmission signal and a frequency synthesizer. A reception low-pass filter of the RF receiver suppresses undesired components contained in I and Q baseband reception signals. A transmission low-pass filter of the RF transmitter suppresses noise due to D/A conversion, which is contained in I and Q transmission analog baseband signals. A calibration test signal is supplied to the inputs of the pair of reception or transmission low-pass filters. A difference in phase between the pair of filters is detected by a phase detection unit. A calibration controller calibrates a relative mismatch between the cut-off frequencies of the pair of filters.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Manabu Kawabe, Satoshi Tanaka, Yoshikazu Nara
  • Patent number: 7917114
    Abstract: The present invention relates to a DC offset canceling circuit. In one aspect of the invention, a DC offset canceling circuit with independently configurable gain and roll-off frequency is provided. In one embodiment of the present invention, the DC offset canceling circuit is used in the receive path of a down-conversion wireless receiver. In another aspect of the invention, a method for independently varying the gain and the roll-off frequency of the DC offset canceling circuit is provided. In one embodiment, the method is used to independently operate a gain control scheme and a DC offset cancellation strategy in a DC canceling circuit.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 29, 2011
    Inventors: Amit Bagchi, Rohit Gaikwad
  • Patent number: 7907924
    Abstract: A semiconductor device interconnecting unit configured to input/output a high-frequency signal having a millimeter wave band to/from a semiconductor device is provided. The semiconductor or device interconnecting unit includes a part of a band pass filter configured to pass therethrough the high-frequency signal having a millimeter wave band by using an LC resonance circuit, and a remainder of the band pass filter, wherein the part and the remainder are separated from each other. The part is provided inside the semiconductor device, and the remainder is provided outside the semiconductor device. The part and the remainder include capacitors having variable capacitors added thereto, respectively. A pass band for the high-frequency signal having a millimeter wave band is changed by changing capacitance values of the variable capacitors.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: March 15, 2011
    Assignee: Sony Corporation
    Inventor: Kenichi Kawasaki
  • Patent number: 7869784
    Abstract: A radio frequency (RF) circuit (100) as disclosed herein is fabricated on a substrate (204, 304) using integrated passive device (IPD) process technology. The RF circuit (100) includes an RF inductor (200, 300) and an integrated inductive RF coupler (202, 302) located proximate to the RF inductor (200, 300). The inductive RF coupler (202, 302), its output and grounding contact pads, and its transmission lines are fabricated on the same substrate (204, 304) using the same IPD process technology. The inductive RF coupler (202, 302) includes a coupling section (212, 306) that is either located inside or outside a spiral of the RF inductor (200, 300). The inductive RF coupler (202, 302) and the RF inductor (200, 300) are cooperatively configured to function as the windings of an RF transformer, thus achieving the desired coupling. The inductive RF coupler (202, 302) provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit (100).
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: January 11, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lianjun Liu
  • Patent number: 7848724
    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 7, 2010
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy van de Plassche, Pieter Vorenkamp, Arnoldus Venes
  • Patent number: 7783275
    Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 24, 2010
    Assignee: Broadcom Corporation
    Inventors: Myles Wakayama, Dana Vincent Laub, Frank Carr, Afshin Mellati, David S. P. Ho, Hsiang-Bin Lee, Chun-Ying Chen, James Y. C. Chang, Lawrence M. Burns, Young Joon Shin, Patrick Pai, Iconomos A. Koullias, Ron Lipka, Luke Thomas Steigerwald, Alexandre Kral
  • Patent number: 7754539
    Abstract: An electronic module that operates at various radio frequency standards is provided. The module includes a first integrated circuit die formed in a first semiconductor substrate and manufactured using a first semiconductor process. Disposed within the first integrated circuit is the first signal conditioning circuit for performing a function and the first and second ancillary circuits. The first ancillary circuit electrically coupled to the first signal conditioning circuit for use by the first signal conditioning circuit during operation thereof. The second ancillary circuit is for other than being used by the first signal conditioning circuit during operation thereof since the second integrated circuit die is electrically coupled to the second ancillary circuit and formed in the second semiconductor substrate and co-located with the first integrated circuit within the module.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: July 13, 2010
    Assignee: SiGe Semiconductor Inc.
    Inventor: Alan J. A. Trainor
  • Patent number: 7734268
    Abstract: A method and an apparatus for leveling an increasing or decreasing slope of an AM modulated receiving signal attenuate the AM modulated receiving signal with an attenuation curve with a stepwise slope corresponding to the increasing or decreasing slope of said AM modulated receiving signal, filters the attenuated AM modulated receiving signal within AM-demodulation with a lowpass infinite-impulse-response filter of at least second order and increases the level of each delay-unit's output signal of the infinite-impulse-response filter each time a step in the attenuated AM modulated receiving signal arrives at the input of said infinite-impulse-response filter.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: June 8, 2010
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Reiner Hausdorf, Leo Brueckner
  • Patent number: 7720453
    Abstract: A function processing unit includes a control-signal input/output unit to which a control signal indicating that radio data for a semiconductor device is transmitted is input by a cable signal, and a reset-signal input unit to which a reset signal instructing reset of the function processing unit is input by a cable signal, and when the reset signal is input, performs a reset process according to the reset signal. A radio-communication processing unit includes a radio-communication-processing-reset-signal input unit to which a radio communication processing reset signal instructing reset of the radio-communication processing unit is input by a cable signal, when the radio communication processing reset signal is input, performs a reset process according to the radio communication processing reset signal, and receives the radio data only when the control signal is input.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: May 18, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kunio Nakaoka
  • Patent number: 7536166
    Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, has a transistor (11; 51), preferably a power LDMOS transistor, and a spiral inductor (12; 26; 41; 52, 53), preferably an RF blocking inductor. The spiral inductor is arranged on top of the transistor, whereby an electromagnetic coupling between the spiral inductor and the transistor is not typically possible to avoid. However, the transistor has a finger type layout (13a-k, 14a-f) to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit is strongly reduced by such an arrangement.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: May 19, 2009
    Assignee: Infineon Technologies AG
    Inventor: Torkel Arnborg
  • Patent number: 7512389
    Abstract: An active inductor includes bipolar transistors T1, T2, T3 and TD (TD being arranged in diode), where T1's emitter is connected to an output port and to T2's collector. T2's base is connected to a first voltage line and between two connected capacitors. T2's emitter is connected to T3's collecter. An end of one capacitor is connected to T1's base and to a second voltage line. An end of the other capacitor is connected to T3's emitter and to a third voltage line. T1's collector is connected to a fourth voltage line and to TM's collecter, which is connected to TM's base. TM's emitter is electrically connected to T3's base. Preferably, the transistors T1-T3 and TD are Silicon based, and the active inductor is fabricated on a single substrate comprising Silicon. The active inductor is incorporated into adaptive oscillators and amplifiers and an improved transceiver.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: March 31, 2009
    Assignee: NEC Corporation
    Inventor: Laurent Desclos
  • Patent number: 7502601
    Abstract: In a power amplifier, a serial bus interface is provided for sending and receiving information to other devices, such as a baseband controller. The power amplifier includes several control pins that can be used as a serial interface, or alternately, with a direct pin control interface. The serial bus interface can be used with digital power control techniques that provide various advantages over conventional power amplifiers.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 10, 2009
    Assignee: Black Sand Technologies, Inc.
    Inventor: Timothy J. Dupuis
  • Patent number: 7493098
    Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: February 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasunobu Yoshizaki, Tetsuya Wakuda
  • Patent number: 7489914
    Abstract: The present invention allows for the use of chip-package co-design of RF transceivers and their components by using discrete active devices in conjunction with passive components. Two particular components are described, including voltage controlled oscillators (VCOs) and low noise amplifiers (LNAs). The high quality passive components for use in the VCOs and LNAs may be obtained by the use of embedded passives in organic substrates. Further, the embedded passives may have multi-band characteristics, thereby allowing multi-band VCOs and LNAs to be implemented with fewer components. In situations where size is a concern, the active devices and passive components utilized in an RF transceiver may be implemented in a low form factor module of less than 1.1 mm thick according to an embodiment of the invention.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: February 10, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Vinu Govind, Sidharth Dalmia, Amit Bavisi, Venkatesh Sundraram, Madhavan Swaminathan, George White