Abstract: A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, has a transistor (11; 51), preferably a power LDMOS transistor, and a spiral inductor (12; 26; 41; 52, 53), preferably an RF blocking inductor. The spiral inductor is arranged on top of the transistor, whereby an electromagnetic coupling between the spiral inductor and the transistor is not typically possible to avoid. However, the transistor has a finger type layout (13a-k, 14a-f) to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit is strongly reduced by such an arrangement.

Abstract: An active inductor includes bipolar transistors T1, T2, T3 and TD (TD being arranged in diode), where T1's emitter is connected to an output port and to T2's collector. T2's base is connected to a first voltage line and between two connected capacitors. T2's emitter is connected to T3's collecter. An end of one capacitor is connected to T1's base and to a second voltage line. An end of the other capacitor is connected to T3's emitter and to a third voltage line. T1's collector is connected to a fourth voltage line and to TM's collecter, which is connected to TM's base. TM's emitter is electrically connected to T3's base. Preferably, the transistors T1-T3 and TD are Silicon based, and the active inductor is fabricated on a single substrate comprising Silicon. The active inductor is incorporated into adaptive oscillators and amplifiers and an improved transceiver.

Abstract: In a power amplifier, a serial bus interface is provided for sending and receiving information to other devices, such as a baseband controller. The power amplifier includes several control pins that can be used as a serial interface, or alternately, with a direct pin control interface. The serial bus interface can be used with digital power control techniques that provide various advantages over conventional power amplifiers.

Abstract: In a communication semiconductor integrated circuit, a capacitance included in a filter on the output side of a mixer circuit is reduced without requiring the cutoff frequency of the filter to be changed. A Gilbert cell circuit is used as a mixer circuit which combines, for downconversion, a reception signal and a local oscillator signal. A low-pass filter for removing unwanted waves from output is composed of load resistors of upper stage differential transistors and a capacitive element provided between differential output terminals. The resistances of the load resistors are increased, and a current circuit for applying a current to emitters or collectors of the upper stage differential transistors is provided, so that a current to make up for a decrease in current amount attributable to the increase in load resistance can be applied from the current circuit to lower stage differential transistors.

Abstract: The present invention allows for the use of chip-package co-design of RF transceivers and their components by using discrete active devices in conjunction with passive components. Two particular components are described, including voltage controlled oscillators (VCOs) and low noise amplifiers (LNAs). The high quality passive components for use in the VCOs and LNAs may be obtained by the use of embedded passives in organic substrates. Further, the embedded passives may have multi-band characteristics, thereby allowing multi-band VCOs and LNAs to be implemented with fewer components. In situations where size is a concern, the active devices and passive components utilized in an RF transceiver may be implemented in a low form factor module of less than 1.1 mm thick according to an embodiment of the invention.

Abstract: A tri-state RF MEMS switch includes: a first well formed in a first substrate; a first input signal line and a first output signal line forming a first gap therebetween in the first well; a post bar forming a boundary between the second well and third well in the second substrate; a second input signal line and a second output signal line, and a third input signal line and a third output signal line forming a second gap and a third gap in the second well and the third well, respectively; and a membrane disposed between the first substrate and the second substrate such that the membrane crosses the first, second and third gaps, the membrane including a first conductive pad, a second conductive pad, and a third conductive pad thereon to face the first, second and third gaps, respectively.

Abstract: An apparatus includes a semiconductor package, a radio receiver and a processor. The radio receiver is located in the semiconductor package and includes at least one gain stage. The processor is located in the semiconductor package to execute stored instructions to control the gain stage(s).

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: In a signal receiving circuit of a direct conversion system applied with a semiconductor integrated circuit for radio communication having a PLL requiring a clock signal, an LNA requiring low-noise receiving characteristics, and others, a variable coupling line is provided between clock signal buffers and at an input stage of the PLL, so that coupling between the variable coupling line and an input terminal of the LNA and coupling between the variable coupling line and a GND terminal of the LNA are made equal to each other at frequencies of higher harmonic waves of a clock signal. When the input terminal and the GND terminal of the LNA are excited at the same phase, since no output occurs at an output terminal of the LNA, an output of the LNA does not contain any higher harmonic wave of a clock signal.

Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).

Abstract: An integrated circuit having a transmit chain configured to provide direct FM modulation of a voltage controlled oscillator of a frequency synthesizer by a composite signal that includes audio and video components, and a receive chain configured to provide a television compatible modulated signal having audio and video information. The receive chain can display locally transmitted signals.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: Disclosed herein is a direct conversion type signal processing semiconductor integrated circuit device capable of suppressing a DC voltage variation in the output of a variable gain amplifier upon the transition to a reception mode, reproducing stable receiving characteristics and improving receiving sensitivity. In the signal processing semiconductor integrated circuit device, voltage reference circuits for generating reference voltages for controlling or restricting currents for current sources for supplying operating currents for amplifiers constituting a reception-system circuit are boosted upon the transition from an idle mode or the like to the reception mode to allow the currents to flow into the constant-current sources of the amplifiers after the stabilization of the generated reference voltages.

Abstract: A first low noise amplifier (LNA1 111) is provided with a control terminal (1115) for turning of/off the low noise amplifier (LNA1 111). Power terminals of the low noise amplifier (LNA1 111) and a second low noise amplifier (LNA2 112) are commonly connected, and are connected to a power supply (10) via a power supply switch (1114). Ground terminals of the two amplifiers (LNA1 111) and (LNA2 112) are commonly connected, and a constant current source (1 115) is connected between the common terminal and the ground. The amplifiers (LNA1 111) and (LNA2 112) are turned on/off by switching the voltage applied to the control terminal (1115) of the first low noise amplifier (LNA1 111) between a high potential and a low potential. The power supply switch (1114) is turned off during signal transmission. Therefore, an LNA block can be provided by using only one power supply switch (1114), whereby it is possible to reduce the number of devices from that in the prior art, thereby realizing a reduction in the size thereof.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A reverse data rate controlling method in a mobile communication system for transmission of packet data is provided. In an embodiment of the present invention, an RRL (Reverse Rate Limit) message includes an ignore RAB (Reverse Activity Bit) field to ensure a predetermined data rate for a particular access terminal (AT). In another embodiment of the present invention, an access probability is set for each data rate in the RRL message. Upon receipt of an RAB, an AT compares a random number with the access probability for its data rate and increases or decreases the data rate according to the comparison result.

Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.

Abstract: An amplifier circuit unit including a signal amplifying transistor is provided with a first bypass circuit unit for bypassing a part of an input signal to a ground side according to the strength of the input signal, and a second bypass circuit unit for bypassing a part of the input signal to an output side according to the strength of the input signal, whereby gain attenuation control is effected. Also, the amplifier circuit unit is provided with a control circuit unit for decreasing the drain bias current of the signal amplifying transistor when the first bypass circuit unit bypasses the part of the input signal to the ground side, and interrupting the drain bias current of the signal amplifying transistor when the second bypass circuit unit bypasses the part of the input signal to the output side, whereby control of the drain bias current is effected.

Abstract: An RF antenna coupling structure includes a first transformer, a second transformer, and a transformer balun. The first transformer includes a primary winding and a secondary winding, wherein the primary winding of the first transformer is operably coupled to a power amplifier, and wherein the secondary winding of the first transformer has a desired output impedance corresponding to the operational needs of the power amplifier. The second transformer includes a primary winding and a secondary winding, wherein the primary winding of the second transformer is operably coupled to a low noise amplifier, and wherein the secondary winding of the second transformer has a desired output impedance corresponding to the needs of the low noise amplifier. The transformer balun includes a differential winding and a single-ended winding, wherein the differential winding is operably coupled to the secondary windings of the first and second transformers and the single-ended winding is operably coupled to an antenna.

Abstract: An integrated circuit superheterodyne radio receiver includes a notch filter coupled with an amplifier for amplifying radio frequency (RF) signals to improve image signal rejection. The notch filter includes a first oscillator circuit with a tank circuit having a resonant frequency corresponding to the unwanted image frequency signal. A control circuit includes a second oscillator circuit, a master bias circuit and a slave bias circuit. The second oscillator circuit is substantially similar to the first oscillator circuit. The master bias circuit is responsive to an amplitude of oscillatory signals in the second oscillator circuit for limiting a flow operating current such that the second oscillator circuit is restrained to operate in a marginally oscillatory state. A slave bias circuit is responsive to the master bias circuit for similarly limiting a flow of current, for operating the first oscillator circuit.

Abstract: The invention provides a circuit arrangement having circuit units (101a-101n) which are arranged in a package (100), a connecting device (200) for connecting the circuit units (101a-101n) to one another and for data interchange between the circuit units (101a-101n), and connection units (203) for connecting the circuit units to external circuit units and for supplying electrical power to the circuit arrangement, where data interchange between the circuit units (101a-10n) arranged within the package (100) is performed using electromagnetic waves which are transmitted by transmission units (201a-201n) and are received by reception units (202a-202n). The circuit units (101a-101n) arranged in the package (100) are in this case respectively equipped with the transmission units (201a-201n) and the reception units (202a-202n).

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A CMOS low noise amplifier (LNA) is provided that is formed without inductors. The CMOS LNA can be used for a single-chip CMOS RF receiver. The CMOS LNA can include a plurality of amplification stages coupled between an input terminal and an output terminal and a gain controller coupled to each of the plurality of amplifier stages, wherein the CMOS LNA does not include an inductor. Each of the amplification stages can have a symmetrically configured and sized first and second circuits to increase a dynamic range and a feedback loop.

Abstract: A MOSFET amplifier includes a pre-amplifier stage and a power amplifier stage. The pre-amplifier is a CMOS inverter having a signal output that is DC connected to the gate of a MOS control transistor of the power amplifier stage. The CMOS inverter includes an NMOS transistor with a source connected through an inductor to ground and a drain to the source of a PMOS transistor. The drain of the PMOS transistor is connected through another inductor to a supply voltage. The gates of the NMOS and PMOS transistors are connected to both receive an input signal of the amplifier.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: The disclosed invention provides a wireless communication receiver that is able to lessen the effect of noise that accompanies gain change by programmable gain amplifiers. Such noise is produced when direct conversion type programmable gain amplifiers by which gains are adjustable in steps are used for gain control of signals of CDMA or the like in which reception is not intermitted.

Abstract: An apparatus to provide a stage in a transmitter or receiver operating in wireless frequency ranges performing a gain control function between a final or an initial stage respectively and process circuitry for adjusting gain and providing a constant input impedance at its input and a constant output impedance at its output, providing a direct conversion transceiver in which constant impedance gain control circuits are provided in the receive and transmit paths, all of which are simple in construction and efficient in operation.

Abstract: An interference protection system for rejecting microwave or radio frequency interference signals is embedded into a sealed packaged chip at any port susceptible to being coupled to an interference signal such as I/O pins or antenna. The interference protection system includes a sense unit for detecting signals with amplitudes exceeding a predetermined threshold level and a protection unit including a pair of MOSFET switches connected in series and maintained in ON state during normal communication state. The switches are switched OFF once the sense unit detects the interference event. A registry unit is included for registering interference events.

Abstract: A data carrier (1) for contactless communication with a communication station (2) has an integrated circuit (7) and has a direct voltage generation circuit (20), and has detection means (28) for detecting a temperature prevailing in the data carrier (1) and in the integrated circuit (7), with the aid of which detection means (28) a representation signal (RS) representative of the prevailing temperature can be generated, which representation signal causes an initiation of a change of the temperature in the data carrier (1) and in the integrated circuit (7).

Abstract: A radio frequency module packaging system and method characterized by compact package size, reduced packaging loss and variation, and reduced heat generation. The radio frequency module is provided with via holes, electrodes for signals, and grounding electrodes on the surface of a substrate. Under the electrodes for signals, via holes are made, and on both sides of the electrodes for signals, grounding via holes are made so that these via holes form microstrip lines. Both input and output ends of a high frequency circuit including an active device, formed as the module's functional circuit on the substrate, are routed through the via holes and connected to another circuit.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: In an RF front end portion for processing a radio-frequency signal in a portable telephone, a low pass filter allowing passing of only a signal in a frequency band lower than a radio-frequency signal component band is arranged between a circuit processing a high power signal and a control circuit controlling operation of the radio-frequency signal processing circuit. The radio-frequency signal processing circuit is a transmission/reception multiplexing circuit transferring a transmission signal of the portable telephone to an antenna or receiving a reception signal from the antenna, and the control circuit is a transmission/reception control circuit determining an operation mode of the transmission/reception multiplexing switch. Alternatively, the radio-frequency signal processing circuit includes a power amplifier amplifying a signal to be transmitted, and a gate voltage control circuit generating gate bias voltage controlling a gain of the power amplifier.