Abstract: Apparatus and systems are provided for a single amplifier filter capable of a high quality factor. A filter comprises an amplifier having an amplifier input and an amplifier output, wherein the amplifier is configured to produce an output signal at the amplifier output based on a signal at the amplifier input. A first resistive element is coupled between an input node and the amplifier input, a second resistive element is coupled between a first node and the amplifier input, and a third resistive element is coupled between the amplifier output and the first node. A first capacitive element is coupled between the amplifier output and the amplifier input. The filter comprises a second node for an inverse of the output signal, wherein a second capacitive element is coupled between the first node and the second node.

Abstract: Methods and apparatuses for frequency synchronizing basestations in a cellular communication system. In one aspect of the invention, a method to predict a timing of transmission of a basestation in a cellular communication system includes: receiving a first time tag for a first timing marker in a first cellular signal transmitted from the basestation; receiving a second time tag of a second timing marker in a second cellular signal transmitted from the basestation; and computing a frequency related to the basestation using the first and second time tags. Each of the time tags are determined using at least one satellite positioning system signal received at a mobile station which receives the corresponding time marker.

Abstract: A MIMO radio transceiver to support processing of multiple signals for simultaneous transmission via corresponding ones of a plurality of antennas and to support receive processing of multiple signals detected by corresponding ones of the plurality of antennas. The radio transceiver provides, on a single semiconductor integrated circuit, a receiver circuit or path for each of a plurality of antennas and a transmit circuit or path for each of the plurality of antennas. Each receiver circuit downconverts the RF signal detected by its associated antenna to a baseband signal. Similarly, each transmit path upconverts a baseband signal to be transmitted by an assigned antenna.

Abstract: Multiple antenna elements of a WTRU are used to form an adaptive antenna beam pattern for receiving signals in the downlink direction. The WTRU utilizes the formed antenna beam to form a transmission antenna beam for transmitting signals in the uplink direction. In an alternate embodiment, the multiple antenna elements are used to form a plurality of fixed, predetermined antenna beams. The WTRU then selects and switches to the one of the predetermined beams that yields the best downlink reception signals. The WTRU utilizes the selected beam pattern to transmit signals in the uplink direction. In an alternate embodiment, the WTRU receives spectral arrangement information and utilizing this information to avoid transmitting in the direction of spectrally adjacent WRTUs.

Abstract: A wireless communications device may include a housing and a wireless transmitter and a wireless receiver carried by the housing. The wireless receiver may include a joint demodulation filter for reducing co-channel interference between a desired signal and a co-channel interfering signal which may include an input receiving samples of the desired signal and the co-channel interfering signal, a Viterbi decoder, and a first signal path between the input and the Viterbi decoder comprising a first filter. The joint demodulation filter may further include a second signal path between the input and the Viterbi decoder and comprising a linear finite impulse response (FIR) modeler for generating a channel impulse response estimate for the co-channel interfering signal. Additionally, a third signal path may be between the input and the Viterbi decoder and include a whitened matched filter for generating a channel impulse response estimate for the desired signal.

Abstract: A duplexer includes two surface acoustic wave (SAW) filters having different center frequencies; a phase matching circuit that matches phases of the two SAW filters; a package in which the SAW filters and the phase matching circuit are housed, the package being composed of multiple layers; and a line pattern provided between at least one of the SAW filters and at least one of a transmit terminal and a receive terminal of the duplexer. The line pattern runs on at least two of the multiple layers within a range defined by peripheral ground patterns provided in the package.

Abstract: A radio frequency (RF) transceiver includes an RF transmitter that generates an outbound RF signal at a carrier frequency that is based on a transmitter local oscillation. An RF front-end receives an inbound RF signal that includes a desired signal component that is based on the outbound RF signal and that includes an undesired signal component. The RF front-end includes a first RF combiner module that attenuates the undesired signal component to produce a desired RF signal. A down conversion module generates a down converted signal from the desired RF signal based on a receiver local oscillation. A receiver processing module generates inbound data from the down converted signal. A frequency control module controls a frequency of the transmitter local oscillation and a frequency of the receiver local oscillation, based on an interference rejection signal, to control the attenuation of the undesired signal component.

Abstract: A wireless communication apparatus receives a radio signal, compensates a frequency offset of received radio signal, stores, in a memory, a frequency offset of the received radio signal which includes an address used as a destination of a transmission signal, compensates a frequency of the transmission signal having the address as the destination by using the frequency offset stored in the memory, and transmits the transmission signal whose frequency is compensated.

Abstract: The digital signal processor is for correcting a DC output at an output terminal of an internal circuit of an analog circuit device. The digital signal processor includes a digital register for storing a digital value, a D/A converter for converting the digital value stored in the digital register into an analog voltage and applying the converted analog voltage to the output terminal as the DC output, a polarity determining circuit which outputs a first signal when an analog DC voltage at a reference correction point different from the output terminal in the internal circuit is higher than a predetermined threshold value and otherwise outputs a second signal, and an updating function configured to monotonously increase or decrease the digital value stored in the digital register while a predetermined one of the first and second signals is outputted from the polarity determining circuit.

Abstract: A RF circuit includes a master PCB, a plurality of slave PCBs and a plurality of antennas. The master PCB includes at least two RF ICs and at least two transceiving diplexer groups for tranceiving different frequency bands. Each transceiving diplexer group includes a plurality of transceiving diplexers transceiving a same frequency band and electrically connected to the RF ICs via PCB tracks without intersection. Each slave PCB includes a frequency division diplexer electrically connected to at least two transceiving diplexers respectively belonging to different tranceiving diplexer groups for respectively transmitting different frequency bands. Each antenna electrically connects to one of the division diplexers.

Abstract: A stable frequency is outputted by an oscillator circuit including a constant current circuit which is electrically connected between a first terminal and a second terminal, a voltage controlled oscillator circuit in which an oscillation frequency fluctuates in accordance with a potential difference between power supply voltage terminals, an n-channel transistor, a p-channel transistor in which a gate-source voltage is set to be constant by the constant current circuit, and a capacitor, in which a source electrode of the p-channel transistor is electrically connected to the first terminal, a drain electrode of the p-channel transistor is electrically connected a drain electrode and a gate electrode of the n-channel transistor, a source electrode of the n-channel transistor is electrically connected to the second terminal, and a gate electrode of the n-channel transistor is electrically connected to the second terminal through the capacitor.

Abstract: A method, wireless communication device (402) and base station (502) for signal processing and transmission is provided. The method includes detecting (604) simultaneous operation of a radio transmitter of the wireless communication device within a first predefined frequency band and a radio receiver of the wireless communication device within a second predefined frequency band. Further, the method includes reducing (606), based on the detecting, a bandwidth of an operating signal of the radio transmitter from a standard bandwidth value to a reduced bandwidth value. The bandwidth is reduced based on a bandwidth reduction factor. Furthermore, the method includes transmitting (608) the operating signal within the first predefined frequency band from the radio transmitter.

Abstract: A method including: processing at a first processing frequency, such that each instance of processing is separated by a first processing time period, at least a first signal; increasing the processing frequency to a second processing frequency and switching from processing the first signal to processing a second signal; determining a parameter indicative of the quality of the second signal; and determining, within the first processing time period measured from the last instance of processing the first signal at the first frequency, which one or more signals to process at the next instance of processing by comparing respective parameters of at least the first and second signals.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A wireless communication apparatus includes a plurality of antenna branches for transmitting and receiving a wireless communication signal, a calibration coefficient calculator for calculating a calibration coefficient for each frequency band, the calibration coefficient correcting an imbalance in phase and amplitude existing between the antenna branches, a coefficient storage memory for storing the calibration coefficient of each frequency band, a calibration coefficient reader for reading the calibration coefficient of a frequency band of one of a transmission signal and a reception signal as a target to be calibrated, a calibration coefficient interpolator for interpolating a calibration coefficient of the frequency band if the coefficient storage memory stores no corresponding calibration coefficient of the frequency band, and a calibration coefficient multiplier for multiplying one of the transmission signal and the reception signal by one of the read calibration coefficient and the interpolated calibrat

Abstract: A portable wireless communication apparatus is provided with antenna elements; a mobile phone signal processing circuit; a DTV tuner for receiving DTV low-band frequency signals and DTV high-band frequency signals; impedance matching circuits for the mobile phone signal processing circuit; and impedance matching circuits for the DTV tuner for receiving the DTV low-band frequency signals and DTV high-band frequency signals. A switch is changed to select either the DTV low-band frequency signals or the DTV high-band frequency signals, and output the selected signals to the DTV tuner. A tuner controller controls the switch to select the DTV high-band frequency signals by using the antenna element for transmission from the mobile phone signal processing circuit.

Abstract: A transmitter device for wireless communication equipment, comprises at least one path (Pl) comprising i) a low-pass filter (LPF 1+, LPFl?) for filtering differential signals and applying a chosen first attenuation to each of them to decrease their amplitudes, ii) a differential transconductor (TC1+, TCl?) arranged for applying a chosen second attenuation to each differential signal coming from the low-pass filter (LPF1+, LPFl?) to decrease its continuous component, and iii) a mixer (Ml) for mixing separately the differential signals delivered by the transconductor with local oscillator carriers at a chosen radio frequency to deliver output RF signals to be transmitted. The transconductor (TC1+, TCl?) comprises two original cells (OC) for defining two original signals from the differential signals having the first attenuation, and N first and N second signal copy cells (CC1-CC6) each arranged for generating a copy of one of the original signals.

Abstract: A wireless communication apparatus compensates for phase and amplitude imbalances existing among transmit and receive branches, while also preventing likelihood information and SNR estimation error produced by such imbalance compensation. In an apparatus having a plurality of transmit and receive antennas and respective branches for each antenna, a calibration processor multiplies receive signals in each receive branch by antenna calibration coefficients, in order to correct phase and amplitude imbalances existing among the receive branches. A transmit beamforming matrix estimator then estimates a transmit beamforming matrix by using the multiplied receive signals.

Abstract: Circuits and methods are disclosed for reducing interference from transmitter leakage in a radio transceiver. An exemplary method for reducing interference from transmitter leakage in a radio transceiver comprises downconverting, filtering, and sampling a radio frequency signal comprising a desired signal and a transmitter leakage signal to obtain a sampled signal of interest. The method further comprises generating a sampled distortion signal estimate that estimates one or more distortion products of the transmitter leakage signal, such as a squared amplitude obtained from a square-law device or corresponding digital function. Finally, the method comprises combining the sampled distortion signal estimate with the sampled signal of interest to obtain interference-reduced signal samples.

Abstract: The invention relates to an antenna system comprising a ground-plane (1100) and at least two antenna elements (1101) connected to a common input/output port (1106) for said antenna system. Each of said antenna elements (1101) comprise one driven point (1102). The antenna system further comprises means (1103) for transmitting the signal from the antenna elements (1101) towards said common input/output port (1106), and a combining means (1105) to interconnect the signals to said common input/output port (1106). Further, the system comprises at least one phase shifting element (1104) placed between at least one of said driven points (1102) and said combining means (1105) and arranged to provide a phase shift that minimizes the sum of the reflection coefficients of said at least two antenna elements (1101) measured at said common input/output port (1106).

Abstract: A transceiver and a method of transmitting data are provided. A frequency band, such as a licensed frequency band, is monitored during a sensing block. Based upon the use of the frequency band during the sensing block, a probability of non-interfering is calculated during a plurality of time periods in a subsequent inter-sensing block. The probability of non-interfering is used by the transceiver to determine a transmit power level such that the possibility of interference with licensed use on the frequency band is reduced. Embodiments of the present invention may be used to improve the transmission rate of the cognitive radio user.

Abstract: An oscillator circuit, a transceiver, and a method for generating an oscillatory signal are provided to avoid the VCO pulling effect. The oscillator circuit includes an oscillator, a frequency multiplier, a frequency divider, and a mixer module. The oscillator is utilized for generating a first signal having a first frequency. The frequency multiplier is coupled to the oscillator, and utilized for generating a second signal according to the first signal, wherein the second signal has a second frequency. The frequency divider is coupled to the oscillator, and utilized for generating a third signal according to the first signal, wherein the third signal has a third frequency. The mixer module is coupled to the frequency multiplier and the frequency divider, and utilized for mixing the second signal and the third signal to generate the oscillatory signal having an output frequency being not a harmonic of the first frequency.

Abstract: Systems and methods are disclosed to maintain synchronous communications that uses a global positioning system satellite, a primary communication unit, and a secondary communication unit. The satellite based time reference broadcasts a reference signal to the primary communication unit and the secondary communication unit. The primary communication unit contains a high quality oscillator, and operates a virtual model of a secondary oscillator which is located in the secondary communication unit. The primary and secondary units have synchronous communications with each other by using a global positioning system satellite broadcast as a reference signal. If the secondary unit loses its signal from the global positioning system, the secondary oscillator enters a holdover state and transmits a notification of the holdover state to the primary communications unit.

Abstract: Embodiments relate to a wireless communication device. The embodiment provides a wireless communication device comprising: a reception signal processor demodulating a received signal; a first signal state detector detecting a reception state of a first signal from the received signal; a second signal state detector detecting a reception state of a second signal from the received signal; a transmission signal processor modulating a transmission signal; and a controller controlling a change of a frequency of a channel transmitted to the transmission signal processor depending on a reception state of at least one of the first signal of the first signal state detector and the second signal of the second signal state detector.

Abstract: A wireless communication device that obtains an analog received signal by receiving a wireless signal, adjusts amplitude by a variable gain amplifier, converts the analog received signal into a digital received signal by an A/D converter and obtains user data by demodulating the digital received signal, including: a received signal strength indication detecting section that detects a received signal strength indication that fluctuates over time; a gain controlling section that controls a gain of the variable gain amplifier; a propagation environment judging section that judges a propagation environment level of the wireless signal, and a time constant controlling section that controls a time constant, based on the judged propagation environment level such that the time constant becomes larger as the propagation environment level becomes lower, the time constant regulating a change speed of the gain at the variable gain amplifier.

Abstract: A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor.

Abstract: In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more amplitude calibration techniques prior to enabling the PLL. For example, an amplitude calibration unit may be used to selectively activate switched unit current sources within a tail current source of the VCO. In this manner, the amplitude the signal generated by the oscillator can be adjusted without requiring closed-loop amplitude monitoring or control.

Abstract: The present invention pertains to a method of calibrating reception properties of a radio frequency (RF) processor. The application describes two embodiments of the invention representing calibration of the properties using an auxiliary transmitter to generate a calibration signal internal to the RF processor.

Abstract: The present invention is related to a method and apparatus for automatic frequency correction of a local oscillator. The apparatus receives a carrier signal. The carrier signal includes a code sequence known to the apparatus. The apparatus downconverts the carrier signal to a baseband signal using the local oscillator. The apparatus performs a block correlation of the samples of the baseband signal with the known code sequence to generate a frequency error signal. The frequency error signal is fed back to the local oscillator to correct the frequency error.

Abstract: A method for automatically tuning a frequency modulator in a mobile device is described. A frequency band is automatically scanned using a frequency modulation (FM) receiver. The FM receiver is integrated as a part of the mobile device. Quality associated with channels of the frequency band is analyzed to identify at least one available channel at a first frequency. The first frequency is assigned to an FM modulator. The FM modulator is integrated as a part of the mobile device. A determination is made whether a command to scan for a second frequency is received. If the command to scan for the second frequency is not received, a signal on the first frequency is transmitted by the FM modulator.

Abstract: A transceiver for radio-frequency communication comprises a waveguide, a transmitting port, a receiving port and a receiver load termination. The waveguide receives and transmits radio-frequency signals. The transmitting port is connected to the waveguide and transmits the radio-frequency signals to the waveguide. The receiving port is connected to the waveguide and receives the radio-frequency signals from the waveguide. The receiver load termination is connected to the waveguide and removes the vertical polarization components of the receiving radio-frequency signals. The receiver load termination includes a filtering unit to reduce the energy of the transmitting radio-frequency signals entering the receiver load termination.

Abstract: According to one embodiment of the invention, a system for controlling carrier leakage in a communications device is provided. The system includes a first mixer unit operable to receive a first signal, to convert the first signal into a second signal having a higher frequency than the first signal, and to transmit the second signal. The system also includes a second mixer unit. The second mixer unit is operable to receive the second signal, to convert the second signal into an in-phase signal and a quadrature signal each having lower frequency than the second signal, and to transmit the in-phase signal and the quadrature signal. The system also includes a processor coupled to the first mixer and the second mixer.

Abstract: A dielectric resonator having a line pattern that includes an electrode gap that defines a signal input/output portion provided on an open side, and a ground portion provided on a short-circuited side. The length L in a main direction of a portion of the line pattern in which the signal input/output portion and the ground portion face each other is smaller than one quarter the wavelength of a resonant signal of the resonator. A variable-capacitance element is connected to the signal input/output portion. One end of the variable-capacitance element has a positive potential and the other end of the variable-capacitance element has a negative potential.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

Abstract: A radio circuit includes a mixing module, a first adjustable resonant circuit and a second adjustable resonant circuit. The mixing module is coupled to mix a first signal having a first carrier frequency with a second signal having a second carrier frequency to produce a mixed signal having a frequency sum component and a frequency difference component. The first adjustable resonant circuit is tuned to resonant at a frequency corresponding to one of the frequency sum component and the frequency difference component. The second adjustable resonant circuit is tuned to resonant at a frequency corresponding to another one of the frequency sum component and the frequency difference component, wherein the first and second adjustable resonant circuits alter the mixed signal to produce a converted signal.

Abstract: It is to provide a mobile telephone device with the broadcasting receiver having high sensitivity over a broad band. A meander element 14 is disposed in parallel to an opening surface 5a of a loop element 5, and the two elements 5 and 14 are connected directly in a feeding point 9 so as to be supplied with power in parallel. Thus, the two elements 5 and 14 operate as antennas taking charge of upper and lower divided bands of a frequency band respectively.

Abstract: A clock offset compensation arrangement may include a fractional interpolator for applying a trigonometric interpolation to a sampled input signal according to a clock offset signal. It uses transform-based processing in the frequency domain. Compared to a polynomial type interpolation it may be easier to implement, and may achieve a closer approximation to an ideal interpolation. It may reduce the effects of non-linear type errors introduced by truncation of higher powers. The arrangement may be applied to receivers or transmitters of multi-carrier modems, as well as other applications which use rate adaptation or synchronization.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: Implementations related to circuits including an oscillator and a switch-mode DC/DC converter are presented herein.

Abstract: A radio system includes a radio frequency (RF) integrated circuit (IC), a baseband digital signal processing (DSP) IC, and a serial digital interface coupling data there-between. In one embodiment of the invention, the RF IC has an input receiver to receive a serial digital transmission bit stream from a digital signal processing integrated circuit; a data recoverer coupled to the input receiver to recover digital data bits from the serial digital transmission bit stream; a low pass filter coupled to the data recoverer convert the digital data bits into an analog transmission signal; a mixer coupled to the low pass filter to up-convert the analog transmission signal from a baseband frequency to a second selectable carrier frequency as a transmit radio frequency signal; and an amplifier coupled to the mixer and an antenna, the amplifier to amplify the transmit radio frequency signal for broadcast over the antenna.

Abstract: A multicarrier transmitter may transmit cyclically delayed linear combinations of two or more data streams with three or more antennas. In some embodiments, the multicarrier transmitter may transmit cyclically delayed linear combinations of three data streams with four antennas.

Abstract: An approach is providing for supporting broadcast transmission of low density parity check (LDPC) coded signals. A receiver includes a decoder configured to decode an LDPC signal to output a decoded signal. The decoder is further configured to operate as an encoder; as such, interference cancellation can be implemented by the encoder re-encoded the received decoded signal. The above approach has particular applicability to satellite broadcast systems.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A PLL circuit according to the present invention includes: a voltage controlled oscillator 10; a frequency divider 30 that divides an oscillation signal of the voltage controlled oscillator 10 and outputs a divided oscillation signal; a first phase comparator 40 that outputs a phase difference between the divided oscillation signal of the frequency divider 30 and a reference signal; a charge pump 60 that converts the output signal of the first phase comparator 40 into a signal for controlling the voltage controlled oscillator 10; a filter that allows a DC component of the output signal of the charge pump 60 to pass therethrough and outputs a voltage to the voltage controlled oscillator 10; a second phase comparator 90 that averages the phase difference between the divided oscillation signal of the frequency divider 30 and the reference signal with respect to time; and a current control circuit 100 that controls an operating current of the frequency divider 30 based on the phase difference averaged with respec

Abstract: A wireless communication system includes plural wireless communication apparatuses. Each wireless communication apparatus includes a transmitter 10 including a spread unit 14 for spreading a transmission sequence to be transmitted with a predetermined spread sequence, a pseudo periodic sequence generating unit 13 for generating a periodic sequence in which the transmission sequence to be transmitted is repeated a predetermined number of times, and a modulating unit 15 for modulating, with a carrier frequency, the transmission sequence to be transmitted. Each wireless communication apparatus includes a receiver 20 including a demodulating unit 22 configured to demodulate a reception wave modulated with the carrier frequency and a despreading unit 27 for despreading the spread signal sequence. The transmission sequence to be transmitted includes a pilot signal used for measuring multipath properties and a transmission data signal.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: Embodiments of RFID tag circuits and methods are described, which include a chip having a clock circuit operable to generate a clock signal having different frequencies, and one or more components operable to work at the different frequencies. In addition to a regular frequency, at least one higher frequency is possible, which is enabled in situations where a reader is known to be close to the chip. The proximity ensures that the chip generates reliably more power, which enables its operation at the higher speed.

Abstract: A circuit (100) comprising an antenna (105) for receiving a carrier signal modulated by a data signal, a direct conversion receiver (180) for receiving the modulated carrier signal, a signal generator circuit (140, 145, 150) arranged to generate a mixing signal having a frequency substantially the same as the carrier signal, a mixing module (125i, 125q) having an in-phase and a quadrature phase signal path (120i, 120q) arranged to mix the mixing signal at different phases with the received modulated carrier signal in order to generate an in-phase and a quadrature baseband signal, a frequency offset circuit (155, 200) arranged to generate an offset signal having a frequency offset from the frequency of the carrier signal, a coupling circuit (170a, 170b, 170c) arranged to selectively decouple the antenna from the direct conversion receiver and to couple the offset signal to the mixing module in order to generate a baseband test signal in the in-phase and quadrature signal paths for determining an imbalance in t

Abstract: Embodiments may be used to control a controllable element that has a nonlinear but monotonic relationship with a control value. In such embodiments, a system may perform control by receiving an error value corresponding to an error of an output signal from the controllable element, and determining the control value within two iterations of a Newton (Secant) algorithm, where the control value enables generation of the output signal within a predetermined tolerance to a nominal value for the control signal.

Abstract: Aspects of a method and system for a flexible automatic frequency control (AFC) design supporting transmit diversity are presented. Aspects of the system may include one or more circuits that enable computation of at least one frequency error value based on one or more previous computed frequency error values, current received symbols, and/or corresponding previously received symbols. A weighted sum may be computed from a plurality of computed frequency error values. A current demodulation frequency may be adjusted based on the computed weighted sum. The adjusted demodulation frequency may be utilized for receiving one or more subsequent symbols.