Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

Abstract: A control method of a distributed antenna system (DAS) including a baseband modem, according to one embodiment, may comprise the steps of: calculating frequency offsets for each RF path in the baseband modem; controlling an oscillator clock of a central unit (CU) on the basis of an average of the frequency offsets; determining an operation mode of the baseband modem; and controlling oscillator clocks of each distributed unit (DU) on the basis of the frequency offsets for each RF path when the operation mode of the baseband modem is a tracking mode.

Abstract: An electronic device may include wireless circuitry with a baseband processor, a transceiver, and an antenna. The transceiver may include a mixer that outputs signals to a transimpedance amplifier. The mixer has an output impedance that varies depending on the frequency of operation. An adjustable resistance can be coupled to the input of the transimpedance amplifier. A control circuit can tune the adjustable resistance to compensate for changes in the output impedance of the mixer as the transceiver operates across a wide range of frequencies.

Abstract: A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE).

Abstract: Provided are a terminal, a terminal peripheral, a signal transmission system, and a signal sending and receiving method. The terminal includes: a first audio module, which is connected to the USB receptacle in a terminal through an I2S bus channel and is configured to send a signal to be sent to a USB receptacle; the USB receptacle is configured to provide a physical connection interface between the terminal and a terminal peripheral.

Abstract: Provided is a technique capable of reporting resource block allocation information with no waste when an allocated resource block is reported, because in the current LTE downlink, the waste of the amount of resource allocation information increases in some cases since a restriction is imposed such that 37-bit fixed scheduling information is transmitted. A resource block group consisting of at least one or more resource blocks continuous on the frequency axis is allocated to a terminal, and the number of controlling signals for reporting allocation information indicating the allocated resource blocks is determined.

Abstract: A semiconductor device includes a clock generator which receives an input clock and generates an output clock, a reference voltage generator which receives the input clock or the output clock, generates a sub-reference voltage in accordance with a frequency of the input clock or a frequency of the output clock, and generates a reference voltage using the sub-reference voltage and a preset error voltage, and a clock detector which receives the output clock, generates a first output voltage in accordance with the output clock, and compares the generated first output voltage with the reference voltage to output an error signal based on the output clock, wherein the preset error voltage is set in accordance with a degree of preset error of the output clock.

Abstract: A hyperbolic waveform multiple-input multiple-output radar includes a generator circuit, multiple transmit circuits, a multiple-input multiple-output antenna, and multiple receive circuits. The generator circuit may be operable to generate a linear frequency modulated signal and a hyperbolic frequency modulated signal. The transmit circuits may be operable to generate multiple transmit signals by analog mixing the linear frequency modulated signal and the hyperbolic frequency modulated signal in response to a plurality of coding family parameters, wherein the transmit signals define an orthogonal family of waveforms. The multiple-input multiple-output antenna may be operable to transmit the transmit signals toward an object and receive multiple receive signals from the object. The receive circuits may be operable to determine multiple data signals in response to the receive signals, wherein the data signals are suitable to determine a distance between the multiple-input multiple-output antenna and the object.

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

Abstract: A server maintains a gallery of ephemeral messages. Each ephemeral message is posted to the gallery by a user for viewing by recipients via recipient devices. In response to a gallery view request from any of the recipient devices, the ephemeral messages in the gallery are displayed on the requesting device in automated sequence, each message being displayed for a respective display duration before display of the next message in the gallery. A user interface via which the gallery is viewable includes indicia with respect to the number of screenshots taken with respect to messages in the gallery during online viewing.

Abstract: A phase locked device includes a digital controlled oscillator circuit, a clock signal generator circuitry, a time to digital converter circuit, and a logic control circuit. The digital controlled oscillator circuit is configured to generate a first clock signal in response to a plurality of digital codes. The clock signal generator circuitry is configured to generate a plurality of second clock signals according to the first clock signal, and to select a third clock signal and a fourth clock signal from the plurality of second clock signals according to a selection signal, in order to generate an output signal. The time to digital converter circuit is configured to detect a delay difference between the output signal and a reference signal, in order to generate the plurality of digital codes. The logic control circuit is configured to generate the selection signal according to the plurality of digital codes.

Abstract: A transceiver includes a receive circuit configured to receive an incoming signal and recover a reference signal at a reference frequency from the incoming signal. The incoming signal is a wireless packet. A first oscillator generates a signal at a set of predetermined frequencies. A first phase lock loop (PLL) interfaced with the first oscillator. The first PLL is configured to adjust a first oscillator frequency of the first oscillator based on an incoming frequency of the incoming signal using the reference frequency. A transmit circuit includes a second oscillator configured to generate a carrier signal at a predetermined frequency and a modulator configured to modulate data over the carrier signal at the predetermined frequency. The transmit circuit includes a second PLL interfaced with the second oscillator that sets the second oscillator to generate the carrier signal at the predetermined frequency using the reference signal. The transmit circuit transmits the modulated carrier signal.

Abstract: This disclosure provides a method for gain control in a wireless receiver. The wireless receiver comprises a first receiver chain adapted to receive a first signal in a first frequency range, a second receiver chain adapted to receive a second signal in a second frequency range, and a common amplifier module operatively connected to the first receiver chain and the second receiver chain. The method comprises determining a first target gain level for a first path comprising the common amplifier module and the first receiver chain, and determining a second target gain level for a second path comprising the common amplifier module and the second receiver chain. The method comprises setting a gain GA of the common amplifier module and a gain GRx1 in the first receiver chain and a gain GRx2 in the second receiver chain based on the first target gain level and the second target gain level.

Abstract: A radio-frequency module includes a plurality of inputs and a plurality of outputs, each of at least two of the inputs of the plurality of inputs coupled to a separate output of the plurality of outputs through a separate single-pole-single-throw switch.

Abstract: The disclosure generally relates to connecting wireless devices based on a correlation between different audio sources. For example, according to various aspects, a first wireless device may capture sound via a microphone and receive audio content from a second wireless device via a wireless receiver. Accordingly, a wireless connection may be established between the first and second wireless devices based on a substantial match between the sound captured via the microphone and the audio content received via the wireless receiver. For example, the sound captured via the microphone may be output from a speaker on the second wireless device. In other examples, the received audio content may be sound captured via a local microphone at the second wireless device. In either case, the correlation between the audio received through the microphone and the audio content received over a radio may substantially simplify the procedure(s) used to connect two audio-enabled devices.

Abstract: A method for avoiding inter-modulation distortion in a communications apparatus capable of supporting carrier aggregation and communicating with a peer communications apparatus in a wireless network via at least a first CC and a second CC includes: determining a frequency adjustment value for adjusting a first oscillating frequency of a first local oscillation signal utilized for processing an RF signal of the first CC or a second oscillating frequency of a second LO signal utilized for processing an RF signal of the second CC when an RF signal or a baseband signal of the second CC is interfered with by an inter-modulation distortion signal contributed by any signal component related to the first CC; and adjusting the first oscillating frequency or the second oscillating frequency according to the frequency adjustment value.

Abstract: Where a communications device maintains multiple wireless connections to other devices and networks which use slotted communications protocols, the slots used by those protocols are arranged so as to minimise the power consumed by the device. Where multiple radios are used, power is minimised by avoiding using radios at the same time when those radios are likely to interfere with each other. Slots used by communication protocols can also be selected to maximise the time that the communications device can spend in lower power mode.

Abstract: A polar transmitter for an RFID reader and a system using the polar transmitter are disclosed. An RFID system according to at least some embodiments of the invention includes a polar transmitter, a receiver to receive responses from RFID tags, and a coupler connected to the polar transmitter, the receiver and one or more antennas. In at least some embodiments, the polar transmitter of the RFID system includes an envelope amplifier with a multi-phase buck converter to provide an envelope signal and a phase modulator connected to a power amplifier to phase modulate the power amplifier using a phase signal. In at least some embodiments, the polar transmitter of the RFID system transmits OPR-ASK signals to reduce AM modulation depth and provide a continuous phase signal for the phase modulator.

Abstract: According to one embodiment, a frequency doubler circuit includes a first field effect transistor (FET) having a first gate, a first source, and a first drain and a second FET having a second gate, a second source, and a second drain, where the first gate of the first FET and the second source of the second FET are driven by an input signal in a first phase, and the first source of the first FET and the second gate of the second FET are driven by the input signal in a second phase, where the first and the second FETs are caused to switch based on the first phase and the second phase of the input signal respectively to generate an output signal at the first drain and the second drain having a frequency that is approximately double of the input signal.

Abstract: An apparatus includes a first oscillator to generate an output signal that has a first frequency. The apparatus further includes a second oscillator to generate an output signal that has a second frequency. The second frequency varies as a function of temperature. The apparatus further includes a controller that counts a number of cycles of the output signal of the second oscillator in order to determine whether to calibrate the first oscillator.

Abstract: A system and method for controlling a heating, ventilating, and air conditioning (HVAC) system in a dwelling is provided. The system includes a plurality of wireless thermostats disposed throughout multiple zones within the dwelling and operable to control climate conditions in the corresponding zones. The system further includes a primary power source operable to supply power to thermostats for operating in a high-power mode when operatively connected thereto. The thermostats each include a secondary power source operable to supply power to the thermostats for operating in a low-power mode when the corresponding thermostat is not powered by the primary power source. Thermostats operating in the high-powered mode are operable to receive and repeat signals originating from one or more thermostats operating in the low-power mode.

Abstract: Embodiments of a wireless device and method for transmitting a packet comprising one or more orthogonal frequency division multiplexed (OFDM) transmission symbols are generally described herein. In some embodiments, the wireless device may be configured to map data to active tones and map zeroes to nulled tones of a set of OFDM tones to generate an OFDM symbol comprising both the active and the nulled tones. The number of active and nulled tones may be based on a nulling factor. The OFDM symbol may be down-clocked to generate an OFDM transmission symbol for transmission over a reduced transmission bandwidth. Accordingly, low power may be used for very low data rate transmissions, which may be suitable for sensor devices.

Abstract: An information processing apparatus includes a first communication unit, a second communication unit, and a communication-apparatus-side controller. The first communication unit performs wireless communication with plural terminal apparatuses, the number of which is less than or equal to a predetermined maximum number of connections. The second communication unit performs wireless communication with a connection-requesting terminal apparatus that newly attempts to perform wireless communication with the first communication unit. The communication-apparatus-side controller switches the wireless communication via the second communication unit to wireless communication via the first communication unit, the wireless communication via the first communication unit being performed using a dedicated line prepared in advance.

Abstract: A system includes a first filter circuitry and one or more second filter circuitry. The first filter circuitry can operate at a frequency of a wireless signal to filter the wireless signal to attenuate undesired feedthrough components and pass through a desired component. The system can also include a multi-phase mixer to convert the frequency of the wireless signal to a lower frequency and divide the wireless signal into at least four phase shifted baseband signal components. The second filter circuitry can operate at the lower frequency to filter the phase shifted baseband signal components to attenuate undesired feedthrough components and pass through a desired component. The system can also include a matrix to combine the baseband signal components to form an output signal.

Abstract: In the field of millimeter band transmitting/receiving systems for a high-speed contactless transmission, an architecture is provided with a common processing circuit supplying modulation signals and a plurality of transmitting/receiving integrated circuits, all identical to one another, receiving these signals, and also a common clock. The transmitting/receiving integrated circuits each comprise: an oscillator locked with the clock signal to produce a carrier frequency, a transmit channel comprising a first controllable phase shift circuit, a frequency transposition to the carrier frequency, and a power amplifier, a receive channel comprising a low noise amplifier, a frequency transposition from the carrier frequency, and a second controllable phase shift circuit. An antenna is associated with each transmitting/receiving circuit.

Abstract: Embodiments of the present invention provide a receiver and a receiving method of the receiver, so that monolithic integration of multiple receiving channels can be implemented. The receiver includes: a zero intermediate frequency channel, performing in-phase/quadrature (IQ) down conversion on a radio frequency signal at a first frequency band using a frequency division or frequency multiplication signal of a first oscillation signal; and a superheterodyne channel, performing down conversion on a radio frequency signal at a second frequency band using the frequency division or frequency multiplication signal of the first oscillation signal, where the first frequency band is different from the second frequency band.

Abstract: An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.

Abstract: A circuit for reducing counter-intermodulation in a modulated signal caused by an oscillator frequency and harmonics of a baseband signal is disclosed. The circuit comprises a first and a second baseband section arranged for generating a first and a second version of a baseband signal, the second version being phase shifted with respect to the first version. The circuit further comprises three signal paths comprising mixers for multiplication of the first and second version of the baseband signal with a local oscillator signal, so that three upconverted signals with rotated phase with respect to each other are obtained, and arranged for applying a scaling with a scaling factor corresponding to the rotated phases. The circuit further comprises a combination unit arranged for combining the three upconverted signals.

Abstract: A device for receiving an Internet radio broadcast is provided. The device comprises a communication interface, at least one input control mounted on the device. a display, and at least one processor in communication with the communication interface, the at least one input control, and the display, and memory containing software executable by the at least one processor.

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery module further comprises a discontinuity detector configured to detect a delay discontinuity in timing messages received in the slave device from the master device, and a loop controller operative to place the clock recovery loop in a particular state responsive to the detected discontinuity.

Abstract: The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.

Abstract: A frequency synthesis device including: a first generator configured to generate a periodic signal of frequency f1; a second and third generator, coupled with the first generator and configured to receive as an input the periodic signal of frequency f1 and to generate a signal SG corresponding to a train of oscillations of frequency substantially equal to N·f1, of a time less than T1=1/f1 and repeated periodically at the frequency f1, where N is a whole number greater than 1; and a fourth generator configured to generate, from the signal SG, a periodic signal wherein a frequency spectrum includes a primary line of frequency f2=(N+i)·f1, where i is a whole number.

Abstract: According to one embodiment, a transmitter includes a first buffer, a second buffer, a logic circuit, and a class E power amplifier. The first buffer receives a first sinusoidal signal, and converts the first sinusoidal signal to a first rectangular wave signal. The second buffer receives a second sinusoidal signal having a phase delay with respect to the first sinusoidal signal, and converts the second sinusoidal signal to a second rectangular wave signal. The logic circuit receives the first and second rectangular wave signals, and performs logical operation processing on the first and second rectangular wave signals to generate a logic signal with a predetermined duty cycle. The class E power amplifier receives the logic signal, and performs amplification operation based on the logic signal.

Abstract: A multi-stage diagnostic system and related method which seeks diagnostic information from a secondary information source when a first information source does not yield sufficient data for producing a diagnostic result. In particular, diagnostic process includes a first stage of communicating with an onboard vehicle computer to retrieve diagnostic trouble codes therefrom. If no diagnostic trouble codes are retrieved from the onboard computer, the diagnostic process proceeds to a second stage wherein symptomatic diagnostic information is solicited from the user. A series of symptomatic questions may be presented to the user on a smartphone. The answers from the symptomatic questions may be used to identify a most likely solution, which may be associated with a repair part(s). The corresponding repair part(s) may be identified by an associated universal part number(s) based on vehicle identification information associated with the vehicle needing repair.

Abstract: A demodulating system (100) for demodulating a phase-modulated input signal (Si) comprises: a complex demodulator (110), having a first input (111) for receiving the phase-modulated input signal (Si) and being designed to perform complex multiplication of this signal with an approximation of the inverse of the phase modulation; a spectrum analyzing device (130) receiving the demodulated product signal produced by the complex demodulator (110) and capable of analyzing the frequency spectrum of the demodulated product signal.

Abstract: According to some embodiments, there is provided a signal generating device, including a signal generator and a local signal generating unit. The signal generator generates a signal of a fixed frequency. The local signal generating unit generates, based on the signal of the fixed frequency, a first local signal to convert a frequency of a first signal, and a second local signal to convert a frequency of a second signal. The second signal is a signal resulting from that the first signal is subjected to frequency conversion based on the first local signal and has a frequency different from the first local signal.

Abstract: A wireless communication device includes a BBIC for performing baseband signal processing, an RFIC for performing radio-frequency signal processing, and a quartz resonator. The RFIC has a storage unit which stores an adjustment value for adjustment of a clock frequency that is based on an oscillation frequency of the quartz resonator, and outputs the adjustment value when its resetting active state is canceled; a frequency adjusting unit for adjusting the clock frequency according to the adjustment value; and an RF signal processing unit which operates based on the clock signal and performs the radio-frequency signal processing.

Abstract: A transceiver includes: a first transforming network arranged for using a first input impedance to receive a first modulated signal and using a first output impedance to output a first transformed signal during a transmitting mode of a first communication standard, and for using the first input impedance to receive a second modulated signal and using a second output impedance to output a second transformed signal during the transmitting mode of a second communication standard; a second transforming network arranged for using a second input impedance to receive the second transformed signal and using a third output impedance to output a first RF signal to a connecting port of the transceiver during the transmitting mode of the second communication standard; a power amplifier, arranged to generate a second RF signal; and a switching circuit for selectively coupling the second transformed signal to the second transforming network.

Abstract: In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal.

Abstract: According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.

Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.

Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.

Abstract: A method and arrangement for transmitting and receiving RF signals, associated with different radio interfaces of communication systems, employ a direct conversion based transceiver which substantially comprises one receive signal branch and one transmit signal branch. Mixing frequencies of the different systems are generated by a single common by use of an output frequency divider in combination with the synthesizer, and by use of filtering corresponding to a system channel bandwidth by means of a controllable low-pass filter operating at baseband frequency.

Abstract: In the field of millimeter band transmitting/receiving systems for a high-speed contactless transmission, an architecture is provided with a common processing circuit supplying modulation signals and a plurality of transmitting/receiving integrated circuits, all identical to one another, receiving these signals, and also a common clock. The transmitting/receiving integrated circuits each comprise: an oscillator locked with the clock signal to produce a carrier frequency, a transmit channel comprising a first controllable phase shift circuit, a frequency transposition to the carrier frequency, and a power amplifier, a receive channel comprising a low noise amplifier, a frequency transposition from the carrier frequency, and a second controllable phase shift circuit. An antenna is associated with each transmitting/receiving circuit.

Abstract: A frequency translation device includes a transmit circuit including a first frequency converter configured to convert a signal at a first frequency into a signal at a second frequency. A receive circuit includes a second frequency converter configured to convert a signal at the second frequency into a signal at the first frequency. A detector circuit is configured to determine when the frequency translation device is receiving a signal, and to route the signal to the transmit circuit or to the receive circuit.

Abstract: One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output.

Abstract: A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.