Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for machine learning processes. A Quantum Statistic Machine (QSM) is described, consisting of three distinct classes of strongly interacting degrees of freedom including visible, hidden and control quantum subspaces or subsystems. The QSM is defined with a programmable non-equilibrium ergodic open quantum Markov chain with a unique attracting steady state in the space of density operators. The solution of an information processing task, such as a statistical inference or optimization task, can be encoded into the quantum statistics of an attracting steady state, where quantum inference is performed by minimizing the energy of a real or fictitious quantum Hamiltonian. The couplings of the QSM between the visible and hidden nodes may be trained to solve hard optimization or inference tasks.

Abstract: Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

Abstract: Fully-supervised semantic segmentation machine learning models are augmented by ancillary machine learning models which generate high-detail predictions from low-detail, weakly-supervised data. The combined model can be trained over both fully- and weakly-supervised data. Only the primary model is required for inference, post-training. The combined model can be made self-correcting during training by adjusting the ancillary model's output based on parameters learned over both the fully- and weakly-supervised data. The self-correction module may combine the output of the primary and ancillary models in various ways, including through linear combinations and via neural networks. The self-correction module and ancillary model may benefit from disclosed pre-training techniques.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for machine learning processes. A Quantum Statistic Machine (QSM) is described, consisting of three distinct classes of strongly interacting degrees of freedom including visible, hidden and control quantum subspaces or subsystems. The QSM is defined with a programmable non-equilibrium ergodic open quantum Markov chain with a unique attracting steady state in the space of density operators. The solution of an information processing task, such as a statistical inference or optimization task, can be encoded into the quantum statistics of an attracting steady state, where quantum inference is performed by minimizing the energy of a real or fictitious quantum Hamiltonian. The couplings of the QSM between the visible and hidden nodes may be trained to solve hard optimization or inference tasks.

Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.

Abstract: Techniques and a system to facilitate meta-level quantum computation are provided. In one example, a system includes a quantum processor and a classical processor. The quantum processor can perform an expectation computation process to compute an expected value of a deflated operator and a quantum state associated with a quantum circuit description. The classical processor can execute computer executable components stored in a memory, where the computer executable components comprise a meta-level variational optimization component. The meta-level variational optimization component can perform a meta-level optimization process associated with a k-eigenvalue decomposition process to iteratively determine an inflation parameter and a variational parameterization for an eigenpair based on samples of the expectation computation process.

Abstract: A method includes generating a bias signal from a first device, and applying the bias signal to a second device, the first device having (a) a superconducting trace and (b) a superconducting quantum interference device (SQUID), in which a first terminal of the SQUID is electrically coupled to a first end of the superconducting trace, and a second terminal of the SQUID is electrically coupled to a second end of the superconducting trace, where generating the bias signal from the first device includes: applying a first signal ?1 to a first sub-loop of the SQUID; and applying a second signal ?2 to a second sub-loop of the SQUID, in which the first signal ?1 and the second signal ?2 are applied such that a value of a superconducting phase of the first device is incremented or decremented by a non-zero integer multiple n of 2?.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: A method for estimating a thermodynamic property of a quantum Ising model with transverse field is disclosed.

Abstract: In some aspects, a flexible cable may comprise: a flexible strip with first and second parallel surfaces and first and second ends, said flexible strip being electrically insulating; a metal stripline within said flexible strip; first and second metallic grounding planes on said first and second surfaces, respectively; and a first circuit board mechanically attached to at least one of said first end of said flexible strip and said first and second metallic grounding planes at said first end, said first circuit board being mechanically stiff, said metal stripline being electrically connected to electrical circuitry on said first circuit board.

Abstract: Methods and systems for solving various computational problems with quantum processors are provided. Such quantum processors comprise a plurality of quantum devices together with a plurality of coupling devices. The quantum processor is initialized by setting states of the quantum devices and coupling devices and allowed to evolve to a final state which approximates a natural ground state of the computational problem. The final state can include values of nodes arranged in a lattice in the quantum processor and can represent a solution to the computational processor. The computational problem can have complexity P, NP, NP-Hard, or NP-Complete and may be mapped to a quantum processor with nearest-neighbor and next-nearest-neighbor couplings. The solution to the computational problem can be read out from the quantum processor and transmitted as a data signal embodied in a carrier wave.

Abstract: A method for enhancing hybrid-classical algorithms for combinatorial optimization includes executing, on a quantum processor, a variational algorithm, the execution producing a subset of a set of solutions (solution space) of the variational algorithm within a predefined period, the variational algorithm computing a quantum state of a quantum system corresponding to a combinatorial optimization problem, each solution in the subset having a corresponding value; sorting, according to a sorting criterion, the subset of solutions; isolating, based on the sorting, a portion of the subset of solutions wherein a value corresponding to each solution in the portion is within a boundary defined by a threshold value; computing an average value of the solutions from the portion of the subset of solutions; and altering the variational algorithm to produce a second subset of solutions such that the second subset of solutions comprises solutions having values within the boundary.

Abstract: Techniques for performing cost function deformation in quantum approximate optimization are provided. The techniques include mapping a cost function associated with a combinatorial optimization problem to an optimization problem over allowed quantum states. A quantum Hamiltonian is constructed for the cost function, and a set of trial states are generated by a physical time evolution of the quantum hardware interspersed with control pulses. Aspects include measuring a quantum cost function for the trial states, determining a trial state resulting in optimal values, and deforming a Hamiltonian to find an optimal state and using the optimal state as a next starting state for a next optimization on a deformed Hamiltonian until an optimizer is determined with respect to a desired Hamiltonian.

Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples.

Abstract: Real-time reconfigurability of quantum object connectivity can be provided with one or more quantum routers that can each be configured as either or both of a single-pole double-throw switch and a cross-point switch. The quantum router includes variable-inductance coupling elements in RF-SQUIDs having inductors transformer-coupled to two control flux lines, one providing a static current and the other providing a dynamic current, the direction of which can be toggled to couple or uncouple quantum objects, such as qubits, based on the dynamic current direction to provide reconfigurable quantum routing.

Abstract: In a general aspect, an integrated microwave circuit is disclosed for processing quantum information. The integrated microwave circuit includes a substrate having a first surface and a second surface opposite the first surface. The substrate is formed of a silicon oxide material having a loss tangent no greater than 1×10?5 at cryogenic temperatures at or below 120 K. The integrated microwave circuit also includes qubit circuitry disposed on the first surface that includes a Josephson junction. A ground plane is disposed on the first surface or the second surface. In some variations, the silicon oxide material is fused silica. In other variations, the silicon oxide material is crystalline quartz.

Abstract: A cascading microwave switch (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies, wherein different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set, wherein the series coupling causes the first Josephson device in an open state to reflect back to an input port of the first Josephson device a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) and the nth Josephson device in the open state to reflect back to an input port of the nth Josephson device a signal of an nth frequency from the multiplexed signal.

Abstract: A method includes generating a bias signal from a first device, and applying the bias signal to a second device, the first device having (a) a superconducting trace and (b) a superconducting quantum interference device (SQUID), in which a first terminal of the SQUID is electrically coupled to a first end of the superconducting trace, and a second terminal of the SQUID is electrically coupled to a second end of the superconducting trace, where generating the bias signal from the first device includes: applying a first signal ?1 to a first sub-loop of the SQUID; and applying a second signal ?2 to a second sub-loop of the SQUID, in which the first signal ?1 and the second signal ?2 are applied such that a value of a superconducting phase of the first device is incremented or decremented by a non-zero integer multiple n of 2?.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using a quantum oracle to make inference in complex machine learning models that is capable of solving artificial intelligent problems. Input to the quantum oracle is derived from the training data and the model parameters, which maps at least part of the interactions of interconnected units of the model to the interactions of qubits in the quantum oracle. The output of the quantum oracle is used to determine values used to compute loss function values or loss function gradient values or both during a training process.

Abstract: Generating trial states for a variational quantum Eigenvalue solver (VQE) using a quantum computer is described. An example method includes selecting a number of samples S to capture from qubits for a particular trial state. The method further includes mapping a Hamiltonian to the qubits according the trial state. The method further includes setting up an entangler in the quantum computer, the entangler defining an entangling interaction between a subset of the qubits of the quantum computer. The method further includes reading out qubit states after post-rotations associated with Pauli terms in the target Hamiltonian, the reading out being performed for S samples. The method further includes computing an energy state using the S qubit states. The method further includes, in response to the estimated energy state not converging with an expected energy state, computing a new trial state for the VQE and iterating to compute the estimated energy using the new trial state.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: A method and system are disclosed for continuous optimization. The method comprises obtaining an optimization problem involving continuous or semi-continuous variables in a digital computer; initiating a stochastic search process in the digital computer in order to solve the optimization problem; until a stopping criterion is met constructing in the digital computer at least one stochastically generated polynomial in binary variables representative of choices of candidate future state of the stochastic search process, providing the at least one polynomial in binary variables to a binary sampling device, sampling from domains of the at least one polynomial in binary variables using the binary sampling device to generate binary sample points, receiving the generated binary sample points in the digital computer and transiting to next state of the stochastic search process and providing a best known solution found as a solution of the optimization problem using the digital computer.

Abstract: A superconducting integrated circuit including a clock distribution network for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network may include a clock structure having unit cells, where each of the unit cells may include at least one spine and at least one stub. The clock structure may further include at least one spine connected to the at least one stub, where the at least one stub may further be inductively coupled to at least one superconducting element. The clock signal may have a wavelength. Each of the unit cells may be spaced apart from each other along the clock structure by a distance, where the distance may be less than one tenth of the wavelength.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

Abstract: A quantum computer may include topologically protected quantum gates and non-protected quantum gates, which may be applied to topological qubits. The non-protected quantum gates may be implemented with a partial interferometric device. The partial interferometric device may include a Fabry-Pérot double point contact interferometer configured to apply “partial” interferometry to a topological qubit.

Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.

Abstract: A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.

Abstract: Systems and methods for reading out the states of superconducting flux qubits may couple magnetic flux representative of a qubit state to a DC-SQUID in a variable transformer circuit. The DC-SQUID is electrically coupled in parallel with a primary inductor such that a time-varying (e.g., AC) drive current is divided between the DC-SQUID and the primary inductor in a ratio that is dependent on the qubit state. The primary inductor is inductively coupled to a secondary inductor to provide a time-varying (e.g., AC) output signal indicative of the qubit state without causing the DC-SQUID to switch into a voltage state. Coupling between the superconducting flux qubit and the DC-SQUID may be mediated by a routing system including a plurality of latching qubits. Multiple superconducting flux qubits may be coupled to the same routing system so that a single variable transformer circuit may be used to measure the states of multiple qubits.

Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.

Abstract: A method of characterizing a tunable superconducting circuit, includes selecting an operating direct current (DC) flux for a first charge island from a plurality of coupled charge islands residing in the tunable superconducting circuit coupled to a first resonator and a second resonator, tuning operating DC flux values for at least two charge islands from the plurality of coupled charge islands, measuring coupling energies of the first resonator and the second resonator and measuring frequencies from each of the plurality of coupled charge islands.

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: Quantum processor based techniques minimize an objective function for example by operating the quantum processor as a sample generator providing low-energy samples from a probability distribution with high probability. The probability distribution is shaped to assign relative probabilities to samples based on their corresponding objective function values until the samples converge on a minimum for the objective function. Problems having a number of variables and/or a connectivity between variables that does not match that of the quantum processor may be solved. Interaction with the quantum processor may be via a digital computer. The digital computer stores a hierarchical stack of software modules to facilitate interacting with the quantum processor via various levels of programming environment, from a machine language level up to an end-use applications level.

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: A quantum electronic circuit device includes a housing having an internal resonant cavity, a qubit disposed within a volume of the internal resonant cavity and a non-superconducting metallic material mechanically and thermally coupled to the qubit within the internal resonant cavity and contiguously extending to the exterior of the housing.

Abstract: A superconducting magnetic shielding system includes first and second planar superconducting shields respectively positioned above and below an environment to be shielded. The shields are each thermally coupled to a cold source at a respective thermalizing point. When the shields are cooled into the superconducting regime, they passively block magnetic fields via the Meissner Effect. Each shield may also be shaped to produce a smooth temperature gradient extending away from its thermalizing point; thus, as the shields are cooled, magnetic fields may be expelled away from the thermalizing point and, consequently, away from the environment to be shielded. A heater may also be provided opposite the thermalizing points to improve control of the temperature gradient.

Abstract: An energy efficient data center incorporating superconducting power transmission cables coupled with cryogenically cooled semiconductor inverters and converters, used to supply power to cryogenically operated or room-temperature computers and servers. Other options and features include a lighting system whose performance is enhanced by the cold temperatures, fiber optic connections operated at cryogenic temperatures, integrated renewable energy power sources, advanced energy storage technologies, cryogenically operated computers, and a number of other cryogenic hardware. The operating temperature of the cryogenic components can be anywhere in the range between 0 K and 200 K, with other components operating above 200 K.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: An integrated circuit for quantum computing may include a superconducting shield to limit magnetic field interactions.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A method is disclosed for making a template for a superconducting coil on a former (25) from a sheet (23) of flexible biaxially-textured material having at least two joining edges, the surface texture of the sheet being defined by a plurality of grains, and the former having a substantially curved surface. The method comprises the steps of shaping the sheet so that each joining edge lies adjacent to another joining edge on application of the sheet to the former, each joining edge and its adjacent edge being a pair of edges, and so that the sheet is dimensioned to cover a part of the surface of the former and substantially to fit that part of the former; positioning the sheet on the former so that regions of the sheet either side of the pair of edges have substantially aligned grains; and forming a join between the pair of edges, the template thereby having a substantially continuous textured surface across the join.