Information Processing (e.g., Logic Circuits, Computer, Etc.) Or Information Storage Or Retrieval System, Device, Or Component (i.e., Both Dynamic And Static) Patents (Class 505/170)
  • Patent number: 10339466
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using a quantum oracle to make inference in complex machine learning models that is capable of solving artificial intelligent problems. Input to the quantum oracle is derived from the training data and the model parameters, which maps at least part of the interactions of interconnected units of the model to the interactions of qubits in the quantum oracle. The output of the quantum oracle is used to determine values used to compute loss function values or loss function gradient values or both during a training process.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: July 2, 2019
    Assignee: Google LLC
    Inventors: Nan Ding, Masoud Mohseni, Hartmut Neven
  • Patent number: 10332023
    Abstract: Generating trial states for a variational quantum Eigenvalue solver (VQE) using a quantum computer is described. An example method includes selecting a number of samples S to capture from qubits for a particular trial state. The method further includes mapping a Hamiltonian to the qubits according the trial state. The method further includes setting up an entangler in the quantum computer, the entangler defining an entangling interaction between a subset of the qubits of the quantum computer. The method further includes reading out qubit states after post-rotations associated with Pauli terms in the target Hamiltonian, the reading out being performed for S samples. The method further includes computing an energy state using the S qubit states. The method further includes, in response to the estimated energy state not converging with an expected energy state, computing a new trial state for the VQE and iterating to compute the estimated energy using the new trial state.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Antonio Mezzacapo, Jay M. Gambetta, Abhinav Kandala, Maika Takita, Paul K. Temme
  • Patent number: 10325218
    Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Rigetti & Co, Inc.
    Inventors: William J. Zeng, Chad Tyler Rigetti
  • Patent number: 10275423
    Abstract: A method and system are disclosed for continuous optimization. The method comprises obtaining an optimization problem involving continuous or semi-continuous variables in a digital computer; initiating a stochastic search process in the digital computer in order to solve the optimization problem; until a stopping criterion is met constructing in the digital computer at least one stochastically generated polynomial in binary variables representative of choices of candidate future state of the stochastic search process, providing the at least one polynomial in binary variables to a binary sampling device, sampling from domains of the at least one polynomial in binary variables using the binary sampling device to generate binary sample points, receiving the generated binary sample points in the digital computer and transiting to next state of the stochastic search process and providing a best known solution found as a solution of the optimization problem using the digital computer.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: April 30, 2019
    Assignee: IQB INFORMATION TECHNOLOGIES INC.
    Inventor: Pooya Ronagh
  • Patent number: 9722589
    Abstract: A superconducting integrated circuit including a clock distribution network for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network may include a clock structure having unit cells, where each of the unit cells may include at least one spine and at least one stub. The clock structure may further include at least one spine connected to the at least one stub, where the at least one stub may further be inductively coupled to at least one superconducting element. The clock signal may have a wavelength. Each of the unit cells may be spaced apart from each other along the clock structure by a distance, where the distance may be less than one tenth of the wavelength.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: August 1, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vladimir V. Talanov, Joshua A. Strong
  • Publication number: 20150119252
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Application
    Filed: March 7, 2013
    Publication date: April 30, 2015
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Publication number: 20150111754
    Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Inventors: Richard G. Harris, Mohammad H.S. Amin, Anatoly Smirnov
  • Publication number: 20140354326
    Abstract: A quantum computer may include topologically protected quantum gates and non-protected quantum gates, which may be applied to topological qubits. The non-protected quantum gates may be implemented with a partial interferometric device. The partial interferometric device may include a Fabry-Pérot double point contact interferometer configured to apply “partial” interferometry to a topological qubit.
    Type: Application
    Filed: December 16, 2013
    Publication date: December 4, 2014
    Applicant: Microsoft Corporation
    Inventors: Parsa Bonderson, Michael H. Freedman
  • Publication number: 20140357493
    Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: PATRICK B. SHEA, ERICA C. FOLK, DANIEL J. EWING, JOHN J. TALVACCHIO
  • Publication number: 20140315723
    Abstract: A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 23, 2014
    Applicant: The Regents of the University of California
    Inventors: Stephanie Moyerman, Brian Keating
  • Patent number: 8854074
    Abstract: Systems and methods for reading out the states of superconducting flux qubits may couple magnetic flux representative of a qubit state to a DC-SQUID in a variable transformer circuit. The DC-SQUID is electrically coupled in parallel with a primary inductor such that a time-varying (e.g., AC) drive current is divided between the DC-SQUID and the primary inductor in a ratio that is dependent on the qubit state. The primary inductor is inductively coupled to a secondary inductor to provide a time-varying (e.g., AC) output signal indicative of the qubit state without causing the DC-SQUID to switch into a voltage state. Coupling between the superconducting flux qubit and the DC-SQUID may be mediated by a routing system including a plurality of latching qubits. Multiple superconducting flux qubits may be coupled to the same routing system so that a single variable transformer circuit may be used to measure the states of multiple qubits.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: October 7, 2014
    Assignee: D-Wave Systems Inc.
    Inventor: Andrew J. Berkley
  • Publication number: 20140274725
    Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, George A. Keefe, Christian Lavoie, Mary E. Rothwell
  • Publication number: 20140235450
    Abstract: A method of characterizing a tunable superconducting circuit, includes selecting an operating direct current (DC) flux for a first charge island from a plurality of coupled charge islands residing in the tunable superconducting circuit coupled to a first resonator and a second resonator, tuning operating DC flux values for at least two charge islands from the plurality of coupled charge islands, measuring coupling energies of the first resonator and the second resonator and measuring frequencies from each of the plurality of coupled charge islands.
    Type: Application
    Filed: August 3, 2012
    Publication date: August 21, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry M. Chow, Antonio D. Corcoles Gonzalez, Jay M. Gambetta, Matthias Steffen
  • Publication number: 20140228222
    Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.
    Type: Application
    Filed: April 17, 2014
    Publication date: August 14, 2014
    Applicant: D-WAVE SYSTEMS INC.
    Inventors: Andrew J. Berkley, Mark W. Johnson, Paul I. Bunyk
  • Patent number: 8786476
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 22, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8772759
    Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 8, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Paul Bunyk, Felix Maibaum
  • Publication number: 20140187427
    Abstract: Quantum processor based techniques minimize an objective function for example by operating the quantum processor as a sample generator providing low-energy samples from a probability distribution with high probability. The probability distribution is shaped to assign relative probabilities to samples based on their corresponding objective function values until the samples converge on a minimum for the objective function. Problems having a number of variables and/or a connectivity between variables that does not match that of the quantum processor may be solved. Interaction with the quantum processor may be via a digital computer. The digital computer stores a hierarchical stack of software modules to facilitate interacting with the quantum processor via various levels of programming environment, from a machine language level up to an end-use applications level.
    Type: Application
    Filed: July 6, 2012
    Publication date: July 3, 2014
    Applicant: D-WAVE SYSTEMS INC.
    Inventors: William G. Macready, Mani Ranjbar, Firas Hamze, Geordie Rose, Suzanne Gildert
  • Patent number: 8738105
    Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: May 27, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Andrew J. Berkley, Mark W. Johnson, Paul I. Bunyk
  • Patent number: 8670807
    Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: March 11, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Geordie Rose, Paul I. Bunyk
  • Patent number: 8611974
    Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: December 17, 2013
    Assignee: D-Wave Systems Inc.
    Inventors: Felix Maibaum, Paul I. Bunyk, Thomas Mahon
  • Publication number: 20130313526
    Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
    Type: Application
    Filed: August 2, 2013
    Publication date: November 28, 2013
    Applicant: D-Wave Systems Inc.
    Inventors: Richard G. Harris, Andrew J. Berkley, Jan Johansson, Mark Johnson, Mohammad Amin, Paul I. Bunyk
  • Publication number: 20130303379
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Application
    Filed: July 16, 2013
    Publication date: November 14, 2013
    Inventors: John F. BULZACCHELLI, William J. GALLAGHER, Mark B. KETCHEN
  • Patent number: 8571614
    Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 29, 2013
    Assignee: Hypres, Inc.
    Inventors: Oleg A. Mukhanov, Alexander F. Kirichenko, Dmitri Kirichenko
  • Publication number: 20130196855
    Abstract: A quantum electronic circuit device includes a housing having an internal resonant cavity, a qubit disposed within a volume of the internal resonant cavity and a non-superconducting metallic material mechanically and thermally coupled to the qubit within the internal resonant cavity and contiguously extending to the exterior of the housing.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefano Poletto, Chad T. Rigetti, Matthias Steffen
  • Publication number: 20130190185
    Abstract: A superconducting magnetic shielding system includes first and second planar superconducting shields respectively positioned above and below an environment to be shielded. The shields are each thermally coupled to a cold source at a respective thermalizing point. When the shields are cooled into the superconducting regime, they passively block magnetic fields via the Meissner Effect. Each shield may also be shaped to produce a smooth temperature gradient extending away from its thermalizing point; thus, as the shields are cooled, magnetic fields may be expelled away from the thermalizing point and, consequently, away from the environment to be shielded. A heater may also be provided opposite the thermalizing points to improve control of the temperature gradient.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 25, 2013
    Applicant: D-WAVE SYSTEMS INC.
    Inventor: Patrick Pablo Chavez
  • Publication number: 20130017955
    Abstract: An energy efficient data center incorporating superconducting power transmission cables coupled with cryogenically cooled semiconductor inverters and converters, used to supply power to cryogenically operated or room-temperature computers and servers. Other options and features include a lighting system whose performance is enhanced by the cold temperatures, fiber optic connections operated at cryogenic temperatures, integrated renewable energy power sources, advanced energy storage technologies, cryogenically operated computers, and a number of other cryogenic hardware. The operating temperature of the cryogenic components can be anywhere in the range between 0 K and 200 K, with other components operating above 200 K.
    Type: Application
    Filed: July 12, 2011
    Publication date: January 17, 2013
    Inventors: Michael J. Hennessy, Eduard K. Mueller, Otward M. Mueller
  • Publication number: 20130005580
    Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 3, 2013
    Applicant: D-WAVE SYSTEMS INC.
    Inventors: Paul Bunyk, Richard David Neufeld, Felix Maibaum
  • Patent number: 8247799
    Abstract: An integrated circuit for quantum computing may include a superconducting shield to limit magnetic field interactions.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: August 21, 2012
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Mark W. Johnson, Jeremy P. Hilton
  • Publication number: 20120094838
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Application
    Filed: December 14, 2011
    Publication date: April 19, 2012
    Applicant: D-WAVE SYSTEMS INC.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Publication number: 20110177952
    Abstract: A method is disclosed for making a template for a superconducting coil on a former (25) from a sheet (23) of flexible biaxially-textured material having at least two joining edges, the surface texture of the sheet being defined by a plurality of grains, and the former having a substantially curved surface. The method comprises the steps of shaping the sheet so that each joining edge lies adjacent to another joining edge on application of the sheet to the former, each joining edge and its adjacent edge being a pair of edges, and so that the sheet is dimensioned to cover a part of the surface of the former and substantially to fit that part of the former; positioning the sheet on the former so that regions of the sheet either side of the pair of edges have substantially aligned grains; and forming a join between the pair of edges, the template thereby having a substantially continuous textured surface across the join.
    Type: Application
    Filed: November 23, 2006
    Publication date: July 21, 2011
    Applicant: COATED CONDUCTOR CYLINDERS LTD
    Inventor: Eamonn Maher
  • Patent number: 7932515
    Abstract: Multiple substrates that carry quantum devices are coupled to provide quantum mechanical communicators therebetween, for example, using superconducting interconnects, vias, solder and/or magnetic flux. Such may advantageously reduce a footprint of a device such as a quantum processor.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: April 26, 2011
    Assignee: D-Wave Systems Inc.
    Inventor: Paul I. Bunyk
  • Publication number: 20110065586
    Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.
    Type: Application
    Filed: June 2, 2009
    Publication date: March 17, 2011
    Applicant: D-WAVE SYSTEMS INC.
    Inventors: Felix Maibaum, Paul I. Bunyk, Thomas Mahon
  • Patent number: 7903456
    Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: March 8, 2011
    Assignee: Hypres, Inc.
    Inventors: Alexander F. Kirichenko, Timur V. Filippov, Deepnarayan Gupta
  • Publication number: 20090192041
    Abstract: A transverse coupling system may include a first qubit, a second qubit, a first conductive path capacitively connecting the first qubit and the second qubit, a second conductive path connecting the first qubit and the second qubit, and a dc SQUID connecting the first and the second conductive paths wherein the compound junction loop is threaded by an amount of magnetic flux.
    Type: Application
    Filed: September 30, 2008
    Publication date: July 30, 2009
    Inventors: Jan Johansson, Andrew J. Berkley
  • Publication number: 20090121215
    Abstract: A system employs a plurality of physical qubits, each having a respective bias operable to up to six differentiable inputs to solve a Quadratic Unconstrained Binary Optimization problem. Some physical qubit couplers are operated as intra-logical qubit couplers to ferromagnetically couple respective pairs of the physical qubits as a logical qubit, where each logical qubit represents a variable from the Quadratic Unconstrained Binary Optimization problem.
    Type: Application
    Filed: November 6, 2008
    Publication date: May 14, 2009
    Inventor: Vicky Choi
  • Publication number: 20090075825
    Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.
    Type: Application
    Filed: August 18, 2008
    Publication date: March 19, 2009
    Inventors: Geordie Rose, Paul I. Bunyk
  • Patent number: 7418283
    Abstract: A method for quantum computing using a quantum system comprising a plurality of qubits is provided. The system can be in any one of at least two configurations at any given time including one characterized by an initialization Hamiltonian HO and one characterized by a problem Hamiltonian HP. The problem Hamiltonian HP has a ground state. Each respective first qubit in the qubits is arranged with respect to a respective second qubit in the qubits such that they define a predetermined coupling strength. The predetermined coupling strengths between the qubits in the plurality of qubits collectively define a computational problem to be solved. In the method, the system is initialized to HO and is then adiabatically changed until the system is described by the ground state of the problem Hamiltonian HP. Then the state of the system is read out by probing an observable of the ?X Pauli matrix operator.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: August 26, 2008
    Assignee: D-Wave Systems Inc.
    Inventor: Mohammad H. S. Amin
  • Publication number: 20080176750
    Abstract: An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device. Such may provide a fully interconnected topology.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 24, 2008
    Inventors: Geordie Rose, Paul Bunyk, Michael D. Coury, William Macready, Vicky Choi
  • Patent number: 7335909
    Abstract: A quantum computing structure comprising a superconducting phase-charge qubit, wherein the superconducting phase-charge qubit comprises a superconducting loop with at least one Josephson junction. The quantum computing structure also comprises a first mechanism for controlling a charge of the superconducting phase-charge qubit and a second mechanism for detecting a charge of the superconducting phase-charge qubit, wherein the first mechanism and the second mechanism are each capacitively connected to the superconducting phase-charge qubit.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: February 26, 2008
    Assignee: D-Wave Systems Inc.
    Inventors: Mohammad H. S. Amin, Jeremy P. Hilton, Geordie Rose
  • Patent number: 7291891
    Abstract: A voltage is applied across gate electrodes (103A) and (103B) in a two-dimensional electronic system (101) placed under a magnetic field, and the polarity of an electric current passed between ohmic electrodes (102D) and (102S) is selected to bring about inversion of electron spins based on a non-equilibrium distribution of electrons in a quantum Hall edge state and to initialize the polarization of nuclear spins. An oscillatory electric field of a nuclear magnetic resonance frequency is applied to coplanar waveguides (104A) and (104B) to control the nuclear spin polarization. The controlled spin polarization is read out by measuring the Hall resistance from ohmic electrodes (102VA) and (102VB).
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: November 6, 2007
    Assignee: Japan Science and Technology Agency
    Inventors: Tomoki Machida, Susumu Komiyama, Tomoyuki Yamazaki
  • Patent number: 7015499
    Abstract: A solid-state quantum computing structure includes a d-wave superconductor in sets of islands that clean Josephson junctions separate from a first superconducting bank. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states. A second bank, which a Josephson junction separates from the first bank, can be coupled to the islands through single electron transistors for selectably initializing one or more of the supercurrents in a different quantum state. Single electron transistors can also be used between the islands to control entanglements while the quantum states evolve.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: March 21, 2006
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Publication number: 20030224944
    Abstract: A structure comprising a tank circuit inductively coupled to a flux qubit or a phase qubit. In some embodiments, a low temperature preamplifier is in electrical communication with the tank circuit. The tank circuit comprises an effective capacitance and an effective inductance that are in parallel or in series. In some embodiments, the effective inductance comprises a multiple winding coil of wire. A method that includes the steps of (i) providing a tank circuit and a phase qubit that are inductively coupled, (ii) reading out a state of the phase qubit, (iii) applying a flux to the phase qubit that approaches a net zero flux, (iv) increasing a level of flux applied to the phase qubit, and (v) observing a response of the tank circuit in a readout device.
    Type: Application
    Filed: December 16, 2002
    Publication date: December 4, 2003
    Inventors: Evgeni Il'ichev, Miroslav Grajcar, Alexandre M. Zagoskin, Miles F. H. Steininger
  • Patent number: 6563310
    Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 13, 2003
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 6563311
    Abstract: A solid-state quantum computing structure includes a d-wave superconductor in sets of islands that clean Josephson junctions separate from a first superconducting bank. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states. A second bank, which a Josephson junction separates from the first bank, can be coupled to the islands through single electron transistors for selectably initializing one or more of the supercurrents in a different quantum state. Single electron transistors can also be used between the islands to control entanglements while the quantum states evolve.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 13, 2003
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Publication number: 20030002674
    Abstract: A quantum cryptography multi-node communication system includes a quantum communication channel and a plurality of nodes including a transmission node and a reception node and connected with the quantum communication channel. The transmission node transmits a light signal as a time series of photons to the reception node through the quantum communication channel, a quantum state of the photons is modulated, and transmits a quantum state sequence to the reception node. The reception node predetermines a quantum state sequence, receives the light signal transmitted from the transmission node, measures quantum states of the received light signal, and determines presence or absence of interception based on the predetermined quantum state sequence, the transmitted quantum state sequence and the measured quantum states.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 2, 2003
    Applicant: NEC Corporation
    Inventors: Yoshihiro Nambu, Akihisa Tomita
  • Patent number: 6459097
    Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: October 1, 2002
    Assignee: D-Wave Systems Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 5937168
    Abstract: After an origination module (OM) receives information, a packet is transmitted to a routing architecture (RA) for routing to a destination module (DM) designated by the router packet. The RA interprets the router packet and adaptively routes the router packet to the DM so that the router packet is quickly processed by the DM. If the DM's queue is empty and the DM is not processing any other packets, the RA places the router packet in the queue and the DM reads its queue to process the router packet. If there is another router packet being processed by the DM, the RA adapts by placing the router packet in the queue. Once processing of the other router packet is complete, the DM processes the router packet in the queue. If there is already another router packet pending within the DM's queue, the RA adapts by creating another DM in memory to process the router packet.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 10, 1999
    Assignee: BellSouth Corporation
    Inventors: Dewey Charles Anderson, Senis Busayapongchai, Audrey Dibrell, David J. Anderson
  • Patent number: 5831278
    Abstract: A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-Superconducting) or any other type of high temperature superconductor junction. The control line is either a conducting or superconducting material which is electrically isolated from the junction but inductively coupled into the junction. A portion of the control line is approximately directly above the junction and has current which at least partially flows parallel or nonparallel to current flowing across the junction. The control line current alters the magnetic field within the junction which changes the critical current of the junction. The junction is in a superconducting or resistive state depending on whether the bias current of the junction is greater than or less than the control current.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: November 3, 1998
    Assignee: Conductus, Inc.
    Inventor: Stuart J. Berkowitz
  • Patent number: 5568302
    Abstract: An optical data transmission system includes an optical data receiver having a plurality of optical detectors and an optical switch which directs successive pulses of a serial data stream to different detectors. The switch includes one or more superconductive mirrors responsive to current pulses to change from a superconducting, reflective state to a non-superconducting, non-reflective state for the duration of a current pulse. In this manner, high speed optical data is received by detectors incapable of operating at the high speed of available optical data links and transmitters. The mirror is oriented at an angle to the data stream such that an optical pulse is reflected to one detector when the mirror is in the superconducting, reflective state and is passed through the mirror to another detector when the mirror is temporarily in the non-superconducting, non-reflective state under the control of a current pulse.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: October 22, 1996
    Assignee: International Business Machines Corporation
    Inventor: Kenneth A. Puzey
  • Patent number: 5442195
    Abstract: A superconducting device may include a superconducting weak link equipped with plural superconducting devices that are used as input-output terminals formed on the same plane and at least one current source for applying current to at least one of these superconducting electrodes. A superconducting device suitable for high integration can be realized as it enables structuring of a superconducting weak link 1 equipped with plural superconducting electrodes 101, 102, 103 and 104 that can be used as input-output terminals and changing symmetry of superconducting electrode arrangement through the form of a normal conductor 201 which is forming a superconducting weak link. In addition, when this superconducting device is used as a quasi-particle injection type device, a superconducting device with plural superconducting electrodes that can be used for a gate electrode, drain electrode or control electrode can be realized. Further, a superconducting device equipped with new functions (e.g.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: August 15, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Saitoh, Toshikazu Nishino, Mutsuko Hatano