Abstract: Disclosed is an annealing system integrated with laser and microwave. The annealing system is provided with a microwave system, a laser system, and a measurement and control system. The microwave system provides a microwave energy to a first area of a to-be-annealed object for annealing the first area of the to-be-annealed object. The laser system uses a laser to provide a laser energy to a second area of the to-be-annealed object for annealing the second area of the to-be-annealed object. The measurement and control system monitors and controls a power of a microwave and/or a laser. The annealing system is capable of reducing a time required for an overall annealing, and also capable of avoiding cracks or defects caused by large stress differences.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: Superconducting tunnel junctions for use in, for instance, quantum processors. In one example, a quantum processor can have at least one qubit structure. The at least one qubit structure includes a first aluminum layer, a second aluminum layer, and a crystalline dielectric layer disposed between the first aluminum layer and the second aluminum layer. The crystalline dielectric layer includes a spinel crystal structure.

Abstract: A true random number generator (TRNG) device having a magnetic tunnel junction (MTJ) structure coupled to a domain wall wire. The MTJ structure is formed of a free layer (FL) and a reference layer (RL) that sandwiches a tunnel barrier layer. The free layer has anisotropy energy sufficiently low to provide stochastic fluctuation in the orientation of the magnetic state of the free layer via thermal energy. The domain wall wire is coupled to the MTJ structure. The domain wall wire has a domain wall. Movement of the domain wall tunes a probability distribution of the fluctuation in the orientation of the magnetic state of the free layer. The domain wall can be moved by application of a suitable current through the wire to tune the probability distribution of 1's and 0's generated by a readout circuit of the TRNG device.

Abstract: A physical vapor deposition system includes a chamber, three target supports to targets, a movable shield positioned having an opening therethrough, a workpiece support to hold a workpiece in the chamber, a gas supply to deliver nitrogen gas and an inert gas to the chamber, a power source, and a controller. The controller is configured to move the shield to position the opening adjacent each target in turn, and at each target cause the power source to apply power sufficient to ignite a plasma in the chamber to cause deposition of a buffer layer, a device layer of a first material that is a metal nitride suitable for use as a superconductor at temperatures above 8° K on the buffer layer, and a capping layer, respectively.

Abstract: An integrated qubit readout circuit is presented, which includes a superconducting parametric amplifier, a circuit board arranged to mount the superconducting parametric amplifier, a circulator mounted on the circuit board and connected to the superconducting parametric amplifier, wherein the circulator comprises a termination port electrically connected to a termination resistor arranged to terminate a pump tone received by the superconducting parametric amplifier, and wherein the termination resistor is mounted on the circuit board.

Abstract: A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmetic logic unit and register file with an ultrafast asynchronous wave-pipelined datapath is also provided. The superconducting circuits may comprise inductive elements fabricated using both a high-inductance layer and a low-inductance layer. The memory cells may comprise superconducting tunnel junctions that incorporate magnetic layers. Alternatively, the memory cells may comprise superconducting spin transfer magnetic devices (such as orthogonal spin transfer and spin-Hall effect devices). Together, these technologies may enable the production of an advanced superconducting computer that operates at clock speeds up to 100 GHz.

Abstract: A qubit device for use in a quantum computing environment includes a semiconductor substrate, an insulating layer disposed on at least a portion of an upper surface of the substrate, and a transition metal silicide (TMSi) heterojunction disposed on at least a portion of an upper surface of the insulating layer. The TMSi heterojunction includes a link layer and at least first and second TMSi regions coupled with the link layer. The link layer may include a normal conductor, thereby forming a superconductor-normal conductor-superconductor (SNS) junction, or a geometric constriction, thereby forming a superconductor-geometric constriction-superconductor (ScS) junction. The link layer may form at least a portion of a channel including intrinsic or doped silicon.

Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

Abstract: Techniques for modifying the Josephson potential of a transmon qubit by shunting the transmon with an inductance are described. The inclusion of this inductance may increase the confined potential of the qubit system compared with the conventional transmon, which may lead to a transmon qubit that is stable at much higher drive energies. The inductive shunt may serve the purpose of blocking some or all phase-slips between the electrodes of the qubit. As a result, the inductively shunted transmon may offer an advantage over conventional devices when used for applications involving high energy drives, whilst offering few to no drawbacks in comparison to conventional devices when used at lower drive energies.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: A technique relates to a superconducting chip. Resonant units each include a Josephson junction. The resonant units have resonant frequencies whose differences are based on a variation in the Josephson junction. A transmission medium is coupled to the resonant units, and the transmission medium is configured to output a sequence of the resonant frequencies as an identification of the chip.

Abstract: A technique relates to a superconducting chip. Resonant units each include a Josephson junction. The resonant units have resonant frequencies whose differences are based on a variation in the Josephson junction. A transmission medium is coupled to the resonant units, and the transmission medium is configured to output a sequence of the resonant frequencies as an identification of the chip.

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.

Abstract: In a general aspect, a microwave quantum circuit includes an on-chip impedance matching circuit. In some cases, a microwave quantum circuit includes a dielectric substrate, a quantum circuit device on the substrate, and an impedance matching circuit device on the substrate. The quantum circuit device includes a Josephson junction, and the impedance matching circuit device is coupled to the quantum circuit device on the substrate.

Abstract: Apparatus and methods for resetting a qubit. In one aspect, an apparatus includes a qubit, wherein the qubit operates over a qubit frequency spectrum with a first flux-insensitive point and a second flux-insensitive point. The apparatus further includes a readout resonator, wherein the readout resonator operates at a readout resonator frequency in-between the first flux insensitive point and the second flux-insensitive point. The apparatus further includes a frequency controller that is configured to control the frequency of the qubit such that during a reset operation the frequency of the qubit is adjusted relative to the readout resonator frequency and the qubit is reset.

Abstract: Apparatus and methods for resetting a qubit. In one aspect, an apparatus includes a qubit, wherein the qubit operates over a qubit frequency spectrum with a first flux-insensitive point and a second flux-insensitive point. The apparatus further includes a readout resonator, wherein the readout resonator operates at a readout resonator frequency in-between the first flux insensitive point and the second flux-insensitive point. The apparatus further includes a frequency controller that is configured to control the frequency of the qubit such that during a reset operation the frequency of the qubit is adjusted relative to the readout resonator frequency and the qubit is reset.

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures.

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: An electronic measuring device is described that can include first and second input inductors connected in series. A shunt inductor is connected in parallel with the second input inductor. Optionally, an additional shunt inductor may also be used in parallel with the first input inductor. The first and second input inductors are inductively coupled to first and second SQUIDs which are in turn inductively coupled to first and second feedback inductors. First and second SQUID controllers are connected, respectively, to the first and second SQUIDs as well as the first and second feedback inductors. The first and second SQUID controllers are also connected to a processor. The processor is operable to process the output of the first and second SQUID controllers to detect unlocking events in the output of the first SQUID controller.

Abstract: A system and methods for controlling superconducting quantum circuits are provided. The system includes at least one superconducting quantum circuit described by multiple quantum states, and at least one single flux quantum (“SFQ”) control circuit configured to generate a voltage pulse sequence that includes a plurality of voltage pulses temporally separated by a pulse-to-pulse spacing timed to a resonance period. The system also includes at least one coupling between the at least one superconducting quantum circuit and the at least one SFQ control circuit configured to transmit the voltage pulse sequence generated using the SFQ control circuit to the at least one superconducting quantum circuit. In some aspects, the system further includes a controller system configured to optimize the pulse-to-pulse spacing to minimize a gate infidelity due to at least one of a timing error, a timing jitter and a weak qubit anharmonicity.

Abstract: In some implementations of the invention, existing high temperature superconducting materials (“HTS materials”) may be modified and/or new HTS materials may be created by enhancing (in the case of existing HTS materials) and/or creating (in the case of new HTS materials) an aperture within the HTS material such that the aperture is maintained at increased temperatures so as not to impede propagation of electrical charge there through. In some implementations of the invention, as long as the propagation of electrical charge through the aperture remains unimpeded, the material should remain in a superconducting state; otherwise, as the propagation of electrical charge through the aperture becomes impeded, the HTS material begins to transition into a non-superconducting state.

Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.

Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.

Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.

Abstract: A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.

Abstract: In one aspect, the present invention relates to a method of forming a reworkable, thermally conductive and electrically resistive material as a bonding structure in a module and application of the same. In certain embodiments, a homogeneous solution is prepared with an anisotropic structure, such as single-wall carbon nanotubes (SWCNTs), and an epoxy resin. The homogeneous solution is applied between a carrier and a chip of the module, and cured at a curing temperature for a curing time period to form a reworkable epoxy bonding layer, which has an anisotropic structure loading factor of about 0.1%-1.0% such that the reworkable epoxy bonding layer is thermally conductive and electrically resistive. When the chip is identified as a faulty chip, the module may be heated at a debonding temperature for a debonding time period such that the reworkable epoxy bonding layer debonds, and the chip becomes detachable from the carrier.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.

Abstract: Terahertz radiation source and method of producing terahertz radiation, said source comprising a junction stack, said junction stack comprising a crystalline material comprising a plurality of self-synchronized intrinsic Josephson junctions; an electrically conductive material in contact with two opposing sides of said crystalline material; and a substrate layer disposed upon at least a portion of both the crystalline material and the electrically-conductive material, wherein the crystalline material has a c-axis which is parallel to the substrate layer, and wherein the source emits at least 1 mW of power.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: The invention relates to a superconducting element joint comprising a joint between two superconducting elements comprising at least one direct SC-SC transition joint. By the invention an improved superconducting element joint may be obtained. The invention also relates to a process for providing such superconducting element joint and a superconducting cable system comprising such superconducting element joint.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: An electrode unit joining structure for a superconducting wire includes: a superconducting wire comprising a first base member, a first superconducting layer provided on the first base member, and a first electroconductive layer provided on the first superconducting layer; an electrode provided on the first electroconductive layer at an end portion of the superconducting wire; and a superconducting cover tape comprising a second base member, a second superconducting layer provided on the second base member, and a second electroconductive layer provided on the second superconducting layer, the superconducting cover tape being provided so as to cover at least part of the electrode, wherein the second electroconductive layer of the superconducting cover tape is disposed on the electrode side, and the electrode, the superconducting wire, and the superconducting cover tape are electrically connected to each other.

Abstract: A reciprocal quantum logic (RQL) latch system is provided. The latch system comprises an output portion that retains a state of the latch system, and a bi-stable loop that comprises a set input, a reset input and an output coupled to the output portion. A positive single flux quantum (SFQ) pulse on the set input when the latch system is in a reset state results in providing a SFQ current in the output portion representative of the latch system being in a set state.

Abstract: The invention relates to a superconducting element joint comprising a joint between two superconducting elements comprising at least one direct SC-SC transition joint. By the invention an improved superconducting element joint may be obtained. The invention also relates to a process for providing such superconducting element joint and a superconducting cable system comprising such superconducting element joint.

Abstract: Method of making a low resistivity electrical connection between an electrical conductor and an iron pnictide superconductor involves connecting the electrical conductor and superconductor using a tin or tin-based material therebetween, such as using a tin or tin-based solder. The superconductor can be based on doped AFe2As2, where A can be Ca, Sr, Ba, Eu or combinations thereof for purposes of illustration only.

Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.