Josephson Junction, Per Se (e.g., Point Contact, Bridge, Barrier Junction, Sis, Sns, Sss, Etc.) Or Josephson Junction With Only Terminals Or Connect Patents (Class 505/190)
  • Publication number: 20030207766
    Abstract: A superconducting quantum-bit device based on Josephson junction has a charge as a first principal degree of freedom assigned to writing and a phase as a second principal degree of freedom assigned to reading. The device comprises a Cooper-pair box comprising first and second Josephson junctions defining a charge island of the Cooper-pair box closing up onto a superconducting loop. A read circuit comprises a read Josephson junction JL inserted into the superconducting loop and having a Josephson energy Ej at least 50 times greater than the Josephson energy of each of the first and second Josephson junctions.
    Type: Application
    Filed: September 16, 2002
    Publication date: November 6, 2003
    Inventors: Daniel Esteve, Denis Vion, Michel Devoret, Cristian Urbina, Philippe Joyez, Hughes Pothier, Pierre-Francois Orfila, Abdelhahim Aassime, Audrey Cottet
  • Patent number: 6635368
    Abstract: A film-based HTS device comprises a substrate and a superconducting film. A peripheral portion of the film is a-axis-aligned material which is so situated on the substrate as to describe a-b planar barriers which are perpendicular to the substrate and which in parallel fashion border upon the entire periphery of the film. The a-b planar barriers serve to block vortices which nucleate at the film's periphery, thereby attenuating the overall vortex activity associated with the film, thereby attenuating the ELF and white noise which are normally prevalent in superconductor devices. Effectiveness in terms of arresting vortex motion may be increased by providing an interior film portion which is also a-axis-aligned material. It may be preferable to provide an interior film portion which is c-axis-aligned material, since this is easier to make and the a-axis-aligned peripheral portion of the film will be sufficiently effective in terms of “pinning” the vortices.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: October 21, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Yehoshua Dan Agassi
  • Patent number: 6605822
    Abstract: A method for performing a quantum computing entanglement operation between a phase qubit and a charge qubit. A coherent connection between the phase qubit and the charge qubit is provided. The coherent connection allows the quantum state of the phase qubit and the quantum state of the charge qubit to interact with each other. The coherent connection is modulated for a duration te. The phase qubit is connected to the charge qubit during at least a portion of the duration te in order to controllably entangle the quantum state of the phase qubit and the quantum state of the charge qubit.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: August 12, 2003
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexandre Blais, Jeremy P. Hilton
  • Patent number: 6563311
    Abstract: A solid-state quantum computing structure includes a d-wave superconductor in sets of islands that clean Josephson junctions separate from a first superconducting bank. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states. A second bank, which a Josephson junction separates from the first bank, can be coupled to the islands through single electron transistors for selectably initializing one or more of the supercurrents in a different quantum state. Single electron transistors can also be used between the islands to control entanglements while the quantum states evolve.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 13, 2003
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 6563310
    Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 13, 2003
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 6495854
    Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, Chang C. Tsuei
  • Patent number: 6459097
    Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: October 1, 2002
    Assignee: D-Wave Systems Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 6372368
    Abstract: An oxide superconducting element is formed on a substrate 10 by a layered structure 30 formed of oxide superconducting thin-film and a non-superconducting thin-film layers. The element is a superconducting regular current interval voltage step element. The current-voltage characteristic curve in a magnetic field has a voltage step being generated at regular bias current intervals. The layered structure 30 is formed by depositing alternately M′Ba2Cu3O7 (M′ is one or a combination of more than two elements of Nd, Sm and Eu) and M″Ba2Cu3O7 thin-films (M″ is either Pr or Sc, or a combination of the two elements).
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: April 16, 2002
    Assignee: International Superconductivity Technology Center
    Inventors: Gustavo Adolfo Alvarez, Youichi Enomoto
  • Patent number: 6353234
    Abstract: The invention concerns a layered arrangement comprising at least one layer based on a high-temperature superconductive material with at least one unit cell having a CuO2 plane, the layer being connected to a non-supeconductive layer. A modified interface layer is provided between the two layers. Alternatively, at least one of the contacting layers can be modified in the interface region. Modification can be brought about by doping with metallic ions or implantation.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: March 5, 2002
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Mikhail Faley, Ulrich Poppe, Chunlin Jia
  • Patent number: 6348699
    Abstract: A superconductive device is disclosed, which has specific characteristics of a generator and/or detector of sub-millimeter wave length radiation, comprising a two-dimensional lateral array of mesas (column-shaped elements) each containing vertically stacked Josephson junctions on top of one another. This device is capable of covering the entire frequency range between the microwave and far infrared spectral regions, in plurality of applications, where radiation emission and detection is involved. According to its various embodiments, thin columns (stacks) of Josephson junctions are monolithically built between superconducting electrical top and bottom contact layers. Mutually isolated segments cut out of the contact layers allow for optimization of circuit parameters such as impedance matching to load and maximizing the output power. External electronic control allows modulation of the radiation field and other operation modes of the device.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: February 19, 2002
    Assignee: Oxxel Oxide Electronics Technology GmbH
    Inventor: Alfred Zehe
  • Patent number: 6324413
    Abstract: A lanthanum aluminate (LaAlO3) substrate on which thin films of layered perovskite copper oxide superconductors are formed. Lanthanum aluminate, with a pseudo-cubic perovskite crystal structure, has a crystal structure and lattice constant that closely match the crystal structures and lattice constants of the layered perovskite superconductors. Therefore, it promotes epitaxial film growth of the superconductors, with the crystals being oriented in the proper direction for good superconductive electrical properties, such as a high critical current density. In addition, LaAlO3 has good high frequency properties, such as a low loss tangent and low dielectric constant at superconductive temperatures. Finally, lanthanum aluminate does not significantly interact with the superconductors. Lanthanum aluminate can also used to form thin insulating films between the superconductor layers, which allows for the fabrication of a wide variety of superconductor circuit elements.
    Type: Grant
    Filed: December 9, 1991
    Date of Patent: November 27, 2001
    Assignee: TRW Inc.
    Inventors: Randy Wayne Simon, Christine Elizabeth Platt, Alfred Euinam Lee, Gregory Steven Lee
  • Patent number: 6320369
    Abstract: A superconducting current measuring circuit is provided with a detection loop through which a current flows by the influence of a magnetic field generated by a measurement target current. The detection loop contains a superconductor. The superconducting current measuring circuit is also provided with a superconducting sampler circuit for measuring the current flowing through the detection loop.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Mutsuo Hidaka, Shuichi Tahara
  • Patent number: 6275716
    Abstract: Compounds of the of the general formula La3−zMezBa3Ca1−vNcvCu7O16+x, wherein Me can be a rare earth metal or an alkaline metal ion selected from the group consisting of yttrium (Y), ytterbium (Yb), sodium (Na) and Nc can be a 2+ ion selected from the group consisting of magnesium (Mg) and cadmium (Cd) have been prepared as the HTSC in thin film superconductors. These compounds can be used as thin film high critical superconductors in thin film high critical temperature superconducting structures and antennas and in multilayered structures and devices such as Josephson junctions, broadband impedance transformers and both flux flow and field effect transistors TABLE 1 Properties of La3-zMezBa3Ca1-vCu7O16+x Compounds. Lattice Parameter (Å) Onset Compound c &agr; Tc (K.) La3Ba3CaCu7O16+x 11.650 3.865 72  11.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: August 14, 2001
    Inventors: Arthur Tauber, Steven C. Tidrow
  • Patent number: 6191073
    Abstract: The invention relates to a series of layers containing at least one layer on the basis of REBa2CU3O7-Z or with a comparable crystallographic structure, wherein said layer is connected to a non-superconductive layer. The only material chosen for the non-superconductive layer is material containing atomic components which are chemically compatible with the superconductive material of the high temperature superconductive layer. Such a series of layers enables a multilayer system or also a cryogenic component, e.g. a Josephson contact, to be formed.
    Type: Grant
    Filed: February 27, 1999
    Date of Patent: February 20, 2001
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Ricardo Hojczyk, Ulrich Poppe, Chunlin Jia
  • Patent number: 6188919
    Abstract: A SNS Josephson junction (10) is provided for use in a superconducting integrated circuit. The SNS junction (10) includes a first high temperature superconducting (HTS) layer (14) deposited and patterned on a substrate (18), such that the first HTS layer (14) is selectively removed to expose a top surface of the substrate (18) as well as to form an angular side surface (22) on the first HTS layer (14) adjacent to the exposed top surface of the substrate (18). Ion implantation is used to form a junction region (12) having non-superconducting properties along the angular side surface (22) of the first HTS layer (14). A second HTS layer (16) is then deposited and patterned over at least a portion of the first HTS layer (14) and the exposed top surface of the substrate (18), thereby forming a SNS Josephson junction.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: February 13, 2001
    Assignee: TRW Inc.
    Inventors: John R. LaGraff, James M. Murduck, Hugo W-K. Chan
  • Patent number: 6157044
    Abstract: A tunnel junction type Josephson device includes a pair of superconductor layers formed of a compound oxide superconductor material and an insulator layer formed between the pair of superconductor layers. The insulator layer is formed of a compound oxide which is composed of the same constituent elements as those of the compound oxide superconductor material of the superconductor layers but with an atomic ratio which does not present a superconductivity characteristics. In addition, the superconductor layers and the insulator layer are continuously formed while supplying oxygen.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: December 5, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hidenori Nakanishi, Saburo Tanaka, Hideo Itozaki, Shuji Yazu
  • Patent number: 6069369
    Abstract: Superconducting device include a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: May 30, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Ushio Kawabe, Yoshinobu Tarutani, Shinya Kominami, Toshiyuki Aida, Tokuumi Fukazawa, Mutsuko Hatano
  • Patent number: 6066600
    Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: May 23, 2000
    Assignee: TRW Inc.
    Inventor: Hugo W. Chan
  • Patent number: 6023072
    Abstract: A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: February 8, 2000
    Assignee: TRW Inc.
    Inventor: Arnold H. Silver
  • Patent number: 6016433
    Abstract: Any oxide superconductor Josephson junction element having an oxide superconductor oriented in the c-axis direction with respect to a substrate, and a needle-like, a-axis (or b-axis) oriented oxide superconductor. Both sides of the needle-like, a-axis (or b-axis) oriented oxide superconductor are sandwiched between the c-axis oriented superconductors. The crystal boundary sections between the needle-like, a-axis (or b-axis) oriented oxide superconductor and each of the c-axis oriented superconductors form a weak link of the Josephson junction. The needle-like, a-axis (or b-axis) oriented oxide superconductor is grown such that the c-axis direction thereof is oriented in the (110) direction which is inclined at an angle of 45 degrees with respect to the (100) direction or (010) direction of the c-axis oriented superconductors.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: January 18, 2000
    Assignees: International Superconductivity Technology Center, Sharp Kabushiki Kaisha
    Inventors: Yuuji Mizuno, Yoshihiro Ishimaru, Youichi Enomoto
  • Patent number: 6011981
    Abstract: An oxide superconducting multilayered thin film structure having a laminated layer structure of oxide superconductor thin film layers and non-superconductor thin film layers constituted by a combination of material groups for making strain free interfaces among both thin film layers. For example, an oxide superconductor multilayered film constituted by a laminated layer structure where thin films of an oxide superconductor represented by the chemical formula of M'Ba.sub.2 Cu.sub.3 O.sub.7-.delta. (M'; a rare earth element of Nd, Sm, Eu or the like or an alloy of these, .delta.; oxygen depletion amount) and thin films of an oxide represented by the chemical formula of M*Ba.sub.2 Cu.sub.3 O.sub.7-.delta. (M*; an element of Pr, Sc or the like or an alloy of these, .delta.; oxygen depletion amount) are alternately stacked. The oxide thin films are thin films fabricated by a pulsed laser deposition process or a sputtering process. A Josephson device can be provided by using the multilayered film.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: January 4, 2000
    Assignee: International Superconductivity Technology Center
    Inventors: Gustavo Alvarez, Furen Wang, Jian-Guo Wen, Naoki Koshizuka, Youichi Enomoto, Tadashi Utagawa, Shoji Tanaka
  • Patent number: 6004907
    Abstract: The present invention forms a superconducting junction using a cubic YBa.sub.2 Cu.sub.3 Ox thin film as a barrier layer. The present invention forms a first YBCO superconducting thin film, a SrTiO.sub.3 insulating layer thin film on the substrate, etches a side of them in the form of inclination, subsequently integrates a non-superconducting cubic YBCO barrier thin film, a second YBCO superconducting thin film, a SrTiO.sub.3 protecting layer thin film in series on the whole surface of the substrate, etches an opposite side of the etched part of the SrTiO.sub.3 insulating layer thin film in the form of inclination, fabricates a superconducting junction by forming a metal electrode to said aperture after forming apertures which expose said first YBCO superconducting thin film, the second YBCO superconducting thin film, fabricates a superconducting junction upon forming the metallic electrode to the apertures, and deposits a cubic YBa.sub.2 Cu.sub.3 Ox barrier thin film at a temperature of 600-650.degree. C.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: December 21, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong Dae Suh, Gun Yong Sung
  • Patent number: 5962866
    Abstract: A superconductor device has a substrate with an inclined surface that divides the substrate surface into a lower planar substrate surface and an upper planar substrate surface. A lower layer of an anisotropic superconductor material is epitaxially deposited on the lower planar substrate surface so that an a-axis of the anisotropic superconductor material of the lower layer is exposed at a top edge of the lower layer. An upper layer of an anisotropic superconductor material is epitaxially deposited on the upper planar substrate surface so that an a-axis of the anisotropic superconductor material of the upper layer is exposed at a top edge of the upper layer. A layer of a non-superconductor material overlies the inclined surface and the layers of anisotropic superconductor material.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: October 5, 1999
    Assignee: Biomagnetic Technologies, Inc.
    Inventors: Mark S. DiIorio, Shozo Yoshizumi, Kai-Yueh Yang
  • Patent number: 5945383
    Abstract: A method of producing a high temperature superconductor Josephson element and an improved SNS weak link barrier element is provided. A YBaCuO superconducting electrode film is deposited on a substrate at a temperature of approximately 800.degree. C. A weak link barrier layer of a nonsuperconducting film of N--YBaCuO is deposited over the electrode at a temperature range of 520.degree. C. to 540.degree. C. at a lower deposition rate. Subsequently, a superconducting counter-electrode film layer of YBaCuO is deposited over the weak link barrier layer at approximately 800.degree. C. The weak link barrier layer has a thickness of approximately 50 .ANG. and the SNS element can be constructed to provide an edge geometry junction.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: August 31, 1999
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Brian D. Hunt
  • Patent number: 5942765
    Abstract: In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7).
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: August 24, 1999
    Assignee: International Superconductivity Technology Center
    Inventors: Kazunori Miyahara, Yoichi Enomoto, Shoji Tanaka
  • Patent number: 5916848
    Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: June 29, 1999
    Assignee: TRW Inc.
    Inventor: Dale J. Durand
  • Patent number: 5916697
    Abstract: A material formed as a film comprised of monomolecular layers (2,3,4,5) stacked on a substrate (1), wherein said film includes at least one first set (R) of layers which form an electric charge reservoir, and a second set (S) of layers which form a conductive cell and which contain a number of conductive copper oxide layers (4), separated from each other by intermediate layers (5), the reservoir and the conductive cell being adjacent in the layer stack. There are at least four conductive copper oxide layers, and the intermediate layers have the chemical formula Ca.sub.1-x M.sub.x and are free of strontium, wherein x is a real number between 0 and 0.2, M is a component with an ionic radius close to that of the Ca.sup.2+ ion, and the intermediate layers may be complete or not.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: June 29, 1999
    Assignees: Michael Lagues, Jacques Lewiner, Ufinnova
    Inventor: Michel Lagues
  • Patent number: 5906963
    Abstract: A lanthanum aluminate (LaAlO.sub.3) substrate on which thin films of layered perovskite copper oxide superconductors are formed. Lanthanum aluminate, with a pseudo-cubic perovskite crystal structure, has a crystal structure and lattice constant that closely match the crystal structures and lattice constants of the layered perovskite superconductors. Therefore, it promotes epitaxial film growth of the superconductors, with the crystals being oriented in the proper direction for good superconductive electrical properties, such as a high critical current density. In addition, LaAlO.sub.3 has good high frequency properties, such as a low loss tangent and low dielectric constant at superconductive temperatures. Finally, lanthanum aluminate does not significantly interact with the superconductors. Lanthanum aluminate can also used to form thin insulating films between the superconductor layers, which allows for the fabrication of a wide variety of superconductor circuit elements.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: May 25, 1999
    Assignee: TRW Inc.
    Inventors: Randy Wayne Simon, Christine Elizabeth Platt, Alfred Euinam Lee, Gregory Steven Lee
  • Patent number: 5892243
    Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c, superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c, superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c, superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ionmilling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: April 6, 1999
    Assignee: TRW Inc.
    Inventor: Hugo W. Chan
  • Patent number: 5891828
    Abstract: PrBa.sub.2 Cu.sub.3 O.sub.Y exhibiting superconductivity is provided by a method including the steps of preparing a solvent consisting of a mixture of praseodymium oxide, at least one of barium oxide and barium carbonate, and copper oxide at a mixing ratio of between 1:3:5 and 1:8:20, disposing the solvent between a feed rod of PrBa.sub.2 Cu.sub.3 O.sub.7 formed to a high density and a seed crystal, heating the solvent to a temperature of 880.degree.-980.degree. C. in an atmosphere of an inert gas of at least one of argon and nitrogen mixed with 0.01-2% oxygen to form a floating solvent zone, moving the floating solvent zone toward the feed rod at 0.1-1.0 mm/hr under a temperature gradient at the solid-liquid interface of 25.degree.-35.degree. C./mm to precipitate single crystal on the seed crystal, and heat-treating the single crystal obtained in an atmosphere containing not less than 15% oxygen. Another aspect of the invention provides a superconducting device including the superconducting PrBa.sub.2 Cu.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: April 6, 1999
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Kunihiko Oka, Zhigang Zou, Toshimitsu Ito, Hiroshi Akoh
  • Patent number: 5889289
    Abstract: High temperature superconductor composite thin film devices with easily moved Josephson vortices are described having high T.sub.c and good magnetic vortex properties. A preferred composite material was YBCO/CeO.sub.2 thin film on a MgO substrate. The superconductor composites were preferably formed by off-axis co-sputtering. A surprising recovery in properties was seen after plasma etching with oxygen.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: March 30, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Edward J. Cukauskas, Laura H. Allen
  • Patent number: 5885937
    Abstract: This invention provides a superconducting tunnel junction element showing satisfactory Josephson effect. The element includes a Bi-based layered compound such as Bi.sub.2 Sr.sub.2 (Ca.sub.0.6 Y.sub.0.4)Cu.sub.2 O.sub.8, Bi.sub.2 Sr.sub.2 Cu.sub.2 O.sub.6 and Bi.sub.2 Sr.sub.2 CaCu.sub.2 O.sub.8 as the barrier layer between the superconducting oxide electrodes. The structural matching of the superconducting oxide with the Bi-based compound is supposed to be good. Some kinds of Cu-based superconducting oxides such as YSr.sub.2 Cu.sub.2.7 Re.sub.0.3 O.sub.7, Sr.sub.2 CaCu.sub.2 O.sub.6 and (La.sub.0.9 Sr.sub.0.1).sub.2 CuO.sub.4 are used for the electrodes to obtain a Josephson element which can work at a high temperature. When using the superconducting oxides including Ba such as YBa.sub.2 Cu.sub.3 O.sub.7 for the electrode, forming a thin film between the electrode and the barrier is better to prevent Ba from reacting with Bi in the barrier layer.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: March 23, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Adachi, Masahiro Sakai, Akihiro Odagawa, Kentaro Setsune
  • Patent number: 5883051
    Abstract: A superconducting Josephson junction element including a first, a-axis oriented, superconductive metal oxide crystal grain having a first area of a {001} plane, and a second, c-axis oriented, superconductive metal oxide crystal grain having a second area of a {110} plane, wherein the first and second crystal grains are in contact with each other at the first and second areas to form a grain boundary therebetween.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: March 16, 1999
    Assignee: International Superconductivity Technology Center
    Inventors: Yoshihiro Ishimaru, Jian-Guo Wen, Kunihiko Hayashi, Youichi Enomoto, Naoki Koshizuka, Shoji Tanaka
  • Patent number: 5880069
    Abstract: A desired pattern is formed on a non-superconducting oxide film after the non-superconducting oxide film has been formed on a magnesia substrate. A superconducting oxide film is formed over the exposed parts of the substrate and the non-superconducting oxide film. The epitaxial orientation of the superconducting oxide film section on the non-superconducting oxide film is different from that of the superconducting oxide film section on the substrate. A tilt-boundary junction is produced at a boundary between the superconducting film sections which are different in epitaxial orientation from each other. Thus, a Josephson junction having a desired pattern can be obtained.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: March 9, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nakao, Hiroaki Furukawa, Ryohkan Yuasa, Shuji Fujiwara
  • Patent number: 5877122
    Abstract: An oxide superconductor element, produced by forming a damaged region on a substrate surface by the Ga.sup.+ focusing ion beam method and then depositing an oxide superconductor thin-film over it, is characterized in that a NdBa.sub.2 Cu.sub.3 O.sub.7-y (0.ltoreq.y.ltoreq.0.5) oxide superconductor is used in a tunnel junction having a tunneling barrier region with weak superconductivity.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: March 2, 1999
    Assignees: Fujitsu Ltd., Sharp Kabushiki Kaisha, NEC Corp., International Superconductivity Technology Center
    Inventors: Yoshihiro Ishimaru, Yuuji Mizuno, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
  • Patent number: 5872368
    Abstract: The order parameter of a superconductor is reduced by injecting spin-polarized carriers into the superconductor. The reduction in the order parameter is used to modulate the critical current of the superconductor. In a typical embodiment, a current is caused to flow through a superconductor. Spin polarized electrons are then injected into the path of the current in the superconductor by biasing a magnetic metal with respect to a terminal of the superconductor. The bias current may be varied to modulate the injection and thus the flow of current through the superconductor.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: February 16, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael Osofsky, Robert J. Soulen, Jr., Raymond Auyeung, James S. Horwitz, Doug B. Chrisey, Mark Johnson
  • Patent number: 5863868
    Abstract: A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: January 26, 1999
    Assignee: TRW Inc.
    Inventors: Hugo Wai-Kung Chan, Kenneth P. Daly, James M. Murduck
  • Patent number: 5849669
    Abstract: A high critical temperature superconducting Josephson device includes a bicrystal substrate formed of a first single crystal substrate and a second single crystal substrate, with end faces of the first and second single crystal substrates having different crystal orientations and being joined to each other. A first superconducting electrode formed of a first film of a high critical temperature superconductor material is located on the first single crystal substrate, whereas a second superconducting electrode formed of a second film of a high critical temperature superconductor material is located on the second single crystal substrate. A bridge is formed of a third film of a high critical temperature superconductor material and located on the bicrystal substrate across a joint between said first and said second single crystal substrates.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: December 15, 1998
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Zhongmin Wen
  • Patent number: 5840204
    Abstract: A method for patterning an oxide superconductor thin film, comprising a step of forming a SiO.sub.2 layer on the oxide superconductor thin film, patterning the SiO.sub.2 layer so as to form the same pattern as that of the oxide superconductor thin film which will be patterned, etching the oxide superconductor thin film by using the patterned SiO.sub.2 layer as a mask, and removing the SiO.sub.2 layer by using a weak HF solution, a buffer solution including HF or a mixture including HF.
    Type: Grant
    Filed: April 5, 1995
    Date of Patent: November 24, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, So Tanaka, Michitomo Iiyama
  • Patent number: 5801393
    Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: September 1, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: 5793055
    Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: August 11, 1998
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Alexander Kastalsky
  • Patent number: 5793056
    Abstract: A technique for defining the active area of a high-T.sub.c superconductor Josephson junction uses an epitaxial slotted insulator patterned over the edge of the superconductor thin film-insulator bilayer. The superconductor/normal-metal/superconductor edge junction formed between the slotted insulator has a small active area. The counter electrode provided as an interconnect of the junction can therefore be wider than the active area of the edge junction since it can overlap onto the patterned slotted insulator. The use of the slotted insulator enables fabrication of junctions having resistances and critical currents in the desired range for high-T.sub.c superconductor circuits while enabling the use of wide, low inductance interconnects.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: August 11, 1998
    Assignee: Northrop Grumman Corporation
    Inventors: Martin G. Forrester, Brian D. Hunt
  • Patent number: 5776863
    Abstract: A method of in-situ fabrication of a Josephson junction having a laminar structure, the method comprising the steps of: (1) etching a planar substrate to yield a first planar segment, a second planar segment and a ramp segment, the ramp segment connecting the two planar segments at an angle thereto and the substrate having a constantly-decreasing thickness in the ramp segment; (2) depositing a first superconductive layer on the substrate; (3) depositing a non-superconductive layer on the first superconductive layer; and (4) depositing a second superconductive layer on the non-superconductive layer, wherein both the first and second superconductive layers, and the non-superconductive layer are epitaxial with a c-axis in a direction substantially normal to the plane of the first and second planar segments, and the layers are of substantially uniform thickness in the three segments.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: July 7, 1998
    Assignee: TRW Inc.
    Inventor: Arnold H. Silver
  • Patent number: 5750474
    Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: May 12, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: 5736488
    Abstract: This invention relates to multilayered superconductive composites, particularly to composites based on thallium-containing superconducting oxides, and their process of manufacture.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: April 7, 1998
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Dean Willett Face, Kirsten Elizabeth Myers
  • Patent number: 5728481
    Abstract: A magnetic detecting device is constructed of a substrate, a first magnetic layer formed on the substrate, a first magnetic layer formed on the substrate, an intermediate layer containing an atom indicative of weak spincoupling and formed on the first magnetic film, and a second magnetic layer formed on the intermediate layer. The magnetic detecting device further comprises a unit or supplying a current through the first and second magnetic layers, and a unit for detecting a voltage generated between the first magnetic layer and the second magnetic layer while the current is supplied thereto.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 17, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kasai, Yuzo Kozono, Yoko Kanke, Toshiyuki Ohno, Masanobu Hanazono
  • Patent number: 5721195
    Abstract: The planar superconducting resonator includes a substrate (1), a symmetrically shaped stripline (2) applied to the substrate (1) in which two orthogonal electromagnetic modes are excitable and including a symmetry perturbation for coupling the two orthogonal electromagnetic modes, an additional stripline (5) arranged on the substrate in the vicinity of the symmetry perturbation, a Josephson junction (3) arranged between the symmetry perturbation and the additional stripline (5) and a device for generating and controlling a magnetic field at the Josephson junction (3) so that the degree of coupling between the two orthogonal electromagnetic modes is varied. The Josephson junction (3) is formed by a non-superconducting layer (4) arranged between the symmetry perturbation and the additional stripline (5).
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: February 24, 1998
    Assignee: Robert Bosch GmbH
    Inventors: Wolfgang Grothe, Klaus Voigtlaender, Matthias Klauda, Claus Schmidt
  • Patent number: 5721196
    Abstract: A Josephson junction device comprises a single crystalline substrate including a principal surface, an oxide layer formed on the principal surface of the substrate having a step on its surface and an oxide superconductor thin film formed on the surface of the oxide layer. The oxide superconductor thin film includes a first and a second portions respectively positioned above and below the step of the oxide layer, which are constituted of single crystals of the oxide superconductor, and a step-edge junction made up of a grain boundary on the step of the oxide layer, which constitutes a weak link of the Josephson junction.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: February 24, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: RE37587
    Abstract: A SQUID includes a substrate and a superconducting current path of a patterned oxide superconductor material thin film formed on a surface of the substrate. A c-axis of an oxide crystal of the oxide superconductor material thin film is oriented in parallel to the surface of the substrate.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: March 19, 2002
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takashi Matsuura, Saburo Tanaka, Hideo Itozaki
  • Patent number: H2066
    Abstract: Films having islands of noble metal protruding from and surrounded by a layer of a superconductor are formed by depositing a layer a noble metal on a substrate, and depositing a superconducting layer at a temperature that converts the noble metal film into puddles. The resulting film is useful as a two-dimensional array of superconductor-normal metal-superconductor Josephson junctions.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: June 3, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Edward J. Cukauskas, Laura H. Allen, Michael A. Fisher