Semiconductor Device Or Thin Film Electric Solid-state Device Manufacture Patents (Class 505/330)
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Patent number: 9082530Abstract: A superconducting thin film material exhibiting excellent superconducting properties and a method of manufacturing the same are provided. A superconducting thin film material includes a substrate, and a superconducting film formed on the substrate. The superconducting film includes an MOD layer formed by an MOD process, and a gas-phase-formed layer formed on the MOD layer by a gas-phase process. Since the MOD layer is formed first and then the gas-phase-formed layer is formed in this manner, degradation of the properties of the gas-phase-formed layer due to heat treatment in the step of forming the MOD layer (heat treatment in the MOD process) can be prevented.Type: GrantFiled: May 9, 2012Date of Patent: July 14, 2015Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kei Hanafusa, Genki Honda, Kotaro Ohki, Tsuyoshi Nakanishi, Takahiro Taneda, Tatsuoki Nagaishi
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Patent number: 9053968Abstract: A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.Type: GrantFiled: October 18, 2012Date of Patent: June 9, 2015Assignee: ChipMOS Technologies Inc.Inventor: Shih-Wen Chou
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Publication number: 20140274725Abstract: A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David W. Abraham, George A. Keefe, Christian Lavoie, Mary E. Rothwell
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Publication number: 20140094372Abstract: Compactly-integrated electronic structures and associated systems and methods are provided. Certain embodiments relate to the ability to integrate nanowire-based detectors with optical components.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicants: Massachusetts Institute of Technology, The Trustees of Columbia University in the City of New YorkInventors: The Trustees of Columbia University in the City of New York, Massachusetts Institute of Technology
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Publication number: 20140087952Abstract: A superconducting nanowire single photon detector (SN-SPD) microelectronic circuit is described which has higher quantum efficiency and signal-to-noise than any SN-SPD's known in the art. The material and configuration of the microelectronic circuit eliminates the polarization dependence and shows improved signal-to-noise over SN-SPD microelectronic circuits known in the art. The higher efficiency, polarization independence, and high signal-to-noise is achieved by vertically stacking two tungsten-silicide (TS) SN-SPDs and electrically connecting them in parallel. This structure forms a multilayer superconducting nanowire avalanche photo-detector (SNAP). A single photon detection device employing the multilayer (SNAP) microelectronic circuit demonstrates a peak system detection efficiency of 87.7% and a polarization dependence of less than 2%. This represents nearly an order of magnitude improvement in both system detection efficiency and reduction of polarization dependence compared to conventional SNSPDs.Type: ApplicationFiled: April 24, 2013Publication date: March 27, 2014Applicant: The United States of America as represented by the Secretary of CommerceInventors: Sae Woo Nam, Burm Baek
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Patent number: 8412292Abstract: Intermodulation distortion (IMD) is known to be an impediment to progress in superconductor-based filter technology. The present invention's methodology for reducing IMD can open doors to heretofore unseen practical applications involving high temperature superconductor (HTS) filters. Typical inventive practice includes (a) increasing the thickness d, and/or (b) changing the operation temperature T, of the filter's HTS film. The film's thickness d is increased in such a way as to decrease the IMD power PIMD in accordance with the material-independent proportionate relationship PIMD?1/d1.5-6. The film's operation temperature T is bettered or optimized in accordance with the material-independent proportionate relationship PIMD?(?O(T))10(K(2)(T))2/(?O(T))6, and further in accordance with three individual material-dependent relationships, namely, between operation temperature T and each of linear penetration depth ?O, gap maximum ?O, and kernel K(2).Type: GrantFiled: July 16, 2010Date of Patent: April 2, 2013Assignee: The United States of America as represented by the Secretary of the NavyInventors: Yehoshua Dan Agassi, Daniel E. Oates
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Patent number: 8274098Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.Type: GrantFiled: December 27, 2007Date of Patent: September 25, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-jong Chung, Ran-ju Jung, Sun-ae Seo, Dong-chul Kim, Chang-won Lee
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Patent number: 8193122Abstract: A seed crystal for the fabrication of a superconductor is grown from a rare-earth oxide having the basic formula XwZtBaxCuyOz, X comprising at least one rare-earth element and Z being a dopant which raises the peritectic decomposition temperature (Tp) of the oxide. In a preferred embodiment, the dopant is Mg. Use of this rare-earth oxide material for seed crystals increases the temperature at which cold-seeding can be performed and thus enables the growth of a wider range of bulk superconductor materials by this process.Type: GrantFiled: June 30, 2011Date of Patent: June 5, 2012Assignee: The Boeing CompanyInventors: David Anthony Cardwell, Nadendla Hari Babu, Yun-Hua Shi
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Publication number: 20120077680Abstract: Systems, articles, and methods are provided related to nanowire-based detectors, which can be used for light detection in, for example, single-photon detectors. In one aspect, a variety of detectors are provided, for example one including an electrically superconductive nanowire or nanowires constructed and arranged to interact with photons to produce a detectable signal. In another aspect, fabrication methods are provided, including techniques to precisely reproduce patterns in subsequently formed layers of material using a relatively small number of fabrication steps. By precisely reproducing patterns in multiple material layers, one can form electrically insulating materials and electrically conductive materials in shapes such that incoming photons are redirected toward a nearby electrically superconductive materials (e.g., electrically superconductive nanowire(s)). For example, one or more resonance structures (e.g.Type: ApplicationFiled: May 27, 2011Publication date: March 29, 2012Applicant: Massachusetts Institute of TechnologyInventors: Karl K. Berggren, Xiaolong Hu, Daniele Masciarelli
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Patent number: 8119571Abstract: Novel articles and methods to fabricate same with self-assembled nanodots and/or nanorods of a single or multicomponent material within another single or multicomponent material for use in electrical, electronic, magnetic, electromagnetic and electrooptical devices is disclosed. Self-assembled nanodots and/or nanorods are ordered arrays wherein ordering occurs due to strain minimization during growth of the materials. A simple method to accomplish this when depositing in-situ films is also disclosed. Device applications of resulting materials are in areas of superconductivity, photovoltaics, ferroelectrics, magnetoresistance, high density storage, solid state lighting, non-volatile memory, photoluminescence, thermoelectrics and in quantum dot lasers.Type: GrantFiled: August 3, 2006Date of Patent: February 21, 2012Inventors: Amit Goyal, Sukill Kang
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Patent number: 7816303Abstract: A laminated superconductor wire includes a superconductor wire assembly, which includes a first superconductor insert comprising a first high temperature superconductor layer overlaying a first substrate and a second superconductor insert comprising a second high temperature superconductor layer overlaying a second substrate. The first and second superconductor inserts are joined together at their respective substrates. An electrically conductive structure substantially surrounds the superconductor wire assembly.Type: GrantFiled: July 29, 2005Date of Patent: October 19, 2010Assignee: American Superconductor CorporationInventors: Cornelis Leo Hans Thieme, Alexis P. Malozemoff, Martin W. Rupich, Urs-Detlev Schoop, Elliott D. Thompson, Darren Verebelyi
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Patent number: 7544345Abstract: A magnesium oxide single crystal having controlled crystallinity has a subboundary, and ranges of variation of diffraction line positions, as measured for reciprocal lattice maps with respect to a region surrounded by the same subboundary, with the range of the variation of 1×10?3 to 2×10?2 degree of on ?? coordinates, and with the range of the variation of 4×10?4 to 5×10?3 degree on 2? coordinates.Type: GrantFiled: December 28, 2005Date of Patent: June 9, 2009Assignee: Tateho Chemical Industries Co., Ltd.Inventors: Atsuo Toutsuka, Yoshifumi Kawaguchi, Masaaki Kunishige
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Patent number: 7510997Abstract: The present invention relates to epitaxial, electrically conducting and mechanically robust, cubic nitride buffer layers deposited epitaxially on biaxially textured substrates such as metals and alloys. The invention comprises of a biaxially textured substrate with epitaxial layers of nitrides. The invention also discloses a method to form such epitaxial layers using a high rate deposition method as well as without the use of forming gases. The invention further comprises epitaxial layers of oxides on the biaxially textured nitride layer. In some embodiments the article further comprises electromagnetic devices which may have superconducting properties.Type: GrantFiled: August 17, 2004Date of Patent: March 31, 2009Assignees: Applied Thin Films, Inc., UT-Battelle, LLCInventors: Sambasivan Sankar, Amit Goyal, Scott A. Barnett, Ilwon Kim, Donald M. Kroeger
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Publication number: 20080312088Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.Type: ApplicationFiled: December 27, 2007Publication date: December 18, 2008Inventors: Hyun-jong Chung, Ran-ju Jung, Sun-ae Seo, Dong-chul Kim, Chang-won Lee
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Publication number: 20080176752Abstract: This invention provides a laser trimming method for tuning the frequency of a spiral resonator, and for improving the characteristics of a high temperature superconductor filter comprised of high temperature superconductor spiral resonators, by tuning the individual high temperature superconductor spiral resonators. This invention also provides a method for tuning the resonance frequency of a high temperature superconductor planar coil. This invention also provides a laser ablation process for creating high temperature superconductor circuit elements.Type: ApplicationFiled: March 26, 2008Publication date: July 24, 2008Inventors: Paul J. Martin, James D. MCCAMBRIDGE
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Patent number: 7341978Abstract: An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide.Type: GrantFiled: March 4, 2005Date of Patent: March 11, 2008Assignee: LSI Logic CorporationInventors: Shiqun Gu, Wai Lo, Hong Lin
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Patent number: 7067458Abstract: A multi-layered unit according to the present invention includes a support substrate formed of fused quartz, an electrode layer formed on the support substrate, made of BSCCO (bismuth strontium calcium copper oxide) having a stoichiometric composition represented by Bi2Sr2CaCu2O8, having an anisotropic property and conductivity and enabling epitaxial growth of a dielectric material containing a bismuth layer structured compound thereon and oriented in the c axis direction, and a dielectric layer formed by epitaxially growing a dielectric material containing a bismuth layer structured compound having a composition represented by SrBi4Ti4O15 on the electrode layer.Type: GrantFiled: February 26, 2003Date of Patent: June 27, 2006Assignee: TDK CorporationInventor: Yukio Sakashita
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Patent number: 6740421Abstract: A method of preparing a biaxially textured article includes the steps of: rolling a metal preform while applying shear force thereto to form as-rolled biaxially textured substrate having an a rotated cube texture wherein a (100) cube face thereof is parallel to a surface of said substrate, and wherein a [100] direction thereof is at an angle of at least 30° relative to the rolling direction; and depositing onto the surface of the biaxially textured substrate at least one epitaxial layer of another material to form a biaxially textured article.Type: GrantFiled: July 14, 2003Date of Patent: May 25, 2004Assignee: UT-Battelle, LLCInventor: Amit Goyal
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Patent number: 6552415Abstract: An electrically stabilized thin-film high-temperature superconductor includes a superconductive layer (32) applied over a flat metallic substrate (31) and connected to the metallic substrate (31) so that electrical contact between the superconductive layer (32) and the metallic substrate (31) is distributed over the area of the metallic substrate (31).Type: GrantFiled: February 13, 2001Date of Patent: April 22, 2003Assignee: ABB Research LtdInventors: Willi Paul, Makan Chen
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Patent number: 6475958Abstract: The present invention relates to a high-temperature superconductor arrangement which is protected against hot spots. A contact-making layer 4 is provided between a superconductor layer 1 and an electrical bypass 2, which contact-making layer 4 has anisotropic electrical conductivity. This ensures a low contact resistance between the superconductor 1 and the bypass 2, without the admittance being increased in the main current flow direction 3. The said anisotropy is produced by discontinuities in the contact-making layer 4, for example by said contact-making layer 4 being broken down into areas 41 which are not connected to one another.Type: GrantFiled: November 13, 2000Date of Patent: November 5, 2002Assignee: ABB Research LtdInventors: Willi Paul, Makan Chen
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Patent number: 6391828Abstract: A superconductor structure is disclosed, comprising a composite body made of an electrically insulating substrate to which an intermediate layer is bonded, a buffer layer is deposited on the intermediate layer and a layer of a metal-oxide high Tc superconductor material is deposited on the buffer layer. The intermediate layer comprises a glass material with a coefficient of thermal expansion greater than 6×10−6 K−1. To produce the structure, at least one deposition process is selected in which the maximum temperature is at most 150 K higher than the transformation temperature of the glass material.Type: GrantFiled: May 4, 2000Date of Patent: May 21, 2002Assignee: Siemens AktiengesellschaftInventor: Rainer Nies
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Publication number: 20010027166Abstract: A cabled conductor comprises a plurality of transposed strands each comprising one or more preferably twisted filaments preferably surrounded or supported by a matrix material and comprising textured anisotropic superconducting compounds which have crystallographic grain alignment that is substantially unidirectional and independent of the rotational orientation of the strands and filaments in the cabled conductor. The cabled conductor is made by forming a plurality of suitable composite strands, forming a cabled intermediate from the strands by transposing them about the longitudinal axis of the conductor at a preselected strand lay pitch, and, texturing the strands in one or more steps including at least one step involving application of a texturing process with a primary component directed orthogonal to the widest longitudinal cross-section of the cabled intermediate, at least one such orthogonal texturing step occurring subsequent to said strand transposition step.Type: ApplicationFiled: January 25, 2001Publication date: October 4, 2001Applicant: American Superconductor Corporation Delaware CorporationInventors: Gregory L. Snitchler, Jeffrey M. Seuntjens, William L. Barnes, Gilbert N. Riley
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Patent number: 6287969Abstract: Disclosed herein is a method of forming a superconductor, comprising the steps of: providing a substrate and exposing the substrate to a first atmosphere, including precursors to form a first epitaxial layer segment. The first layer segment is then exposed to a second atmosphere, including precursors to form a second epitaxial layer segment, and the second layer segment is exposed to a third atmosphere including precursors to form a third epitaxial layer segment. Each of the first and third layer segments are each formed from a superconductor material and the second layer segment is formed from a material different from the first and third layer segments and the first, second and third layer segments have a collective thickness, the third layer segment having an outer surface with a roughness which is less than that of a single layer of the superconductor material with a thickness equal to the collective thickness.Type: GrantFiled: May 6, 1999Date of Patent: September 11, 2001Assignee: McMaster UniversityInventors: Robert A. Hughes, Patrick J. Turner, John S Preston
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Patent number: 6232155Abstract: A semiconductor-on-insulator (SOI) device is fabricated by forming spaced apart trenches in a first face of a semiconductor substrate. An insulating layer is formed on the first face of the semiconductor substrate, including on the trenches. A second substrate is bonded to the insulating layer, opposite the semiconductor substrate. The semiconductor substrate is thinned at a second face thereof which is opposite the first face, until a semiconductor film remains on the insulating layer, having alternating thin and thick film semiconductor regions on the insulating layer. Source/drains are formed in the thin film semiconductor regions. Insulated gates are formed on the thick film semiconductor regions, such that a respective insulated gate is located between adjacent source/drains. SOI devices which can suppress floating body effects and yet provide dense integration may thereby be formed.Type: GrantFiled: December 3, 1999Date of Patent: May 15, 2001Assignee: Samsung Electronics Co., Ltd.Inventor: Duck-hyung Lee
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Patent number: 6051846Abstract: A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.Type: GrantFiled: April 1, 1993Date of Patent: April 18, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael J. Burns, Paul R. de la Houssaye, Graham A. Garcia, Stephen D. Russell, Stanley R. Clayton, Andrew T. Barfknecht
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Patent number: 5851843Abstract: A method of manufacturing super conduction field effect transistor having a bi-crystal boundary junction is disclosed. According to the present invention, it is constituted such that on a SrTiO.sub.3 bi-crystal substrate, a bi-crystal super conductive thin films for source and drain electrode having a compound of YBa.sub.2 Cu.sub.3 O.sub.7-x, a non-super conductive oxide layer having a compound of PrBa.sub.2 Cu.sub.3 O.sub.7-x interposed between the bi-crystal super conductive thin films for source and drain electrode and the SrTiO.sub.3 bi-crystal substrate, a boundary channel interposed therebetween, a amorphous insulating layer for gate electrode having a compound of SrTiO.sub.Type: GrantFiled: October 16, 1997Date of Patent: December 22, 1998Assignee: Electronics and Telecommunications Research InstituteInventors: Jeong Dae Suh, Gun Yong Sung
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Patent number: 5747418Abstract: An apparatus and method for producing electricity from heat. The present invention is a thermoelectric generator that uses materials with substantially no electrical resistance, often called superconductors, to efficiently convert heat into electrical energy without resistive losses. Preferably, an array of superconducting elements is encased within a second material with a high thermal conductivity. The second material is preferably a semiconductor. Alternatively, the superconducting material can be doped on a base semiconducting material, or the superconducting material and the semiconducting material can exist as alternating, interleaved layers of waferlike materials. A temperature gradient imposed across the boundary of the two materials establishes an electrical potential related to the magnitude of the temperature gradient. The superconducting material carries the resulting electrical current at zero resistivity, thereby eliminating resistive losses.Type: GrantFiled: October 17, 1996Date of Patent: May 5, 1998Assignee: The United States of America as represented by the United States Department of EnergyInventors: John D. Metzger, Mohamed S. El-Genk
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Patent number: 5739084Abstract: A method for fabricating a superconducting device with a substrate, a first oxide superconductor thin film, a barrier layer, a diffusion layer, and a second oxide superconductor thin film. The first oxide superconductor thin film with a very thin thickness is formed on the principal surface of the substrate. The barrier layer and the diffusion source layer are formed on a portion of the first oxide superconductor thin film. The second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film until the barrier and diffusion source layers are embedded in the second oxide superconductor thin film, so that a material of the diffusion source layer is diffused into the second oxide superconductor thin film.Type: GrantFiled: January 2, 1997Date of Patent: April 14, 1998Assignee: Sumitomo Electric Industries Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5728599Abstract: Process for manufacturing a high interconnection density, fine-line, superconductive printed leadframes using thick-film screen-printing techniques, or other printing techniques. Generally, a superconductive leadframe pattern is printed on a backing substrate. Once the pattern is cured, the backing substrate, or portions thereof can be removed. The backing substrate can be a "fish paper" substrate treated with a release agent, or other substrate material which can be dissolved away, etched away, or otherwise removed. Portions of the backing substrate can be used to provide mechanical integrity for the leadframe. The leadframe fingers can be printed using a superconductive paste or a superconductive precursor paste which is subsequently treated to exhibit superconductivity.Type: GrantFiled: August 7, 1995Date of Patent: March 17, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Mark Schneider, Chok J. Chia
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Patent number: 5672569Abstract: A superconducting circuit having patterned superconducting wiring lines. Each wiring line consists of at least one portion (2') of the thin film (2) of an oxide superconductor deposited on a substrate (1). The portion (2') has a predetermined crystal orientation and the remaining portions (2") have a different crystal orientation or changed to non-superconductor. The superconducting circuit has a planar surface.In variations, two different wiring lines (21, 22) each having a different crystal orientation are produced at different portions of a thin film of oxide superconductor, so that superconducting current flow separately through two different portions in a common thin film.Type: GrantFiled: March 8, 1995Date of Patent: September 30, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5663081Abstract: Disclosed is a method for making a high-temperature super-conducting field-effect transistor with a thick super-conducting channel, the method comprising the steps of depositing a template layer on an oxide crystal substrate by using a pulse laser depositing apparatus; forming a YBa.sub.2 Cu.sub.3 O.sub.7-x layer on the template layer; patterning the YBa.sub.2 Cu.sub.3 O.sub.7-x layer to form a patterned YBa.sub.2 Cu.sub.3 O.sub.7-x layer having an opening and expose a surface portion of the template layer; depositing a YBa.sub.2 Cu.sub.3 O.sub.7-x channel layer on the surface portion of the template layer and over the patterned YBa.sub.2 Cu.sub.3 O.sub.7-x layer, the channel layer having a thickness of from 60 to 100 nm; sequentially forming an SrTiO.sub.3 protective layer and an SrTiO.sub.Type: GrantFiled: November 30, 1994Date of Patent: September 2, 1997Assignee: Electronics and Telecommunications Research InstituteInventors: Gun-Yong Sung, Jeong-Dae Suh
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Patent number: 5650377Abstract: Fine epitaxial patterns of yttrium barium copper oxide on a strontium titanate substrate are provided by using a silicon nitride mask to define the pattern to be formed. A thin film of yttrium barium copper oxide is placed on the silicon nitride mask and exposed portions of strontium titanate substrate. Where the yttrium barium copper oxide is in contact with the silicon nitride mask, it is nonepitaxial in crystal structure. Where the yttrium barium copper oxide contacts the strontium titanate substrate in the openings, it is epitaxial in structure forming fine patterns that become superconducting below the critical transition temperature. A channel can be formed in the strontium titanate substrate. The epitaxial yttrium barium copper oxide pattern is formed in this channel to minimize possible exposure to the silicon nitride mask.Type: GrantFiled: October 5, 1993Date of Patent: July 22, 1997Assignee: International Business Machines CorporationInventors: Dieter Paul Kern, Robert Benjamin Laibowitz, Kim Yang Lee, Mark I. Lutwyche
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Patent number: 5646095Abstract: A method for selectively etching insulative material composed of SrTiO3 or MgO in the presence of a copper oxide perovskite superconductive material includes treating the insulative material with a liquid selective etchant solution containing hydrogen fluoride in water for a period of time, the insulative material being etched at a substantially faster rate than the superconductive material etch rate, then treating the superconductive material exposed to the insulative selective with another etchant to remove a surface layer.Type: GrantFiled: October 5, 1994Date of Patent: July 8, 1997Assignee: International Business Machines CorporationInventors: Walter Eidelloth, William Joseph Gallagher
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Patent number: 5637555Abstract: A method for manufacturing a three-terminal superconducting device is disclosed. A superconducting channel constituted in an oxide superconductor thin film is deposited on a deposition surface of a substrate. A gate electrode for the device is formed through a gate insulator layer on the superconducting channel of the device. The steps of forming the gate electrode include forming a thin film that stands upright with respect to the insulator layer for the gate.Type: GrantFiled: August 23, 1995Date of Patent: June 10, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5593918Abstract: Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g.Type: GrantFiled: April 22, 1994Date of Patent: January 14, 1997Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Mark Schneider, Nicholas F. Pasch, Abraham Yee, William C. Schneider
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Patent number: 5567673Abstract: This invention relates to a process of forming multilayered thallium-containing superconducting composites, wherein a first thallium-containing superconducting layer, an intermediate thallium-containing oxide layer and a second thallium-containing superconducting layer are successively deposited on a substrate by a vapor phase process by controlling the heating temperature, pressure of oxidizing gas and thallium vapor pressure during post-deposition annealing of the superconducting films.Type: GrantFiled: March 29, 1995Date of Patent: October 22, 1996Assignee: E. I. Du Pont de Nemours and CompanyInventors: Dean W. Face, Kirsten E. Myers
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Patent number: 5552375Abstract: Disclosed are methods of forming superconducting devices including a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.Type: GrantFiled: February 7, 1994Date of Patent: September 3, 1996Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Ushio Kawabe, Yoshinobu Tarutani, Shinya Kominami, Toshiyuki Aida, Tokuumi Fukazawa, Mutsuko Hatano
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Patent number: 5547923Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode is formed on the first and second oxide superconducting regions. The superconducting device thus formed can functions as a super-FET.Type: GrantFiled: June 7, 1995Date of Patent: August 20, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5534491Abstract: A process for producing a layered structure containing at least one thin film of oxide superconductor (1) such as Y.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x having a contaminated surface on a substrate (3). The contaminated surface of the thin film of oxide superconductor is heat-treated in an atmosphere containing oxygen of high purity of higher than 5N and a partial pressure of 25 Torr at a temperature of 350.degree. to 700.degree. C. On the thin film of oxide superconductor (1), another thin film (2) of oxide superconductor or non-superconductor is deposited.The resulting structure of layered thin films is used for fabricating superconducting transistor, Josephson junctions, superconducting circuits or the like.Type: GrantFiled: January 31, 1995Date of Patent: July 9, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5512540Abstract: A manufacturing method of a superconducting pattern is described. A superconducting ceramic film is deposited on a non-conductive surface and partly spoiled in order to form a barrier film by which two superconducting regions is separated. The spoiling is performed by adding a spoiling element into the ceramic film by ion implantation.Type: GrantFiled: October 14, 1994Date of Patent: April 30, 1996Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 5510324Abstract: The invention relates to a method of manufacturing a superconducting device, which comprises the steps of forming on a principal surface of a substrate a non-superconducting oxide layer having a similar crystal structure to that of a c-axis oriented oxide superconductor thin film and a flat-top projection at its center portion, forming a c-axis oriented oxide superconductor thin film having an extremely thin thickness on the non-superconducting oxide layer so as to form a superconducting channel on the projecting portion of the non-superconducting oxide layer, forming an insulating layer on the c-axis oriented oxide superconductor thin film so as to form a gate insulating layer on the superconducting channel, and forming an a-axis oriented oxide superconductor thin film so as to form a superconducting source region and a superconducting drain region of which upper surfaces have the same level as that of the superconducting channel.Type: GrantFiled: December 2, 1994Date of Patent: April 23, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
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Patent number: 5509183Abstract: A superconducting device comprising a substrate having a principal surface, a superconducting source region and a superconducting drain region formed of an oxide superconductor on the principal surface of the substrate separated from each other, an extremely thin superconducting channel formed of the oxide superconductor between the superconducting source region and the superconducting drain region. The superconducting channel electrically connects the superconducting source region to a superconducting drain region, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device comprises a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel, and non-superconducting oxide layers having a similar crystal structure to that of the oxide superconductor.Type: GrantFiled: May 12, 1995Date of Patent: April 23, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5494891Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.Type: GrantFiled: December 6, 1994Date of Patent: February 27, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5468723Abstract: A superconducting device has a structure of superconductor--normal--conductor (semiconductor)--superconductor. The superconducting regions and the normal-conductor region can be made of the same elements but having different relative proportions of the elements. The device can be fabricated by introducing at least one element into an unmasked region of the superconductor to form a normal conductor region or into unmasked regions of the normal conductor to form superconductor regions.Type: GrantFiled: May 4, 1994Date of Patent: November 21, 1995Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
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Patent number: 5466664Abstract: A method of manufacturing a superconducting device involves forming a thin film on the surface of a substrate, forming a superconducting gate electrode on a portion of the thin film, etching the portions of the thin film using the gate electrode as a mask thereby providing a superconducting channel under the gate, forming a step portion on the superconducting channel and under the gate, converting the oxide portion of the step portion into a gate insulation portion by heating the substrate in a vacuum, forming a second oxide superconducting film on the exposed surface of the channel so that superconducting source and drain electrodes are formed on each side of the gate such that the drain and source have a thickness greater than that of the channel and are electrically isolated from the gate electrode.Type: GrantFiled: July 26, 1994Date of Patent: November 14, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
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Patent number: 5449659Abstract: A method for producing multilayer structures comprised of materials with incompatible processing parameters is disclosed. A bonding layer of arbitrary dielectric constant is applied to each of two substructures. Each substructure is composed of a substrate and at least one epitaxial crystalline layer. Examples of particular bonding materials used are polyimide, fluorocarbon polymers, other organic materials, and glass. The bonding material may be applied like photoresist, or sputtered, or applied in any appropriate manner consistent with the processing constraints of the crystalline materials. Structures formable in this way include superconductor-amorphous dielectric-superconductor and ferroelectric-insulator-semiconductor trilayers, as well as microwave resonators and multichip modules.Type: GrantFiled: November 9, 1992Date of Patent: September 12, 1995Assignee: Conductus, Inc.Inventors: Stephen M. Garrison, Randy W. Simon
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Patent number: 5434127Abstract: For manufacturing a superconducting device, a first c-axis orientated oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. An a-axis orientated oxide superconductor thin film is grown, using the gate electrode as a mask, so that second and third superconducting regions having a relatively thick thickness are formed at both sides of the gate electrode, electrically isolated from the gate electrode. The superconducting device thus formed can functions as a super-FET.Type: GrantFiled: July 25, 1994Date of Patent: July 18, 1995Assignee: Sumitomo Electric Industries, ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5420101Abstract: The invention relates to a structured superconductive track and a process for making it from epitaxial high temperature superconductor (HTSC) layers using lift off technique, in which a HTSC track deposited on an elevated substrate region is surrounded by an insulating layer of doped HTSC lying on a lower substrate region, and the substrate region with the superconductive track formed thereon is elevated such that the superconductive track is isolated from the insulating layer.Type: GrantFiled: December 23, 1993Date of Patent: May 30, 1995Assignee: Forschungszentrum Julich GmbHInventors: Carlo Copetti, Jurgen Schubert, Willi Zander, Christoph Buchal
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Patent number: 5401714Abstract: A field-effect structure formed on a substrate and comprising a channel with source and drain as well as a gate that is separated from the channel by an insulating layer. The channel is made of a high T.sub.c metal-oxide superconductor, e.g., YBaCuO, having a carrier density of about 10.sup.21 /cm.sup.3 and a correlation length of about 0.2 nm. The channel thickness is preferrable in the order of 1 nm. The superconductor is preferably a single crystalline and oriented such that the superconducting behavior is strongest in the plane parallel to the substrate. With a signal of a few volts applied to the gate, the entire channel cross-section is depleted of charge carriers whereby the channel resistance can be switched between a "zero resistance" (undepleted, superconducting) state and "very high resistance" (depleted state).Type: GrantFiled: May 4, 1994Date of Patent: March 28, 1995Assignee: International Business Machines CorporationInventors: Preveen Chaudhari, Carl A. Mueller, Hans P. Wolf
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Patent number: 5401716Abstract: A manufacturing method of Josephson devices is described. A superconducting ceramic film is deposited on a non-conductive surface and partly spoiled in order to form a barrier film by which two superconducting regions is separated. The spoiling is performed by adding a spoiling element into the ceramic film by ion implantation.Type: GrantFiled: February 3, 1992Date of Patent: March 28, 1995Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki