Etching Patents (Class 505/728)
  • Patent number: 8735326
    Abstract: Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: May 27, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Erica Folk, Patrick B. Shea, Andrew C. Loyd
  • Patent number: 7674751
    Abstract: A method of making a laminated superconductor wire includes providing an assembly, where the assembly includes a substrate; a superconductor layer overlaying a surface of the substrate, the superconductor layer having a defined pattern; and a cap layer; and slitting the assembly in accordance with the defined pattern of the superconductor layer to form a sealed wire. Slitting the assembly in accordance with the defined pattern may form multiple sealed wires, and the substrate may be substantially wider than the sealed wires.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: March 9, 2010
    Assignee: American Superconductor Corporation
    Inventors: Alexis P. Malozemoff, Martin W. Rupich, Douglas C. Folts
  • Patent number: 6974501
    Abstract: The invention relates to multi-layer articles and methods of making such articles. The methods include first conditioning the surface of an underlying layer, such as a buffer layer or a superconductor layer, then disposing a layer of material on the conditioned surface. The conditioned surface can be a high quality surface. Superconductor articles formed by these methods can exhibit relatively high critical current densities.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: December 13, 2005
    Assignee: American Superconductor Corporation
    Inventors: Wei Zhang, Martin W. Rupich, Suresh Annavarapu, Leslie G. Fritzemeier, Edward J. Siegal, Valery Prunier, Qi Li
  • Patent number: 6339047
    Abstract: Methods of treating superconducting composites to enhance their wettability in solder, and composites having enhanced wettability. It has been found that wettability can be substantially enhanced by stripping a thin layer off the surface of the composite before incorporating it into a laminated component. This layer can be stripped, for example, by chemically etching the composite, for example in a solution of nitric acid and ammonium bifluoride.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: January 15, 2002
    Assignee: American Semiconductor Corp.
    Inventors: Craig J. Christopherson, David M. Olen, Deborah L. Ouellette, Thomas De Santos, Eric R. Podtburg, Sy-Jenq Loong
  • Patent number: 6270688
    Abstract: A method of polishing ferroelectric materials and specifically perovskite materials and still more specifically barium strontium titanate (1) wherein the surface (5) to be polished is initially partially smoothened or planarized by mechanical abrading with final smoothening or planarization provided by a chemical polishing with a polishing wheel using an acidic solution containing essentially the acid, hydrogen peroxide and water. Preferred acids are perchloric acid, acetic acid, nitric acid and combinations thereof.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: August 7, 2001
    Assignee: Raytheon Company
    Inventors: James F. Belcher, Howard R. Beratan, Paul O. Johnson
  • Patent number: 6207067
    Abstract: A method for fabricating an oxide superconducting device includes the steps of: forming a V-shaped groove on a substrate by a converging ion beam and forming a barrier with reduced superconductivity on the oxide superconducting thin-film on the groove to form a Josephson Junction, wherein the irradiation ion amount of the converging ion beam is varied according to the position of the beam within the groove in such a manner that an inclination angle of the inclined portion of the substrate is fixed. An oxide superconducting device (a Josephson Junction device) having a high degree of flexibility in arrangement and with high reproducibility, and having a high degree of uniformity is provided.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: March 27, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, International Superconductivity Technology Center
    Inventors: Naoki Yutani, Katsumi Suzuki, Youichi Enomoto, Jian-Guo Wen
  • Patent number: 6060433
    Abstract: The invention provides a structure comprising a high temperature superconducting layer deposited on a ceramic polycrystalline ferrite plate suitable for making commercial microwave devices. In one embodiment, the high temperature superconductor is yttrium barium copper oxide (YBCO), the ferrite is yttrium iron garnet (YIG), and the microwave device is a phase shifter. The method of making this embodiment comprises, polishing the YIG plate, depositing biaxially oriented yttria-stabilized zirconia (YSZ) to form a crystalline template using an ion-beam-assisted-deposition technique, depositing a CeO.sub.2 lattice matching buffer layer using pulsed laser deposition, depositing YBCO using pulsed laser deposition, and annealing the YBCO in oxygen. Etching the YBCO to form a meanderline patterned waveguide results in a high figure-of-merit microwave phase shifter when the device is cooled with liquid nitrogen and an external magnetic field is applied.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: May 9, 2000
    Assignee: NZ Applied Technologies Corporation
    Inventors: Yi-Qun Li, Hua Jiang
  • Patent number: 5952269
    Abstract: A method for forming a superconducting device using a selective etching technique on superconducting thin films. The method utilizes rapid etching which combines ion implantation with chemical etching. The portions of the superconducting film to be retained are masked from the ion implantation process. The chemical etching process then removes the implanted portions of the superconducting film at a much faster rate than the portions not implanted so that only the un-implanted portions remain. The resulting superconducting devices can be used, e.g., as nanostructures and nano tips, bolometers, multilayer RF coils, microwave waveguides and filters.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: September 14, 1999
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Qiyuan Ma, Mingling Chen
  • Patent number: 5840204
    Abstract: A method for patterning an oxide superconductor thin film, comprising a step of forming a SiO.sub.2 layer on the oxide superconductor thin film, patterning the SiO.sub.2 layer so as to form the same pattern as that of the oxide superconductor thin film which will be patterned, etching the oxide superconductor thin film by using the patterned SiO.sub.2 layer as a mask, and removing the SiO.sub.2 layer by using a weak HF solution, a buffer solution including HF or a mixture including HF.
    Type: Grant
    Filed: April 5, 1995
    Date of Patent: November 24, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, So Tanaka, Michitomo Iiyama
  • Patent number: 5789346
    Abstract: Method for manufacturing a superconducting device including forming on a surface of a substrate a non-superconducting oxide layer, a first oxide superconductor thin film, etching the first oxide superconductor thin film so as to form a concave portion, implanting ions to the first oxide superconductor thin film at the bottom of the concave portion so as to form an insulating region such that the first oxide superconductor thin film is divided into two superconducting regions by the insulating region, and forming a second oxide superconductor thin film on the insulating region and the two superconducting regions, which is continuous to the two superconducting regions.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: August 4, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5750474
    Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: May 12, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: 5739084
    Abstract: A method for fabricating a superconducting device with a substrate, a first oxide superconductor thin film, a barrier layer, a diffusion layer, and a second oxide superconductor thin film. The first oxide superconductor thin film with a very thin thickness is formed on the principal surface of the substrate. The barrier layer and the diffusion source layer are formed on a portion of the first oxide superconductor thin film. The second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film until the barrier and diffusion source layers are embedded in the second oxide superconductor thin film, so that a material of the diffusion source layer is diffused into the second oxide superconductor thin film.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: April 14, 1998
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5688383
    Abstract: A method for decreasing the microwave surface impedance of high-temperature superconducting thin films comprises (a) applying, preferably by spin-coating, a protective coating (preferably poly(methyl methacrylate) or polyimide) to the surface of a high-temperature superconducting thin film, such as Tl.sub.2 Ba.sub.2 CaCu.sub.2 O.sub.8 ; (b) exposing the coated thin film to low angle ion milling at an incident angle of 5.degree. to 30.degree. (preferably 10.degree. to 20.degree.) relative to the surface of the coated film; and (c) optionally including the step of removing any residual protective coating from the surface of the thin film, such as by exposure to an oxygen plasma.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: November 18, 1997
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: Philip Shek Wah Pang
  • Patent number: 5677265
    Abstract: A process for the oxygenation of ceramic high T.sub.c superconductors is disclosed. The superconductor is formed from a sintered powdered ceramic. Microchannels are formed in the ceramic material by embedding in the powder a plurality of wires or fibers formed of a material which is thermally removable during the sintering process to leave thin, continuous, tubular channels. After sintering, the ceramic is exposed to oxygen in a high temperature, high pressure environment. The microchannels aid in the transport of oxygen into the interior of the material by providing passages along which the oxygen travels prior to diffusing into the material. The lengths of the diffusion paths in the material are thereby greatly shortened. In another embodiment, the channels are formed after sintering and prior to oxygenation by drilling, punching, or etching.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: October 14, 1997
    Assignee: Northeastern University
    Inventors: Bill C. Giessen, Robert S. Markiewicz, Bala Maheswaran, Thomas R. Gilbert
  • Patent number: 5650377
    Abstract: Fine epitaxial patterns of yttrium barium copper oxide on a strontium titanate substrate are provided by using a silicon nitride mask to define the pattern to be formed. A thin film of yttrium barium copper oxide is placed on the silicon nitride mask and exposed portions of strontium titanate substrate. Where the yttrium barium copper oxide is in contact with the silicon nitride mask, it is nonepitaxial in crystal structure. Where the yttrium barium copper oxide contacts the strontium titanate substrate in the openings, it is epitaxial in structure forming fine patterns that become superconducting below the critical transition temperature. A channel can be formed in the strontium titanate substrate. The epitaxial yttrium barium copper oxide pattern is formed in this channel to minimize possible exposure to the silicon nitride mask.
    Type: Grant
    Filed: October 5, 1993
    Date of Patent: July 22, 1997
    Assignee: International Business Machines Corporation
    Inventors: Dieter Paul Kern, Robert Benjamin Laibowitz, Kim Yang Lee, Mark I. Lutwyche
  • Patent number: 5646095
    Abstract: A method for selectively etching insulative material composed of SrTiO3 or MgO in the presence of a copper oxide perovskite superconductive material includes treating the insulative material with a liquid selective etchant solution containing hydrogen fluoride in water for a period of time, the insulative material being etched at a substantially faster rate than the superconductive material etch rate, then treating the superconductive material exposed to the insulative selective with another etchant to remove a surface layer.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: July 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Walter Eidelloth, William Joseph Gallagher
  • Patent number: 5599465
    Abstract: A method is provided for producing superconducting Josephson devices using a chemical etching solution which comprises forming a mask on a predetermined portion of a MgO substrate, and immersing the MgO substrate having the mask in an aqueous acid solution in which the volume ratio of phosphoric acid to sulfuric acid is approximately 10:1 or more, so as to form a step at the boundary between the masked region and the unmasked region.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: February 4, 1997
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chan H. Park, Jin P. Hong
  • Patent number: 5571778
    Abstract: A superconductor junction material is disclosed which comprises a substrate of a single crystal, and at least flux flow element, and optionally at least one Josephson junction element, provided on the surface, each of the flux flow and Josephson junction elements being formed of a superconducting oxide layer having a weak link. The flux flow and Josephson junction elements are prepared by vacuum deposition at different oxygen partial pressures.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: November 5, 1996
    Assignees: Superconductivity Research Laboratory of International Superconductivity Technology Center, Sharp Corporation
    Inventors: Manabu Fujimoto, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
  • Patent number: 5547923
    Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode is formed on the first and second oxide superconducting regions. The superconducting device thus formed can functions as a super-FET.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 20, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5494891
    Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5446016
    Abstract: A method for forming a patterned oxide superconductor thin film on a substrate comprises steps of forming a metal or semi-metal layer on a portion of the substrate, on which the oxide superconductor thin film will be formed, forming a layer of a material including silicon on a portion of the substrate, on which an insulating layer will be formed, removing the metal or semi-metal layer and depositing an oxide superconductor thin film over the substrate.
    Type: Grant
    Filed: February 15, 1994
    Date of Patent: August 29, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5434127
    Abstract: For manufacturing a superconducting device, a first c-axis orientated oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. An a-axis orientated oxide superconductor thin film is grown, using the gate electrode as a mask, so that second and third superconducting regions having a relatively thick thickness are formed at both sides of the gate electrode, electrically isolated from the gate electrode. The superconducting device thus formed can functions as a super-FET.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: July 18, 1995
    Assignee: Sumitomo Electric Industries, ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5418213
    Abstract: A method for forming an oxide superconductor thin film having different thickness portions, in a process for manufacturing a superconductor device, includes the step of forming an oxide superconductor thin film having a uniform thickness on a substrates. A portion of the oxide superconductor thin film is etch-removed so that the oxide superconductor thin film has a thin thickness portion. Preferably, before the etching, the oxide superconductor thin film is coated with a metal layer, and the oxide superconductor thin film and the metal layer are etched together by means of a physical dry etching process.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: May 23, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Hideo Itozaki, Shuji Yazu
  • Patent number: 5411937
    Abstract: A novel method for fabricating nanometer geometry electronic devices is described. Such Josephson junctions can be accurately and reproducibly manufactured employing photolithographic and direct write electron beam lithography techniques in combination with aqueous etchants. In particular, a method is described for manufacturing planar Josephson junctions from high temperature superconducting material.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: May 2, 1995
    Assignee: Sandia Corporation
    Inventors: Joel R. Wendt, Thomas A. Plut, Jon S. Martens
  • Patent number: 5356870
    Abstract: An ion beam is irradiated to an oxide superconducting thin film formed on a substrate to disturb the crystal structure of the superconducting thin film and thus forming a damaged layer. The damaged layer has higher solubility in a halogen solution has a faster etching rate than other portions. Then, the superconducting thin film is etched by using a halogen solution to remove the damaged layer and form a groove at that portion. As a result, a groove of a desired form can be provided efficiently.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: October 18, 1994
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuji Fujiwara, Ryokan Yuasa, Hiroaki Furukawa, Masaaki Nemoto, Masao Nakao
  • Patent number: 5326747
    Abstract: A process for patterning layered thin films comprising a bottom oxide superconductor (1) layer deposited on a substrate (3) and another thin film (2) deposited on the bottom superconductor layer and consisting of insulator, ordinary conductor or oxide superconductor having a different crystal orientation from the bottom superconductor layer. The bottom superconductor layer (1) is subjecting to heat-treatment before another thin film (2) is deposited thereon. The heat-treatment can be carried out under a first condition in ultra high-vacuum at a temperature which is lower than the oxygen-trap temperature (T.sub.trap) at which oxygen can enter into the oxide superconductor but is higher than a temperature which is lower by 100.degree. C. than the oxygen-trap temperature (T.sub.trap -100.degree. C.) or under a second condition in an atmosphere containing oxygen of high purity at a temperature which is higher than the oxygen-trap temperature (T.sub.
    Type: Grant
    Filed: April 9, 1992
    Date of Patent: July 5, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5321004
    Abstract: A Josephson break junction device suitable for highly sensitive electronic detecting systems. A superconductor film such as YBa.sub.2 Cu.sub.3 O.sub.7 is deposited on a substrate such as a simple-crystal MgO. The film is fractured across a narrow strip by at least one indentation in the substrate juxtaposed from the strip to form a break junction. A transducer is affixed to the substrate for applying a bending movement to the substrate to regulate the distance across the gap formed at the fracture to produce a Josephson turned junction effect. Alternatively, or in addition to the transducer, a bridge of a novel metal is applied across the gap to produce a weak-link junction.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: June 14, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ignacio M. Perez, William R. Scott
  • Patent number: 5306702
    Abstract: A process for producing a Bi-based perovskite superconducting film, comprising the steps of forming on a substrate a Pb-film, containing Bi-base material film comprising Bi, Pb, Sr, Ca and Cu in a Bi:Pb:Sr:Ca:Cu molar ratio of (1.9 to 2.1):(1.2 to 2.2, preferably 1.5 to 1.8):2:(1.9 to 2.2):(3 to 3.5) and sintering the Pb-containing Bi-base material film in an oxygen-containing atmosphere. The sintering step includes a main sintering period of 20 to 120 minutes, in which the temperature is raised from a first temperature to a second temperature, with the second temperature being in a range of 850.degree. to 860.degree. C., and the temperature rise in the main sintering period of 20 to 120 minutes being from 3.degree. to 10.degree. C.
    Type: Grant
    Filed: June 17, 1992
    Date of Patent: April 26, 1994
    Assignee: Fujitsu Limited
    Inventors: Atsushi Tanaka, Nobuo Kamehara, Koichi Niwa
  • Patent number: 5304535
    Abstract: A process for etching with a scanning tunneling microscope on both a single crystal and a thin film of high temperature superconductor is disclosed.
    Type: Grant
    Filed: October 29, 1990
    Date of Patent: April 19, 1994
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Mark A. Harmer, Bruce A. Parkinson
  • Patent number: 5292717
    Abstract: A method for producing a structured layer of a first material having at least one recess of a predetermined geometrical shape on a substructure formed of at least one second material that includes a metal oxide superconductor material with a high transition temperature which is sensitive to solvents containing acids includes the steps of: forming a first composite by applying a varnish layer to the substructure which is soluble in a first solvent that does not attack the substructure such that the varnish layer has a structure corresponding to the structure of the structured layer of the first material to be produced; cold depositing on the first composite an auxiliary layer of a third material that is soluble in a second solvent which does not attack the first and second materials; forming a second composite from the first composite by removing with the first solvent the varnish layer along with a part of the auxiliary layer resting thereon; applying a coating layer of the first material to the second compos
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: March 8, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventor: Bernhard Roas
  • Patent number: 5286336
    Abstract: A Josephson junction and a method for its fabrication in which a laminated junction layer is formed in situ on the side edge of a base electrode contact. The laminated junction layer forms the Josephson junction of the present invention and includes an insulating or barrier layer sandwiched between a superconducting base electrode and a superconducting counter electrode. The Josephson junction is formed on the side edge of the base electrode contact to allow very small junction areas to be fabricated using conventional optical lithographic techniques, such as photolithography. The laminated junction layer is formed in situ, with the three layers of the laminated junction layer being formed successively without removing the device from the controlled atmosphere of the deposition system, to prevent contamination of the junction region.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: February 15, 1994
    Assignee: TRW Inc.
    Inventors: Hugo W. Chan, Arnold H. Silver, Robert D. Sandell, James M. Murduck
  • Patent number: 5280013
    Abstract: A superconducting electronic circuit device, useful when impedance matching is desired, especially suited to microwave frequencies, consisting of a thin dielectric layer with superconducting layers on both sides. A superconductor such as Yttrium Barium Copper Oxide (YBCO) is formed on a first substrate such as lanthanum aluminate. A protective layer like gold is deposited on the YBCO and a second carrier substrate is bonded to the protected YBCO. The first substrate is then thinned into a thin dielectric film and a second layer of superconductor is epitaxially grown thereon to create the desired circuits.
    Type: Grant
    Filed: October 29, 1992
    Date of Patent: January 18, 1994
    Assignee: Conductus, Inc.
    Inventors: Nathan Newman, Aharon Kapitulnik, Brady F. Cole, Randy W. Simon
  • Patent number: 5278140
    Abstract: A method is disclosed for fabricating grain boundary junction devices, which comprises preparing a crystalline substrate containing at least one grain boundary therein, epitaxially depositing a high Tc superconducting layer on the substrate, patterning the superconducting layer to leave at least two superconducting regions on either side of the grain boundary and making electrical contacts to the superconducting regions so that bias currents can be produced across the grain boundary.
    Type: Grant
    Filed: September 16, 1992
    Date of Patent: January 11, 1994
    Assignee: International Business Machines Corporation
    Inventors: Praveen Chaudhari, Cheng-Chung J. Chi, Duane B. Dimos, Jochen D. Mannhart, Chang C. Tsuei
  • Patent number: 5250507
    Abstract: In the process for producing molded bodies from precursors of oxidic high-temperature superconductors of the BSCCO type, a copper mold of the desired shape which encloses a solidified bismuth strontium calcium cuprate melt is wired as anode in a direct current circuit composed of anode, cathode and an electrolyte, a dilute sulfuric acid is used as electrolyte and the electrolyte is subjected to a direct current of 1 to 50 mA.cm.sup.-2 until the copper mold wired as anode is dissolved and the BSCCO molded body is laid bare.
    Type: Grant
    Filed: August 2, 1991
    Date of Patent: October 5, 1993
    Assignee: Hoechst Aktiengesellschaft
    Inventors: Eberhard Preisler, Joachim Bock
  • Patent number: 5248657
    Abstract: A superconducting conductor assembly using high temperature materials. A double-walled tubular structure has at least one helical strip of superconductive material on the inner wall of the inside tube. Brittle, non-ductile superconducting materials may be used. A coolant, typically liquid nitrogen, is circulated between the tubes to maintain the superconductor below the critical temperature of the superconductor. A buffer layer is preferably included between tube wall and superconductor. A plurality of alternating layers of buffer and superconductor may be used.
    Type: Grant
    Filed: May 13, 1991
    Date of Patent: September 28, 1993
    Assignee: General Dynamics Corporation, Space Systems Division
    Inventors: Richard E. Bailey, Foster M. Kimball, Eddie M. Leung, Robert D. McConnell
  • Patent number: 5238913
    Abstract: Superconducting microcircuits including a thin layer of Ba.sub.2 Cu.sub.3 O.sub.5+x (0<x<1) on a substrate. A thin layer of a dopant; for example, Y.sub.2 O.sub.3 for superconducting patterns of YBa.sub.2 Cu.sub.3 O.sub.7-x, or Pr.sub.2 O.sub.3 for insulator patterns of PrBa.sub.2 Cu.sub.3 O.sub.7-x. These layers are covered with a layer of photoresist, which is exposed to light through a mask having a pattern for a desired circuit. The photoresist is then developed to reveal a pattern of the thin dopant layer which will be etched away. The microcircuit is then etched and stripped to remove the unneeded portion of the thin dopant layer. Finally, the microcircuit is heated at a temperature and for a period of time sufficient to diffuse and react the dopant layer with the thin layer of Ba.sub.2 Cu.sub.3 O.sub.5+x, forming a pattern of superconductor or insulator.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: August 24, 1993
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Nicholas V. Coppa
  • Patent number: 5231073
    Abstract: The structures for confining or guiding high frequency electromagnetic radiation have surfaces facing the radiation constructed of high temperature superconducting materials, that is, materials having critical temperatures greater than approximately 35.degree. K. The use of high temperature superconductors removes the constraint of the relatively low energy gaps of conventional, low temperature superconductors which precluded their use at higher frequencies. The high temperature superconductors also provide larger thermal margins and more effective cooling. Devices which will benefit from the structures of the invention include microwave cavities, millimeter-wave/far infrared cavities, gyrotron cavities, mode converters, accelerators and free electron lasers, and waveguides.
    Type: Grant
    Filed: October 18, 1989
    Date of Patent: July 27, 1993
    Assignee: Massachusetts Institute of Technology
    Inventors: Daniel R. Cohn, Leslie Bromberg, Benjamin Lax, Ward D. Halverson, Paul P. Woskov
  • Patent number: 5227364
    Abstract: A method of forming a fine groove on a superconducting thin film. A superconducting oxide thin film is formed on a MgO substrate, and a damaged layer is formed thereon by irradiating the superconducting thin film with focused ion beams to such a degree that not sputter is generated and the crystalline structure of the superconducting thin film is disturbed. The damaged layer is then removed by treatment with a strong alkali such as KOH. Thus, a fine groove is effectively formed. By inserting an oxide layer between the substrate and the superconducting thin film, a Josephson junction device suitable for superconducting transistors is produced.
    Type: Grant
    Filed: June 27, 1991
    Date of Patent: July 13, 1993
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuji Fujiwara, Ryokan Yuasa, Masao Nakao, Masaaki Nemoto
  • Patent number: 5219826
    Abstract: A superconducting Josephson junction is created in high T.sub.c superconducting film, with a bridge connecting two superconducting banks, by subjecting the bridge to a tunneling electron current from a sharp electrode close to the bridge. The tunneling current alters the structure over atomic dimensions to create a weak link of length comparable to high T.sub.c coherence lengths so as to permit phase coherent Cooper pair current flow across the weak link.
    Type: Grant
    Filed: August 20, 1990
    Date of Patent: June 15, 1993
    Assignee: Conductus, Inc.
    Inventor: Aharon Kapitulnik
  • Patent number: 5219830
    Abstract: A process for preparing high-Tc superconducting integrated circuits by using a method in which a thin surface layer of non-superconducting tetragonal YBa.sub.2 Cu.sub.3 Oy wafer is selectively transformed into a superconducting orthorhombic phase by oxygen-diffusion. The superconducting orthorhombic islands are surrounded with non-superconducting tetragonal phases and these are electrically isolated from each other. The process results in the formation of superconducting integrated circuits which are inexpensive and are high in quality.
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: June 15, 1993
    Assignee: Samsung Electro-Mechanics
    Inventors: Ju Y. Jeong, Song I. H., Seok Y. Yoon, Sang C. Park
  • Patent number: 5215960
    Abstract: In a method of manufacturing a superconducting device which has a first thin film of oxide superconductor material formed on a substrate and a second thin film formed on the first thin film of oxide superconductor material, after the second thin film is deposited on the first thin film of oxide superconductor material, a multi-layer structure formed of the first and second thin films is patterned so that a side surface of the first thin film is exposed. In this condition, the whole of the substrate is heated in an O.sub.2 atmosphere or in an O.sub.3 atmosphere so that oxygen is entrapped into the first thin film of oxide superconductor material. Thereafter, the patterned multi-layer structure is preferably covered with a protection coating.
    Type: Grant
    Filed: July 16, 1991
    Date of Patent: June 1, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Sou Tanaka, Mitsuchika Saitoh, Michitomo Iiyama
  • Patent number: 5212147
    Abstract: A method of forming a patterned in-situ photoconductive film on a substrate including providing a patterned photoresist layer on upper and lower metallic layers formed on a substrate. The patterned photoresist layer is used to form an opening in the upper layer. The pattern in the upper layer thereby has an opening having a geometry substantially similar to a desired pattern of photoconductive material to be formed on the substrate. A portion of the lower layer is removed to form cantilevered regions of the upper layer adjacent to the opening. Superconductive material is then deposited on the substrate by directing the material through the opening at an angle generally perpendicular to the substrate. The superconductive film on the substrate within the lower layer is coated with a polymer. The upper and lower layers and all superconductive material on those layers are removed to leave the polymer-encapsulated superconductive material on the substrate.
    Type: Grant
    Filed: May 15, 1991
    Date of Patent: May 18, 1993
    Assignee: Hewlett-Packard Company
    Inventor: James R. Sheats
  • Patent number: 5198412
    Abstract: A process is disclosed for producing superconductor films on a variety of substrates, and more particularly a patterned superconductor film on a planar substrate. The basic process includes the steps of: 1) depositing a metal film of superconductor precursor elements on a substrate; 2) patterning the metal film; and 3) oxidizing the metal film to form a superconductor film. Because the process separates the metal precursor film formation, patterning, and oxidation steps, each of the steps can be individually optimized.
    Type: Grant
    Filed: December 13, 1991
    Date of Patent: March 30, 1993
    Assignee: Hewlett-Packard Company
    Inventors: V. K. Nagesh, John T. Anderson
  • Patent number: 5196395
    Abstract: A method for generating repeatable and reproducible crystallographic grain-boundary junctions is provided by forming a film on a crystalline substrate which has intersecting faces. In a preferred embodiment, a single crystal substrate is etched by an anisotropic etchant to provide a "V"-groove in one face, and an epitaxial superconducting film is grown on the faces of the V-groove. In another preferred embodiment, a step is etched with an anisotropic etch, and an epitaxial superconducting film grown on the step. Grain-boundary junctions are formed at the points of intersection of the faces with each other, or with the faces and the surface of the substrate. The film may be patterned and etched in the area of the boundary junction to form useful devices.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: March 23, 1993
    Assignee: Superconductor Technologies, Inc.
    Inventors: Timothy W. James, Julia S. Fleming
  • Patent number: 5131976
    Abstract: A Josephson junction apparatus comprises a polymeric film having flexiblity, and a Josephson junction circuit formed on the polymeric film. The Josephson junction circuit includes a Josephson junction device and a wiring for connecting to the Josephson junction device. Namely, the Josephson junction apparatus has flexibility, and thus the Josephson junction apparatus can be placed not only on a flat surface but also it can be placed on a curved surface in practice. Furthermore, in the Josephson junction apparatus, when a functional polymeric film is used as a substrate of a Josephson junction of the Josephson junction device, a protective film is previously formed over the functional polymeric film, so that a wetting of the functional polymer film, which is caused by water or organic solvents being used used repeatedly during the manufacturing process, can be prevented and a dimensional stability of the film can be increased.
    Type: Grant
    Filed: November 13, 1990
    Date of Patent: July 21, 1992
    Assignee: Fujitsu Limited
    Inventor: Hiromasa Hoko
  • Patent number: 5087608
    Abstract: A method for the passivation of superconductive rare earth cuprates involves depositing thereon a thin film of an amorphous or diamond-like carbon film of a thickness ranging from 100 .ANG. to 10 microns. The cuprate film may be in the as-deposited form, so necessitating a subsequent annealing step to convert the film to a superconducting phase and to remove the carbon.
    Type: Grant
    Filed: December 28, 1989
    Date of Patent: February 11, 1992
    Assignee: Bell Communications Research, Inc.
    Inventors: Siu W. Chan, Leonilda A. Farrow
  • Patent number: 5059581
    Abstract: The surface of high temperature superconductors such as YBa.sub.2 Cu.sub.3 O.sub.7-x are passivated by reacting the native Y, Ba and Cu metal ions with an anion such as sulfate or oxalate to form a surface film that is impervious to water and has a solubility in water of no more than 10.sup.-3 M. The passivating treatment is preferably conducted by immersing the surface in dilute aqueous acid solution since more soluble species dissolve into the solution. The treatment does not degrade the superconducting properties of the bulk material.
    Type: Grant
    Filed: June 28, 1990
    Date of Patent: October 22, 1991
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Richard P. Vasquez
  • Patent number: 5055158
    Abstract: A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas, depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface with the tops of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.
    Type: Grant
    Filed: April 4, 1991
    Date of Patent: October 8, 1991
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Chao-Kun Hu, Mark A. Jaso, Mark B. Ketchen, Alan W. Kleinsasser, Dale J. Pearson
  • Patent number: 5041188
    Abstract: A high temperature superconductor (HTS) fabrication process employs a two level metal deposition sequence for depositing a layer of metal (14, 18) over HTS material (12) to protect the HTS material from subsequent, possibly deleterious, processing steps. The process of the invention provides a capability for both patterning a HTS film material and electrically contacting the film using conventional photolithographic processes. The process of the invention furthermore accomplishes these objectives without degrading the superconducting properties of the film. The two level metal process protects the film from aqueous based processes such as photoresist development. The two level metal process furthermore does not require processes such as aqueous based chemical etching or ion milling of the surfaces of the superconducting film, thereby eliminating at least two processes which are known to degrade the superconducting properties of HTS material.
    Type: Grant
    Filed: June 12, 1990
    Date of Patent: August 20, 1991
    Assignee: Santa Barbara Research Center
    Inventors: James M. Myrosznyk, Jerry A. Wilson, Michael Ray
  • Patent number: 4996191
    Abstract: An etchant containing 1-hydroxy-ethane-1,1-diphosphonic acid is useful in etching Ba--Cu--O and Ca--Cu--O high-temperature superconductors.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: February 26, 1991
    Assignee: Lion Corporation
    Inventors: Takeshi Kobayashi, Masayoshi Tonouchi, Yoshiyuki Sakaguchi