And Etching Patents (Class 505/820)
  • Patent number: 11882771
    Abstract: Techniques and methods to form smooth metal layers deposited onto selected surfaces of Josephson junction devices are provided. For example, one or more embodiments described herein can comprise depositing a layer of a first material comprising metal atom species on a selected surface of a device layer; depositing a layer of a second material on a surface of the layer of first material; and performing plasma etching on the layer of second material and the layer of first material to form an etched surface of the layer of first material that is smoother than the surface of the layer of first material, as deposited.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathryn Jessica Pooley, Hongwen Yan, Gerald W. Gibson
  • Patent number: 6339047
    Abstract: Methods of treating superconducting composites to enhance their wettability in solder, and composites having enhanced wettability. It has been found that wettability can be substantially enhanced by stripping a thin layer off the surface of the composite before incorporating it into a laminated component. This layer can be stripped, for example, by chemically etching the composite, for example in a solution of nitric acid and ammonium bifluoride.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: January 15, 2002
    Assignee: American Semiconductor Corp.
    Inventors: Craig J. Christopherson, David M. Olen, Deborah L. Ouellette, Thomas De Santos, Eric R. Podtburg, Sy-Jenq Loong
  • Patent number: 6110392
    Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: August 29, 2000
    Assignee: TRW Inc.
    Inventors: George L. Kerber, Michael Leung
  • Patent number: 5578226
    Abstract: A multi-layer superconductive interconnect structure includes a first multi-layer substrate with a first superconducting layer (SL) deposited on a first epitaxial substrate and a first glue dielectric layer (GDL) on the first SL. A second multi-layer substrate includes a second SL deposited on a second epitaxial substrate and a second GDL on said second SL. The first GDL and the second GDL are clamped and cured together to form a composite substrate.
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: November 26, 1996
    Assignee: TRW Inc.
    Inventors: Hugo W. Chan, Arnold H. Silver
  • Patent number: 5462762
    Abstract: A method of fabricating a superconducting quantum interference device (DC-SQUID) constructed from short weak links with untrafine wires. The method comprises the following steps: successive forming a niobium nitride film and a silicon nitride film on a substrate; oblique etching of the niobium nitride film and said silicon nitride film with respect to the substrate by a reactive ion etching process using a mixture of oxygen and CF.sub.4 gases to form an olique edge; and successive forming a barrier thin film and a counterelectrode of niobium on the said edge. The short weak links wire fabricated by field evaporation technique. The counterelectrode material were field-evaporated and formed the conductive paths in the pinholes in the insulating thin film.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: October 31, 1995
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yoshio Onuma, Katsuyoshi Hamasaki
  • Patent number: 5462919
    Abstract: For manufacturing a superconducting thin film having at least one non-superconducting region at and near its surface portion, an oxide superconductor thin film is formed on a surface of the substrate. The oxide superconductor thin film is heated in high vacuum environment so that oxygen of the oxide superconductor crystals escapes from the surface of the oxide superconductor thin film and a surface portion of the oxide superconductor thin film having a substantial thickness changes into non-superconducting layer of a compound oxide which is composed of the same constituent elements as those of the oxide superconductor but includes the oxygen amount less than that of the oxide superconductor and a thin superconducting channel is formed under the non-superconducting layer.
    Type: Grant
    Filed: February 18, 1994
    Date of Patent: October 31, 1995
    Assignee: Sumitomo Electric Industries,Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: 5439875
    Abstract: A Josephson junction device comprises a single crystalline substrate including a principal surface having a first and a second regions of which at least lattice distance of exposed lattices are slightly different from each other and an oxide superconductor thin film formed on the principal surface of the substrate. The oxide superconductor thin film includes a first and a second portions respectively positioned on the first and the second regions of the substrate, which are constituted of single crystals of the oxide superconductor, lattices of the one shifts at angle of 45.degree. to that of the other, and a grain boundary between said two portions, which constitutes a weak link of the Josephson junction.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: August 8, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5131976
    Abstract: A Josephson junction apparatus comprises a polymeric film having flexiblity, and a Josephson junction circuit formed on the polymeric film. The Josephson junction circuit includes a Josephson junction device and a wiring for connecting to the Josephson junction device. Namely, the Josephson junction apparatus has flexibility, and thus the Josephson junction apparatus can be placed not only on a flat surface but also it can be placed on a curved surface in practice. Furthermore, in the Josephson junction apparatus, when a functional polymeric film is used as a substrate of a Josephson junction of the Josephson junction device, a protective film is previously formed over the functional polymeric film, so that a wetting of the functional polymer film, which is caused by water or organic solvents being used used repeatedly during the manufacturing process, can be prevented and a dimensional stability of the film can be increased.
    Type: Grant
    Filed: November 13, 1990
    Date of Patent: July 21, 1992
    Assignee: Fujitsu Limited
    Inventor: Hiromasa Hoko
  • Patent number: 5069748
    Abstract: This is a structure of, and method for preparation of, molybdenum resistors in a superconductor integrated circuit. It utilizes a pattern superconductor film; applying a titanium film on the patterned superconductor film; and then applying a molybdenum film on the titanium film to provide a titanium-molybdenum, etch-stop interface; applying a patterned resist film on the molybdenum film; etching the exposed molybdenum film to expose a portion of the titanium-molybdenum, etch-stop interface; and oxidizing the exposed titanium-molybdenum, etch-stop interface. The titanium-molybdenum etch stop interface protects the patterned superconductor film and the support (including any other underlayers) and increases processing margins for the etch time.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: December 3, 1991
    Assignee: Westinghouse Electric Corp.
    Inventor: John X. Przybysz
  • Patent number: 5055158
    Abstract: A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas, depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface with the tops of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.
    Type: Grant
    Filed: April 4, 1991
    Date of Patent: October 8, 1991
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Chao-Kun Hu, Mark A. Jaso, Mark B. Ketchen, Alan W. Kleinsasser, Dale J. Pearson
  • Patent number: 5041188
    Abstract: A high temperature superconductor (HTS) fabrication process employs a two level metal deposition sequence for depositing a layer of metal (14, 18) over HTS material (12) to protect the HTS material from subsequent, possibly deleterious, processing steps. The process of the invention provides a capability for both patterning a HTS film material and electrically contacting the film using conventional photolithographic processes. The process of the invention furthermore accomplishes these objectives without degrading the superconducting properties of the film. The two level metal process protects the film from aqueous based processes such as photoresist development. The two level metal process furthermore does not require processes such as aqueous based chemical etching or ion milling of the surfaces of the superconducting film, thereby eliminating at least two processes which are known to degrade the superconducting properties of HTS material.
    Type: Grant
    Filed: June 12, 1990
    Date of Patent: August 20, 1991
    Assignee: Santa Barbara Research Center
    Inventors: James M. Myrosznyk, Jerry A. Wilson, Michael Ray
  • Patent number: 4997522
    Abstract: A system for etching superconducting films of yttrium-barium-copper-oxide (YBa.sub.2 Cu.sub.3 O.sub.2) is disclosed. The etchant comprises ethylenediaminetetraacetic acid of varying concentrations in water or a water/glycerol mixture. The described etchant permits superconducting transition temperatures to remain unaffected within the experimental accuracy of 1.degree. C. Additionally, films do not require reoxygenation after etching, and the etchant is suitable for micropatterning using standard photolithography.
    Type: Grant
    Filed: August 18, 1989
    Date of Patent: March 5, 1991
    Assignee: Bell Communications Research, Inc.
    Inventor: Frough K. Shokoohi
  • Patent number: 4985117
    Abstract: A method of manufacturing Josephson junctions includes steps of high Tc superconductor thin films on a substrates by chemical vapor deposition using raw materials, which includes at least yttrium, barium and copper, serving as vapor generating sources, and fabricating the high Tc superconductor thin films into micro-bridges to produce Josephson junctions.
    Type: Grant
    Filed: January 1, 1990
    Date of Patent: January 15, 1991
    Assignees: Kabushiki Kaisha Riken, Research Development Corporation of Japan
    Inventors: Hideyuki Kurosawa, Toshio Hirai, Hisanori Yamane, Tsutomu Yamashita
  • Patent number: 4913769
    Abstract: The present invention relates to an element comprising a superconductive material or a wiring formation technique. In a thin film wiring board in which a superconductive material is used as a conductor, annealing should be conducted at a high temperature in an oxygen atmosphere after formation of a film in order to convert the conductor portion into a superconductive material, which makes it necessary to use an inorganic oxide as the insulating film. This brought about a problem that the etching of the second and subsequent insulation layers causes a damage to the wiring and insulation layer provided thereunder.In the present invention, an over-etching preventing layer is provided on a wiring layer provided under the second and subsequent insulation layers in order to solve the problem in question.The present invention brings about an effect of realizing the formation of a multi-layered wiring layer by making use of a superconductive material.
    Type: Grant
    Filed: August 4, 1988
    Date of Patent: April 3, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Kanda, Takayoshi Sowa, Tetsuya Yamazaki, Hiroaki Okudaira
  • Patent number: 4891355
    Abstract: A method of producing a superconducting circuit by forming a film having a superconducting phase on a substrate and applying a laser beam to a part of the superconducting phase to cause transition of the part of the superconducting phase into a non-superconducting phase.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: January 2, 1990
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Noriki Hayashi, Satoshi Takano, Kenji Miyazaki, Noriyuki Yoshida