Electrical Computer Or Data Processing System (class 364) Patents (Class 505/829)
  • Patent number: 6563311
    Abstract: A solid-state quantum computing structure includes a d-wave superconductor in sets of islands that clean Josephson junctions separate from a first superconducting bank. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states. A second bank, which a Josephson junction separates from the first bank, can be coupled to the islands through single electron transistors for selectably initializing one or more of the supercurrents in a different quantum state. Single electron transistors can also be used between the islands to control entanglements while the quantum states evolve.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 13, 2003
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 6563310
    Abstract: A solid-state quantum computing structure includes a set of islands that Josephson junctions separate from a first superconducting bank. A d-wave superconductor is on one side of the Josephson junctions (either the islands' side or the bank's side), and an s-wave superconductor forms the other side of the Josephson junctions. The d-wave superconductor causes the ground state for the supercurrent at each junction to be doubly degenerate, with two supercurrent ground states having distinct magnetic moments. These quantum states of the supercurrents at the junctions create qubits for quantum computing. The quantum states can be uniformly initialized from the bank, and the crystal orientations of the islands relative to the bank influence the initial quantum state and tunneling probabilities between the ground states.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: May 13, 2003
    Assignee: D-Wave Systems, Inc.
    Inventor: Alexandre M. Zagoskin
  • Patent number: 5757650
    Abstract: The disclosed is a method comprising the steps of displaying entirely a plurality of storehouse facilities in the form of a plan view; informing a storage abnormality when the actual storage location and stock condition are different from that displayed in parallel with displaying the stock condition at each instant; and correcting the stock condition at the time the storage abnormality is informed. Shelves are distinguished using displayed figures in accordance with shelves in which already stored, shelves still remaining empty, and shelves for which storage is prevented; and the stock condition of the storehouse facilities is displayed by specifying any of the facility on the displayed surface.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: May 26, 1998
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Tomimasa Yamashita, Takio Okuno, Katsuhiro Hagino
  • Patent number: 5377126
    Abstract: Apparatus and method for non-contact temperature measurement of a film growing on a substrate which accounts for the change in emissivity due to the change in film thickness. The system employs an adaptively calibrated pyrometer wherein the substrate emittance is continuously computed so that the temperature measurement is accurate regardless of the emittance variation. The new system is easily constructed by adding data processing system software and hardware to conventional pyrometers.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: December 27, 1994
    Assignee: Massachusetts Institute of Technology
    Inventors: Markus I. Flik, Alfredo Anderson, Byungin Choi
  • Patent number: 5146119
    Abstract: A switching circuit which comprises a digital circuit formed of a superconductor, a transmission line connected to the digital circuit through magnetic coupling, and a resistor element disposed in the transmission line for differentiating the output of the digital circuit.
    Type: Grant
    Filed: December 28, 1989
    Date of Patent: September 8, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Ryotaro Kamikawai, Akira Masaki
  • Patent number: 5126598
    Abstract: A Josephson integrated circuit includes a Josephson logic processor operated at a first clock rate, and a latch circuit formed of Josephson devices operated at the first clock rate for receiving output data from the Josephson processor together with a status signal for holding the output data. The latch circuit is supplied with a clear signal for resetting the output data therefrom. In addition, the invention includes therefrom a data output circuit formed of Josephson devices operated in response to a second clock rate that is slower than the first clock rate, wherein the data output circuit has an output terminal and supplied with the output data held in the latch means for passing the output data to the output terminal at the second clock rate. Further, the data output means produces the clear signal at the second clock rate.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: June 30, 1992
    Assignee: Fujitsu Limited
    Inventor: Seigo Kotani
  • Patent number: 4943556
    Abstract: A combination of optical interconnect technology with superconducting matal to form a superconducting neural network array. Superconducting material in a matrix has the superconducting current decreased in one filament of the matrix by interaction of the Cooper pairs with radiation controlled by a spatial light modulator. This decrease in current results in a switch of current, in a relative sense, to another filament in the matrix. This "switching" mechanism can be used in a digital or analog fashion in a superconducting computer application.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: July 24, 1990
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Harold H. Szu