Abstract: The invention relates to a high temperature superconducting electric field effect device which creates a dual grain boundary on a superconducting thin film and employs it as a channel. The device comprises a substrate, a bottom layer formed on a predetermined region of the bottom layer, a dual grain boundary channel region formed on the bottom layer, a high temperature source and a drain formed at both end portions of the channel region on the substrate, a high temperature superconducting thin film channel layer formed a predetermined region on the source, the drain and the substrate, dual grain boundaries formed on the high temperature superconducting thin film channel layer, and a gate insulating layer formed on the dual grain boundary channel region.
Type:
Grant
Filed:
August 8, 1996
Date of Patent:
June 23, 1998
Assignee:
Electronics and Telecommunications Research Institute
Abstract: A read only memory device comprises a first electrode, and a second electrode arranged overlapping with the first electrode so as to be geometrically in connection at the intersection. At least one of the first and second electrodes is formed of a ceramics system high temperature superconductor. A prescribed electrode out of said electrodes which is formed of the high temperature superconductor has a high resistance region for insulating the first and second electrodes from each other at the intersection corresponding to a prescribed stored data.In the manufacturing method, the first and second electrodes are formed and, thereafter, a high resistance region is formed by irradiating focused ion beam.
Abstract: This is a method for making an ohmic connection between a semiconductor and oxide superconductor, the connection being such that current can pass between the semiconductor and the superconductor without going through a degraded portion which is greater than the coherence length of the superconductor. The method can comprise depositing a buffer layer (which is essentially inert to the oxide superconductor) on a first portion of a semiconductor substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer (e.g. of gold or silver) on the oxide superconductor, and depositing a semiconductor contact layer on a second portion of the semiconductor substrate (the semiconductor contact layer being, for example, of aluminum, or a refractory metal silicide); and depositing a layr (e.g.
Abstract: A semiconductor device which includes either a single semiconductor chip bearing an integrated circuit (IC) or two or more electrically interconnected semiconductor chips, is disclosed. This device includes interconnects between device components (on the same chip and/or on different chips), at least one of which includes a region of superconducting material, e.g., a region of copper oxide superconductor having a T.sub.c greater than about 77K. Significantly, to avoid undesirable interactions, at high processing temperatures, between the superconducting material and underlying, silicon-containing material (which, among other things, results in the superconducting material reverting to its non-superconducting state), the interconnect also includes a combination of material regions which prevents such interactions.
Type:
Grant
Filed:
September 9, 1987
Date of Patent:
June 6, 1989
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories