Abstract: An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program memory into which a control program is written is serially connected to an auxiliary microprocessor including an auxiliary nonvolatile program memory. The microprocessor and the auxiliary microprocessor function in cooperation to control on-vehicle electric load groups in response to input signals from on-vehicle sensor groups and on-vehicle analog sensor group. The nonvolatile program memory and the microprocessor are subjected to runaway monitoring performed by a watchdog timer and to an external checksum diagnosis performed periodically by the auxiliary microprocessor. If an anomaly occurs in the runaway monitoring, the external checksum diagnosis, and a checksum interval, parts of electric loads are cut off of power supply by load power relay.

Abstract: An image signal processing apparatus includes two JPEG codecs. A plurality of frames of image signals periodically input from a multiplexer are individually compressed by the two JPEG codecs, and the compressed image signals are recorded on a hard disk by an HDD. Furthermore, the plurality of frames of the compressed image signals reproduced from the hard disk are individually expanded by the two JPEG codecs, and the expanded image signals are output to a monitor. Herein, each of the JPEG codecs selectively executes individual compression of the plurality of frames of the image signals and individual expansion of the plurality of frames of the compressed image signals. A CPU makes the JPEG codecs perform the compression process prior to the expansion process.

Abstract: A system and method for updating a source copy of an ordered list (the source list) comprising a plurality of list items according to modifications made to the order of the list items in a local copy of the ordered list (the local list) is provided. Each list item includes an order value. The order of the list items is determined according to the order values. To update the source list, the list items that have been moved in the local list are identified and placed on a temporary list, retaining the ordinal position in the local list. For each list item in the temporary list, the list item is placed back in the local list and its order value is set according to the average of the previous list item's order value and the subsequent list item's order value. The list item is then written to the source list.

Abstract: A building control system, such as an HVAC system, has a field unit incorporating a control panel (a field panel) with a local user interface allowing user selected parameters for collecting trend information when the system detects a change of value for a point in the system or a timed instruction in the memory of the field panel to begin collecting trend data for a point. The resulting trend data collected by the field panel can be uploaded to a workstation in the building control system, where the trend data can be formatted into a report, and then digitally authenticated.

Abstract: A control system for calculating control commands for actuators in an aircraft, wherein the control commands are calculated by computers distributed in the craft in dependence on input signals containing parameters that serve as the basis for said commands, wherein a computer (C) is arranged at each respective local actuator (A) and, together with the actuator (A), forms a servo node (S) where the computer (C) receives input signals via data bus (B), whereby the computer (C) in each servo node (S) calculates control commands for the local actuator (A) based on one or more sets of control laws in dependence on received parameters, and wherein the computer (C) calculates, in a corresponding manner, control commands for at least one additional actuator (A) in another servo node (S), and wherein a choice of control commands is used as the control command (7) for the actuator (A) locally in each servo node (S) in dependence on a comparison between the control commands (4) calculated locally in the servo node (S) a

Abstract: The hardware of the present invention must be structured with the Brownian motion equation, Bayes' equation and its matrices as integral components. All data are input to a common bus bar. All data are then sent to all nodes simultaneously. Each node will have coded gates to admit the proper data to the appropriate matrix and Bayes' equation. Then, as the data are processed, they will be sent to a central data processing unit that integrates the data in the Brownian motion equation. The output is displayed in linguistic terms or in digital form by means of fuzzy logic.

Abstract: The image-processing apparatus includes n image processing sections which receive n consecutive pixel data items that are respectively input with the same timing and which respectively process the respective input pixel data items with the same timing, and a control section that controls the n image processing sections. Each of the image processing sections are capable of being set to one of a first operation mode allowing data communication with the controlling section and a second operation mode allowing only reception from the aforementioned controlling section, one of the image processing sections is set to the first operation mode, and n?1 of the image processing sections are set to the second operation mode.

Abstract: A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Abstract: An apparatus, system and process is provided for communicating safety-related data, over an open system, from a sender to a receiver. Safety-related components, including function blocks, flexible function blocks, resource blocks and transducer blocks, as well as, safety-related objects are provided. Also, an extended safety-related protocol provides for authenticating communications between safety-related components over an existing black channel, such as one using a fieldbus Architecture.

Abstract: Disclosed are techniques for effective wireless device access and management via device capability integration. A method for constructing a machine using a plurality of devices selected from a group of devices, wherein each device in the group is configurable for providing short-range wireless communication, includes the steps of: starting an application template in response to an instruction from a user; analyzing the template to determine one or more capabilities required for the machine; searching in the group for devices substantially matching at least one of the capabilities; and integrating the matching devices into the machine.

Abstract: An appearance inspection apparatus is composed of a memory 14, a thread generator and a plurality of CPUs 10 to 13. The memory 14 stores image data of an appearance of an IC. The thread generator generates a thread in which a procedure is described for independently processing the image data stored in the memory 14 and storing the processing result into the memory 14. The plurality of CPUs 10 to 13 for executing the plurality of threads generated by the thread generator, in parallel. Thus, this can provide an appearance inspection apparatus and an appearance inspection method that can execute an appearance inspection at a high speed, irrespectively of a simple configuration.

Abstract: An electronic control system, such as a field oriented control system, is provided, including a device to be controlled; an application control arrangement including a plurality of functional blocks configured to perform a cascaded computation, the application control arrangement configured to generate control signals to control the device in accordance with the cascaded computation; and a master control arrangement communicatively coupled to the application control arrangement and configured to communicate parameter inputs and an initial start pulse to the application control arrangement, the initial start pulse being operable to initiate the cascaded computation; wherein each of the functional blocks is configured to generate output data and a done pulse in accordance with a predetermined partial computation, the output data being valid and stable at least for a duration of the done pulse, the predetermined partial computation of each of the functional blocks being performed as a function of input data and

Abstract: A process plant includes a safety system that is physically and logically integrated with a process control system such that the safety system and the process control system can use common communication, diagnostic and display hardware and software within the process plant while still providing functional isolation between the safety system controllers and the process control system controllers. This integrated process control and safety system uses a common data communication structure for both the safety system and the process control system so that applications can send data to and receive data from devices in either system in the same manner, e.g., using the same communication hardware and software.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: A networking infrastructure for an operating room, comprising a plurality of medical devices, each device of which is connected through a single communication channel to the network, wherein each device may be controlled through a local interface, or through a remote interface available through the network. Furthermore, the networking infrastructure operates in robust manner with respect to the removal of a communication channel to the network associated with the removal of medical device from the network, or with respect to the addition of a communication channel to the network associated with the addition of a medical device to the network.

Abstract: A parallel flash programming system for use in motor vehicle assembly includes an input receptive of information relating to a predetermined number of processors connected to a system bus, processor flash programming attributes, and system bus attributes. An incremental flash programming times determination module is adapted, based on the information, to determine incremental flash programming times of a processor in relation to multiple interframe wait times respective of multiple parallel flash programming schema in accordance with the predetermined number of processors. A global flash programming time resolution module is adapted to determine, based on incremental flash programming times respective of multiple processors of the predetermined number, an assignment of the multiple processors to a number of parallel programming tracks yielding a global flash programming time in accordance with predetermined criteria.

Abstract: A power distribution assembly (PDA) includes a plurality of power modules that are installed within a chassis that is mounted to a vehicle, such as an aircraft. The power modules are used to control aircraft systems such as braking, navigation, or temperature control systems. The PDA includes first and second microprocessors that have separate serial busses that are in communication with each of the power modules. A first power supply powers the first microprocessor and each of the power modules and a second power supply powers the second microprocessor and each of the power modules independently from the first power supply. Additionally the first and second microprocessors communicate with each other via both serial busses to determine which microprocessor is in active control and which microprocessor is on standby in addition to monitoring the health of the other microprocessor.

Abstract: A microprocessor system for safety-critical control operations includes at least three central units which are preferably located jointly on one chip and execute the same program. Further, there is provision of read-only memories and random-access memories with additional memory locations for test data, input and output units and comparators which check the output signals of the central units for correlation. The central units are interconnected by way of bus systems and bypasses which enable the central units to jointly read and process the existing data, including the test data and commands, according to the same program. The central units are extended by redundant periphery units into two complete control signal circuits and are interconnected in such a manner that, upon failure, the faulty central unit is identified by a majority decision and an emergency operation function is maintained.

Abstract: A method and apparatus for statistical compilation is presented. The statistical compilation circuit includes a multi-bank memory that stores a plurality of statistics, where a statistic component portion for each statistic is stored in each of the plurality of banks in the multi-bank memory. An arbitration block is operably coupled to receive at least one statistical update stream. Each statistical update stream includes a plurality of statistical updates, where each statistical update includes a statistic identifier and an update operand. The arbitration block schedules received statistical updates to produce a scheduled update stream. A control block operably coupled to the arbitration block and the multi-bank memory executes the updates included in the scheduled update stream. The control block retrieves the current value of one of the statistic component portions from one of the memory banks and combines the current value with the update operand of a corresponding statistical update.

Abstract: An ECU is equipped with an engine control microcomputer for executing engine control and a throttle control microcomputer for executing throttle control. The engine control microcomputer is programmed to execute a monitor program. A time in the engine control microcomputer is set with a predetermined time each time the monitor program is executed normally. The timer switches automatically its output logic level at a port from high to low, when the time count reaches zero. When the output logic level is switched to low, a throttle motor is disabled.

Abstract: A system for process control comprises a server digital data processor and a client digital data processor that are coupled by a network, such as the Internet or an Intranet. The server digital data processor, which is additionally coupled to a control/sensing device and any associated interface equipment (collectively, referred to as “process control apparatus”), includes a command processor that transfers information between the network and the process control apparatus. The client digital data processor includes an information client (e.g., a so-called Internet web browser) capable of requesting and receiving an applet from the server digital data processor. The information client, further, defines a hardware-independent and operating system-independent virtual machine environment within the client digital data processor.

Abstract: A serial communication interface (SCI) cable 4 is provided between the slave processor 2 and the master processor 3. Both processors are connected with a communication interface for peripheral units (SPI: Serial Peripheral Interface) which enables fast transmission. The slave processor 2 transmits a transmission request command which requests at least one of data transmission and reception from the command communication section 220 to the master processor 3 through the SCI cable 4.

Abstract: Data bus system having a plurality of control units (1) which interchange messages with one another via a data bus (2) and which are provided for controlling components, the individual control units (1) being of modular design and being fitted in different installation spaces in a technical product, characterized in that the control units (1) are designed as distributed control units having individual modules (3, 4, 5a, 5b, 6), a plurality of which can be arranged independently of one another and some of which are connected via an internal data bus (7), and the individual modules (3, 4, 5a, 5b, 6) in a control unit produce data and signals for driving the same component/components (8, 9, 10, 11) with individual modules identical in terms of hardware being provided in different control units (1), and in that at least two different types of individual modules (3, 4, 5a, 5b, 6) are provided in a plurality of control units (1), with one output-stage individual module (5a, 5b) provided in a plurality of control un

Abstract: A circuit for processing a first image including two image supply blocks, two image processing units, a control unit and a plurality of buses. The image supply blocks assert selected lines of image data onto a respective one of first and second plurality of buses. The image processing units each process the data according to respective algorithms and provide respective update ok signals that each indicate that the respective image processing unit has completed use of the first sub-portion of data. The image supply blocks provide respective update signals to the image processing units in response to the update ok signals from both of the image processing units, transfer data from the second sub-portion to the first, and assert new data on the second sub-portion. Each image processing unit, in response to receiving both update signals, changes state to track the data without losing bus cycles to maintain performance.

Abstract: In a method and device for monitoring speed, in particular for monitoring the rotation speed of an electric machine, two processors are employed which monitor the speed using different checking modes and cross-compare results. The first processor executes a conventional control algorithm and checks on the basis of an estimated or measured value of the speed whether a speed limit has been exceeded. The second processor determines the actual output frequency, which is also indicative of the speed, of a converter either from actual current values, which are measured anyway, or by reconstructing the voltage from control signals of transistors. Both processors thus monitor if a rotation speed limit has been exceeded and/or execute corresponding response actions. The method also recognizes faults in the power section based on the evaluation of the phase current. The system can also be designed to manage pulling loads.

Abstract: A distributing node initiates an install control program in receiving nodes, and then broadcasts or multicasts program data to the receiving nodes. Thereby, the installation of the program into the nodes is carried out in shorter time. In this event, the distributing node and the receiving nodes buffer the program data in units of data block sizes of storage devices associated therewith. The distributing node executes in parallel the processing for storing data read from the storage device in a buffer, and the processing for reading the data from the buffer and broadcasting or multicasting the read data to the receiving node. The receiving node executes in parallel the processing for storing the data received from the distributing node in a buffer, and the processing for reading the program data from the buffer and storing the program data in the storage device thereof.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: The present invention provides a large-scale carrying system that allows the operation of only a part of the system which has been completely constructed, while concurrently allowing the construction of a part of the system which has not been constructed yet. A carrying system comprises a carrying vehicle system 3 which carries an article to a predetermined location using a carrying vehicle, an article housing system 4 in which the article is temporarily housed for storage, an integrating controller 5 which integrally controls a system set 2 comprising at least one carrying vehicle system 3 and at least one article housing system 4, and an auxiliary controller 14 which can integrally manage at least part of the system set. The integrating controller 5 and the auxiliary controller 14 are connected together through a network. It is thus possible to transfer data on the part of the system set 2 which is integrally managed by the auxiliary controller 14, to the integrating controller 5.

Abstract: A supervisory parallel switching device is designed for use with a CIM system including a host computer unit connected via an extended computer integrated unit to at least one equipment unit through an SECS-compliant (Semiconductor Equipment Communication Standard) serial communication link, for the purpose of allowing the equipment unit to be continuously under computer control even in the event of an unanticipated shutdown to the extended computer integrated unit.

Abstract: A control system and method are provided having a control agent controlling a user interface, an actuator control, a programming control, and a job control. The control system is used with a programming system which has an actuator control for opening and closing sockets and a programming mechanism for performing a programming operation on the programmable devices at a high rate of speed.

Abstract: An electronic control apparatus for a control object makes a mode check before each program part is retrieved even at a predetermined start timing, and inhibits a retrieval of program parts unnecessary for operation modes including a normal mode, inspection mode or rewrite mode. As it is not necessary to check the mode in the processing of each program part, the control processing for the control object can be executed efficiently in each mode. As the program parts unnecessary for the specified operation mode is not retrieved either in the specified operation mode, the processing efficiency is increased.

Abstract: A central processor of a factory automation system which has an application program 13 for issuing instructions to a plurality of controllers 1 to 4 in parallel and controlling the controllers 1 to 4, a plurality of interface 30a, 30b for connecting the application program 13 and the controllers 1 to 4, and interface control 35c for dynamically increasing or decreasing the number of the interface 30a, 30b in response to the number of the instructions issued by the application program 13 to the controllers 1 to 4 in parallel.

Abstract: A computer system and method for executing several processes in tandem, that includes a scarce resource, which is accessed by the processes to be executed. A first device is provided for computing the capacity load of the scarce resource, a second device is provided for determining a load responsibility of a process that accesses the scarce resource, and a third device is provided for delaying the execution of a process that accesses the scarce resource depending on each of the capacity load, the critical capacity load of the scarce resource, and the load responsibility of the process. In this way, a blocking of the scarce resource with a limited capacity, and thus of the computer system, can be prevented.

Abstract: A control system including a personal computer (1) for controlling a process. The personal computer (1) includes a communications processor (14), which is connected to a field bus (2). Sensors (3, 4) and/or actuators (5, 6) are connected to the field bus (2). A monitoring unit (16) monitors a cyclic data transmission on the field bus (2). The monitoring unit (16) also causes a PC processor (7) to process data received at the field bus (2) by means of a control program, if at least one predetermined condition is met, e.g., a change in the process data. Thereby, the PC processor (7) is relieved of the burden of continuously polling the process data. The process data are stored in a memory (15). The control system is used, in particular, in communications processors for personal computers.

Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: A distributed control system employs a number of autonomous cooperative units that intercommunicate with bids and counter bids to allocate the production of a product among them. Bidding closure is obtained in an environment where each autonomous cooperative unit can propagate multi-threaded bidding chains, by attaching a response time value to each propagated bid indicating when a response must be received. Sub-bids from that propagated bid forward a reduced version of this response time value that accounts for the sub-bid processing time. Thus, all bidding is concluded within the response time value. Participants in a successful bidding chain are notified so that in the future they may direct bids toward bidding partners that have historically proven successful as part of a successful bidding chain.

Abstract: A control and data transmission installation and a process for transmission of safely-related data in a control and data transmission installation. In accordance with the invention, safety procedures of existing field bus systems, particularly the interbus, are improved in such a way that there is no need either for additional lines for the transmission of control signals or redundant, safety-related units. In the inventive control and data installation, a master control device and a number of bus subscribers each include respective safety-related devices for carrying out predetermined safety functions. The safety-related devices can communicate with each other by way of a field bus.

Abstract: The present invention is a block oriented control system that allows interoperability between devices made by different manufacturers. A block oriented control system is a system which includes a plurality of field devices incorporating a physical layer, communication stack, and user layer, with the field devices being connected by a transmission medium, such as a bus. The physical layer receives signals from the bus and translates the signals into a message for the communications stack, and receives messages from the communications stack and translates the messages into signals for the bus. The communication stack controls the communications between devices operating in the control system. The user layer is a block oriented approach to the system's control functions, and includes function blocks and system management. The function blocks are standardized encapsulations of control functions, such as analog input or proportional/derivative.

Abstract: Disclosed are a data processing apparatus which, by being providing with a software processor for implementing prescribed data processing by software and a hardware processor for implementing the prescribed data processing by hardware, makes it possible to process externally supplied data at high speed, as well as a method of selecting processors efficiently in this data processing apparatus. If data processing has been requested, the time it takes the hardware processor to execute this data processing is acquired using test data. If the time required for processing is less than a predetermined time, the hardware processor is selected to execute processing by hardware. If the time required for processing is equal to or greater than the predetermined time, the software processor is selected to execute processing by software. The appropriate processor is selected depending upon the status of utilization of the software processor and the status of utilization of the hardware processor.

Abstract: For optimizing data processing in a safety system for a machine, such as a robot or the like, while permitting a simple, safety-uncritical diagnosis, the invention provides a process for processing safety-relevant data in a safety system for a machine, such as a robot or the like, with several nodes connected in a ring and which is characterized in that in parallel in each node are processed the data received by it, which are retransmitted to the next node and for diagnosis purposes a diagnostic unit is provided which passively receives the data present in at least one node.

Abstract: A search system and method for controlling multiple agents to optimize an objective using distributed sensing and cooperative control. The search agent can be one or more physical agents, such as a robot, and can be software agents for searching cyberspace. The objective can be: chemical sources, temperature sources, radiation sources, light sources, evaders, trespassers, explosive sources, time dependent sources, time independent sources, function surfaces, maximization points, minimization points, and optimal control of a system such as a communication system, an economy, a crane, and a multi-processor computer.

Abstract: A vehicle computer arrangement, particularly for a motor vehicle, a train, an airplane or a ship, which is provided with at least two computers (10, 20) and at least one data bus (60) via which the at least two computers (10, 20) are interconnected, and in which at least one monitoring circuit (40) is arranged between a first computer (10) and a second computer (20) of the at least two computers, the monitoring circuit checking whether a data exchange between the first and the second computer is permitted for data processed or to be processed in the first or the second computer, and blocking the data exchange in the event that it is not permitted for the monitored data.

Abstract: Apparatus, methods, data structures, and systems are provided for subdividing input data associated with a first software program into job quanta, wherein each job quantum is operable to be executed by a separate software program residing on a different processing element from the first software program. The first software program and the separate software program execute substantially in parallel and output data associated with the executions of the programs are assembled into a single coherent presentation or results data. Moreover, the software programs may be threaded or non-threaded.

Abstract: A method, apparatus, article of manufacture, and a memory structure for selecting a coordinator node to configure a parallel processing system having a plurality of interconnected nodes. The method comprises the steps of: multicasting a best available node list and a best desired node list from each node to each node; receiving the best available node list and the best desired node list from each node in each node; and selecting the coordinator node as the node originating a best available node list that includes every node in the desired node list. If no node is identified as originating a best available node list that includes every node in the desired list, the node originating a best available node list that includes the greatest number of nodes in the desired node list is selected as the coordinator node.

Abstract: A local synchronization type parallel pulse signal processing circuit has a plurality of neurons connected to each other based on a predetermined rule and disposed in parallel, executing a predetermined arithmetic process with respect to input signals and outputting, a phase synchronization signal generation circuit outputting phase synchronization signals to the predetermined vicinal neurons, and a synchronization detection portion detecting synchronization within an allowable phase difference between the outputs of the predetermined vicinal neurons. The phase synchronization signal generation circuit functions also as a neuron executing the predetermined arithmetic process and outputting in accordance with a result of the synchronization detection by the synchronization detection portion. With this architecture, the synchronization circuit operating stably without any contradiction in a way that brings neither an increase in circuit scale nor an increase in consumption of electric power, is actualized.

Abstract: A data processing system of this invention comprises a first processing unit for performing first data processing, a second processing unit for performing second data processing and a fetch unit for issuing an instruction code fetched from a code memory to the first processing unit if the fetched instruction code is a type 1 instruction code for the first processing unit and issuing the fetched instruction code to the second processing unit if the fetched instruction code is a type 2 instruction code for the second processing unit. In addition, the fetch unit simultaneously issues a type 1 instruction code and a type 2 instruction code to the first and the second processing units respectively if the next instruction code is a different type of instruction code to the fetched instruction code and simultaneous issuing is possible.

Abstract: An efficient DSP or MPU is combined with efficient DRAM on a single IC die. To optimize the embedded memory, the chip includes wide-band connections to DRAM. Row and column addresses of DRAM can be applied at the same time using wide address busses. Additional metal lines lower the resistance of the word line in the DRAM circuits. For certain process steps, the processor block is masked off and the process steps unique to the fabrication of memory are performed on the memory block, and vice-versa. Process steps which are common to the processor and memory blocks can be performed simultaneously on the processor and memory blocks without masking off either block. Certain process steps can be employed in the fabrication of the one of the two processor and memory blocks in addition to or in lieu of processes normally used in the fabrication of that block. An electronic component (e.g.

Abstract: Database tables are unloaded by launching a number of threads corresponding to a number of export directories located on separate storage devices that maintain the database tables. Each thread is assigned a database table to unload, and data unloaded from each database table is stored in a corresponding export directory. The data is unloaded from each database table by reading data storage blocks from each table and storing the data logs in the export directory. Each thread is handled by a separate process in a Symmetrical Multi-Processing (SMP) environment. The process is repeated until each database table has been unloaded. The data is then loaded into database tables by first creating a number of temporary tables corresponding to the number of threads, reading a set of data stored in the export directory and storing the data read in a corresponding of the temporary tables by launching a load process for each temporary table.

Abstract: A data processing system and method are described for creating a virtual partition within an existing partition within a hard disk drive included within the system. A first master boot record is written which includes a partition. The partition defines a first file system to be utilized by the hard drive. A file is created within the partition. The first master boot record is temporarily overwritten with a second master boot record without altering the first file system. The second master boot record includes a designation of the file as a second partition. The second partition defines a second file system. The second partition is designated as the active partition. The data processing system is booted utilizing the second master boot record. The second partition is a virtual partition within the existing partition.

Abstract: Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image processors to process digital image data, and providing one or more parametric controls within each of the two or more image processors. The aspects further include accessing chosen controls of the one or more parametric controls to modify the two or more image processors for alteration of the image processing.