Abstract: A transceiver for transmitting and receiving full duplex communications includes transmitter and receiver circuitry. The transmitter circuitry transmits from a first location first signals having a first orthogonal function +ln applied thereto on a first channel on a first frequency band to a second location. The receiver circuitry receives at the first location second signals on a second channel on the first frequency band from the second location having a second orthogonal function ?ln applied thereto and the first signals having the first orthogonal function +ln applied thereto on the first channel on the first frequency band from the first location at a same time on the first frequency band. The receiver circuitry only processes received signals including the second orthogonal function ?ln.

Abstract: Various examples of methods and systems are disclosed for correction of phase and amplitude errors that occur in transmission lines connecting transmitter/receiver devices to measurement fixtures. In one example, a method is described that includes using time domain processing to determine a phase shift from the measurement fixture that can occur between calibration measurements and measurements of the specimen under test. In another example, a method is described that includes frequency-domain processing of the signals to obtain both phase and amplitude corrections. Including these phase and amplitude corrections in the calibration procedure can reduce or minimize the errors induced in the measurements when the transmission line(s) experience either temperature changes or physical deflections, among other things.

Abstract: A system for providing full-duplex communications comprises a first transceiver for simultaneously transmitting first signals having a first orthogonal function applied thereto on a first channel and simultaneously receiving second signals having a second orthogonal function applied thereto at a same time. A second transceiver simultaneously receives the first signals having the first orthogonal function applied thereto on the first channel and simultaneously transmits the second signals having the second orthogonal function applied thereto at the same time. Application of the first orthogonal function to the first signals and application of the second orthogonal function to the second signals prevents interference between the first signals and the second signals.

Abstract: A test system includes: a signal processor configured to generate a plurality of orthogonal baseband sequences; a signal generator configured to supply the plurality of orthogonal baseband sequences to a corresponding plurality of RF transmitters of a device under test (DUT), wherein the RF transmitters each employ the corresponding orthogonal baseband sequence to generate a corresponding RF signal on a corresponding channel among a plurality of channels of the DUT such that the RF transmitters output a plurality of orthogonal RF signals at a same time; a combiner network configured to combine the plurality of orthogonal RF signals and to output a single signal under test; and a single channel measurement instrument configured to receive the single signal under test and to measure independently therefrom at least one characteristic of each of the RF transmitters. Orthogonal RF test signals may be used similarly to test RF receivers of the DUT.

Abstract: A system for providing full-duplex communications includes a first transceiver for transmitting first signals having a first orthogonal function of a plurality of orthogonal functions applied thereto on a first channel and receiving second signals having a second orthogonal function of the plurality of orthogonal functions on a second channel at a same time. A second transceiver transmits the second signals having the second orthogonal function of the plurality of orthogonal functions on the second channel and receives the first signals having the first orthogonal function of the plurality of orthogonal functions on the first channel at the same time. The first channel having the first orthogonal function applied thereto and the second channel having the second orthogonal function applied thereto do not interfere with each other enabling full duplex transmissions between the first transceiver and the second transceiver.

Abstract: An information processing apparatus, connected to a management server managing a set value used among a plurality of information processing apparatuses, can perform an appropriate process according to the situation of an information processing system and can prevent wasteful power consumption thereof. A set value acquired from the management server and changed by the information processing apparatus is transmitted to the management server, but when the transmission fails, the transmission of the changed set value is retried, and it is switched according to a classification of the set value to be transmitted whether the retry is stopped or is continued.

Abstract: A method for recording pulse signals which allows the reconstruction of a time reference. The time of every pulse signal event can be determined by counting sampling result bits preceding the respective sampling result bit using the known sampling frequency. For this purpose, every period of the sampling frequency is associated with a bit representing the respective sampling result and the sampling result bits are stored one by one and per channel in data blocks. The sampling frequency is preferably higher than a pixel clock, a sampling result bit associated with a flank of the pixel clock being marked. The pixel clock can thus be synchronized with the individual events exactly per sampling period. The invention further relates to the field of fluorescence correlation spectroscopy using confocal microscopes or laser scanning microscopes.

Abstract: Disclosed is a calibration method using a vector network analyzer including: acquiring impulse responses for a direct wave and a multi-reflected wave generated by transmitting and receiving devices connected to a measuring port of the vector network analyzer; setting a gate only for an impulse response for the direct wave among the impulse responses for the acquired direct wave and multi-reflected wave; and transforming the impulse response for the direct wave to which the gate is set into a frequency domain signal and defining the transformed frequency domain signal as calibration results.

Abstract: An impulse response measurement with high precision is made possible with a simple device or signal processing, even if sampling clocks on the transmitting side and the receiving side are asynchronous at the time of measuring an impulse response of a measured system. An impulse response measuring method includes an input signal generating step of generating an input signal of an arbitrary waveform to be input to a measured system by using a synchronization signal having a first sampling clock frequency, a signal converting step of performing conversion on a measured signal output from the measured system into a discrete value system by using a synchronization signal having a second sampling clock frequency, and an inverse filter correcting step of correcting at least a phase of an inverse filter which is an inverse function of a function showing a frequency characteristic of the input signal according to a frequency ratio of the first sampling clock frequency and the second sampling clock frequency.

Abstract: A method of directly measuring hydrogen permeability of a film is provided. The method of evaluating a film includes acquiring, with respect to a specimen including a plurality of films stacked on each other, ion dose-dependence data of intensity of ?-beam generated by hydrogen resonant nuclear reaction, and fitting the data with a functional equation of the ion dose.

Abstract: A variable impedance sense (VIS) circuit (400) can detect a drift in the impedance of variable impedance circuits due to changes in operating conditions. Adjustments to binary impedance setting codes are made in response to a detected drift only when such changes do not increase a worst case variation from a target impedance. Adjustments can also be made in response to a detected input offset polarity.

Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set an reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.

Abstract: A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.

Abstract: A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.

Abstract: A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.

Abstract: Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the electronic device at the first frequency and transmitting data to the electronic device at a second frequency. The second frequency is equal to a product of the first frequency and a frequency offset value.

Abstract: An electronic system for testing a material includes at least one module for mechanically mounting on the material. The module includes a signal generator for generating a signal generator signal. The module also includes a stimulus signal delivering device (SSDD) and an SSDD circuit for providing a device signal derived from said signal generator signal to the material. The module also includes a sensor and a sensor circuit for receiving an interaction signal derived from interaction of the device signal with the material.

Abstract: There is provided a detection apparatus including a transition point detecting unit operable to receive the output signal to detect the point of transition, a timing comparing unit operable to detect the signal level of the output signal in front of or behind the point of transition in the output signal, and a correction unit operable to compensate the timing of the point of transition detected from the transition point detecting unit based on the signal level of the output signal detected from the timing comparing unit.

Abstract: The method comprises generating an acoustical volume velocity Q in the listening position, measuring a response quantity p, such as sound or vibration, at a suspected source position resulting from the volume velocity Q, and determining the acoustical transfer impedance Zt as the response quantity p divided by the acoustical volume velocity Q, Zt=p/Q. According to the invention the acoustical volume velocity Q is generated using a simulator (10) simulating acoustic properties of at least a head of a human being, the simulator comprising a simulated human ear (14, 15) with an orifice in the simulated head and a sound source (30) for outputting the acoustical volume velocity Q through the orifice. The output volume velocity Q from the orifice of an ear is estimated from measurements with two microphones inside the corresponding ear canal.

Abstract: One embodiment of the present invention provides a system that facilitates high-sensitivity detection of an anomaly in telemetry data from an electronic system using a telemetric impulsional response fingerprint of the telemetry data. During operation, the system applies a sudden impulse step change to one or more operational parameters of the electronic system during operation. Next, the system generates a three-dimensional (3D) telemetric impulsional response fingerprint (TIRF) surface from a dynamic response in the telemetry data to the sudden impulse step change. The system then determines from the 3D TIRF surface whether the telemetry data contains an anomaly.

Abstract: Abnormality diagnosing method in which a highly reliable abnormality diagnosis of an image forming apparatus can be initiated immediately following the delivery of the image forming apparatus to a user.

Abstract: A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance.

Abstract: A method for use with a test system having sites that hold devices under test (DUTs) includes executing a first site loop to iterate through the sites, where the first site loop includes an instruction to program hardware associated with at least one of the sites, and executing a second site loop to process data received from the DUTs, where the second site loop and the first site loop have a same syntax.

Abstract: A method and apparatus for designing perturbation signals to excite a number of input variables of a system, in order to test that system for the purpose of obtaining models for the synthesis of a model-based controller. The method begins with providing input parameters of the system. A plurality of binary multi-frequency (BMF) signals are generated based on these input parameters and the frequency spectra of these BMF signals are calculated. One BMF signal is selected out of the set of BMF signals so that the frequency spectrum of the selected BMF signal most closely matches a desired frequency spectrum specified by the input parameters. The selected BMF signal is used as a first perturbation signal for testing the system. The selected BMF signal is also shifted by predetermined amounts of samples to create delayed copies of the original BMF signal to be used as additional perturbation signals.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An exposure apparatus includes a motion control system, the motion control system including a structure, a plurality of actuators to apply forces to the structure, respectively, and a plurality of sensors to sense motion states of the structure, respectively. The apparatus includes a pseudo-random signal generator to generate a plurality of pseudo-random signals and to apply the plurality of pseudo-random signals to the plurality of actuators, the plurality of pseudo-random signals being equal in number to a number of degrees of freedom of the motion control system, a storage unit to store a first plurality of time-series data obtained by the plurality of sensors with a second plurality of time-series data corresponding to the plurality of pseudo-random signals, and a characteristic deriving unit to derive a characteristic of the motion control system based on the first and second plurality of time-series data.

Abstract: An apparatus for sampling a power supply current value for performing frequency analysis of the power supply current flowing in an integrated circuit with a test signal applied to the integrated circuit has a power supply generating a prescribed supply of power for the integrated circuit (DUT: device under test), a current detection means for observing the power supply current value supplied from the power supply to the DUT, a test signal generation means for generating a prescribed test signal to be applied to an input/output terminal other than a power supply terminal of the DUT and for generating a test signal application signal during application of the test signal to the DUT, a sampling means for sampling the power supply current value signal, a sampling time determining means for instructing the sampling means with regard to the start and end timing for sampling, based on the test signal application signal, a sampling data storage means for storing data sampled by the sampling means, a Fourier transform

Abstract: In accordance with our invention, for two mixture-type probability distribution functions (PDF's), G, H, G ? ( x ) = ? i = 1 N ? ? i ? g i ? ( x ) , ? H ? ( x ) = ? k = 1 K ? ? k ? h k ? ( x ) , where G is a mixture of N component PDF's gi (x), H is a mixture of K component PDF's hk (x), ?i and ?k are corresponding weights that satisfy ? i = 1 N ? ? i = 1 ? ? and ? ? ? k = 1 K ? ? k = 1 ; we define their distance, DM(G, H), as D M ? ( G , H ) = min w = [ ? ik ] ? ? i = 1 N ? ? k = 1 K ? ? ik ? d ? ( g i , h k ) where d(gI, hk is the element distance between component PDF's gi and hk and w satisfie ?ik?0, 1?i?N, 1?k?K; and ? k = 1 K ? ? ik = ? i , 1 ? i ? N , ? i = 1 N ? ? ik = ? k , 1 ? k ? K . The application of this definition of distance to various sets of real world data is demonstrated.

Abstract: A method and system for performing integrated adjustable short-haul/long-haul time domain reflectometry (TDR). A TDR pulse count is set to a predetermined number. Next, a TDR pulse is transmitted through a cable. The width of the TDR pulse is a function of the multiplication of the TDR pulse count with the period of a TDR clock. It is then determined whether the TDR pulse has been reflected back. If the TDR pulse has not been reflected, the TDR pulse count is successively increased to successively increase the width of the transmitted TDR pulse until a reflection is detected—indicating an open in the cable. Furthermore, it eliminates false detections of cable opens. Moreover, the system can be combined into a line interface unit (LIU) integrated circuit such that TDR functionality can be performed automatically without the use of a technician.

Abstract: A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense amplifiers to compare a bit line voltage to a series of reference voltages and then determines upper and lower limits of a range of range of reference voltages for which sensing operation provide inconsistent results. One embodiment uses an output signal of a sense amplifier to control a pull-down transistor of an I/O line and alternative precharging schemes for the I/O line allow determining both limits using the same compression circuitry to process a result value stream on the I/O line.

Abstract: Embodiments of the invention relate to performing integrated adjustable short-haul/long-haul time domain reflectometry (TDR). A TDR pulse count is set to a predetermined number. Next, a TDR pulse is transmitted through a cable. The width of the TDR pulse is a function of the multiplication of the TDR pulse count with the period of a TDR clock. It is then determined whether the TDR pulse has been reflected back. If the TDR pulse has not been reflected, the TDR pulse count is successively increased to successively increase the width of the transmitted TDR pulse until a reflection is detected—indicating an open in the cable. Furthermore, embodiments of the invention eliminate false detections of cable opens. Moreover, embodiments of the invention can be combined into a line interface unit (LIU) integrated circuit such that TDR functionality can be performed automatically without the use of a technician.

Abstract: A circuit board, for use with a high speed backplane, includes transmitter and receiver with circuitry for correcting for multipath signal errors. A training sequence that is often a pseudo-random signal is transmitted by the transmitter on a first circuit board to a receiver located on a second circuit board. The receiver on the second circuit board includes an analog-to-digital signal converter, an equalizer, and a binary digital-to-analog reconverter for receiving the training sequence. The equalizer preferably comprises a series of connected registers having taps in between, a plurality of individual weighting means attached to each of the taps, and a summing means connected to the weighting means. A training sequence is transmitted from the first circuit board to the receiver on the second circuit board, enabling the receiver to adaptively determine a set of weighting means coefficients for correcting the multipath errors in subsequent signals.

Abstract: A vector network analyzer using sliding correlator techniques and multi-user detection techniques. The sliding correlator technique is based on the time domain sliding effect caused by a small clock frequency offset in the pseudo random code generators of a transmitter and a receiver. A time scaled version of the impulse response of the device under test can be obtained from the time domain slided pseudo random code signals by using a correlator. A multi-user detection method is introduced using two uncorrelated pseudo random codes. One of the uncorrelated pseudo random codes measures the D.U.T. and another code is a reference channel. These codes can be demodulated and despread with one receiver module. A Fast Fourier Transform of the measured impulse response is the frequency response of the measured signal.

Abstract: The invention is a method of measuring transfer functions of a physical system using a wideband excitation signal by exciting the system with a low-power, wide band input signal that has a rich frequency content over a wide band and using a stochastic process to derive a system transfer function over the excitation signal bandwidth.

Abstract: An application specific automated test equipment system for source synchronous bus interface devices is described. A native interface board is provided to interface an automated test unit and a device under test. The native interface board is configured with devices selected to recreate a native environment of the device under test. A first clock drives the devices on the native interface board. A second clock drives the device under test. The second clock signal is derived from the first clock signal to form a substitute clock signal that can be adjusted in relation to the first clock signal. Input and output timing relationships of the device under test are determined by altering the arrival time of the substitute clock at the device under test with respect to the timing of the first clock signal.

Abstract: The invention relates to a method for the determination of the impulse response g(t) of a broad band linear system. The method can be used for the application of high frequency technology. For a test signal, a maximum length binary sequence (MLBS) is employed. The measured signal, obtained by the system, is sampled under maintenance of the sample theorem whereby the sampling clock in accordance with the invention is obtained directly from that high frequency clock pulse which is used for the generation of the MLBS. The digitized measured signal is then subjected to a fast Hadamard-transformation for calculation of the impulse response. The invention furthermore, provides a measuring circuit which carries out this method.

Abstract: The invention relates to a method for determining the transmission characteristics (H(jf)) of an electric line (2) in an ISDN system, in which a test signal (m(t)) is applied to the line (2) at one end, and at the other end of the line (2) the received signal (g(t)) produced owing to the test signal (m(t)) is evaluated.In order to be able to carry out such a method using a test signal having a crest factor of one with relatively little cost, use is made as test signal of a binary, bipolar random number sequence signal (m(t)) having the crest factor of one, and during a time interval corresponding to the period of the test signal (m(t)) the received signal (g(t)) is scanned and subjected to a Fourier transformation to obtain a spectral signal (G(jf)); the latter is complexly multiplied by a reference spectrum Mi(jf) to obtain an output signal (H(jf) which represents a measure of the transmission characteristics of the line (31).

Abstract: A method simulating the filtering of a current pulse in a series of pulses. The method includes receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current pulse as the last in the series of n+1, each pulse address being in a range of m values; storing the n pulses addresses prior to the current pulse address; building a composite address from the current pulse address and the prior n pulse addresses and applying the composite address to read a pulse shape from a memory of at least m.sup.n+1 pulse shapes. Also, apparatus issuing high speed pulses of programmable length.